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vm: fix % result when dividing by 0
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parent
415c599310
commit
dea7f37553
@ -1270,7 +1270,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / right
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else left / right
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}
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}
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"%" -> {
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"%" -> {
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if(right==0.toUByte()) 0xffu
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if(right==0.toUByte()) 0u
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else left % right
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else left % right
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}
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}
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else -> throw IllegalArgumentException("operator byte $operator")
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else -> throw IllegalArgumentException("operator byte $operator")
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@ -1286,7 +1286,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / value
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else left / value
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}
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}
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"%" -> {
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"%" -> {
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if(value==0.toUByte()) 0xffu
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if(value==0.toUByte()) 0u
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else left % value
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else left % value
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}
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}
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else -> throw IllegalArgumentException("operator byte $operator")
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else -> throw IllegalArgumentException("operator byte $operator")
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@ -1298,7 +1298,7 @@ class VirtualMachine(irProgram: IRProgram) {
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val left = registers.getUB(reg1)
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val left = registers.getUB(reg1)
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val right = registers.getUB(reg2)
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val right = registers.getUB(reg2)
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val division = if(right==0.toUByte()) 0xffu else left / right
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val division = if(right==0.toUByte()) 0xffu else left / right
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val remainder = if(right==0.toUByte()) 0xffu else left % right
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val remainder = if(right==0.toUByte()) 0u else left % right
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valueStack.push(division.toUByte())
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valueStack.push(division.toUByte())
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valueStack.push(remainder.toUByte())
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valueStack.push(remainder.toUByte())
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}
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}
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@ -1306,7 +1306,7 @@ class VirtualMachine(irProgram: IRProgram) {
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private fun divAndModConstUByte(reg1: Int, value: UByte) {
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private fun divAndModConstUByte(reg1: Int, value: UByte) {
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val left = registers.getUB(reg1)
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val left = registers.getUB(reg1)
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val division = if(value==0.toUByte()) 0xffu else left / value
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val division = if(value==0.toUByte()) 0xffu else left / value
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val remainder = if(value==0.toUByte()) 0xffu else left % value
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val remainder = if(value==0.toUByte()) 0u else left % value
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valueStack.push(division.toUByte())
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valueStack.push(division.toUByte())
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valueStack.push(remainder.toUByte())
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valueStack.push(remainder.toUByte())
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}
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}
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@ -1315,7 +1315,7 @@ class VirtualMachine(irProgram: IRProgram) {
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val left = registers.getUW(reg1)
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val left = registers.getUW(reg1)
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val right = registers.getUW(reg2)
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val right = registers.getUW(reg2)
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val division = if(right==0.toUShort()) 0xffffu else left / right
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val division = if(right==0.toUShort()) 0xffffu else left / right
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val remainder = if(right==0.toUShort()) 0xffffu else left % right
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val remainder = if(right==0.toUShort()) 0u else left % right
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valueStack.pushw(division.toUShort())
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valueStack.pushw(division.toUShort())
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valueStack.pushw(remainder.toUShort())
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valueStack.pushw(remainder.toUShort())
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}
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}
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@ -1323,7 +1323,7 @@ class VirtualMachine(irProgram: IRProgram) {
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private fun divAndModConstUWord(reg1: Int, value: UShort) {
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private fun divAndModConstUWord(reg1: Int, value: UShort) {
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val left = registers.getUW(reg1)
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val left = registers.getUW(reg1)
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val division = if(value==0.toUShort()) 0xffffu else left / value
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val division = if(value==0.toUShort()) 0xffffu else left / value
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val remainder = if(value==0.toUShort()) 0xffffu else left % value
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val remainder = if(value==0.toUShort()) 0u else left % value
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valueStack.pushw(division.toUShort())
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valueStack.pushw(division.toUShort())
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valueStack.pushw(remainder.toUShort())
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valueStack.pushw(remainder.toUShort())
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}
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}
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@ -1337,7 +1337,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / right
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else left / right
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}
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}
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"%" -> {
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"%" -> {
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if(right==0.toUByte()) 0xffu
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if(right==0.toUByte()) 0u
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else left % right
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else left % right
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}
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}
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else -> throw IllegalArgumentException("operator byte $operator")
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else -> throw IllegalArgumentException("operator byte $operator")
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@ -1389,7 +1389,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / right
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else left / right
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}
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}
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"%" -> {
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"%" -> {
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if(right==0.toUShort()) 0xffffu
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if(right==0.toUShort()) 0u
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else left % right
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else left % right
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}
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}
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else -> throw IllegalArgumentException("operator word $operator")
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else -> throw IllegalArgumentException("operator word $operator")
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@ -1405,7 +1405,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / value
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else left / value
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}
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}
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"%" -> {
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"%" -> {
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if(value==0.toUShort()) 0xffffu
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if(value==0.toUShort()) 0u
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else left % value
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else left % value
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}
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}
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else -> throw IllegalArgumentException("operator word $operator")
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else -> throw IllegalArgumentException("operator word $operator")
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@ -1422,7 +1422,7 @@ class VirtualMachine(irProgram: IRProgram) {
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else left / right
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else left / right
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}
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}
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"%" -> {
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"%" -> {
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if(right==0.toUShort()) 0xffffu
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if(right==0.toUShort()) 0u
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else left % right
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else left % right
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}
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}
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else -> throw IllegalArgumentException("operator word $operator")
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else -> throw IllegalArgumentException("operator word $operator")
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