fixed improved asm generation for conditions that compare signed word to zero

This commit is contained in:
Irmen de Jong 2021-10-31 02:39:45 +02:00
parent 33d17afc32
commit e3c00669c1
2 changed files with 36 additions and 69 deletions

View File

@ -93,15 +93,10 @@ internal class ExpressionsAsmGen(private val program: Program, private val asmge
else -> throw AssemblyError("invalid comparison operator $operator") else -> throw AssemblyError("invalid comparison operator $operator")
} }
} }
DataType.BYTE, DataType.WORD -> { DataType.BYTE -> {
if(dt==DataType.BYTE) { asmgen.assignExpressionToRegister(left, RegisterOrPair.A)
asmgen.assignExpressionToRegister(left, RegisterOrPair.A) if (left is FunctionCall && !left.isSimple)
if (left is FunctionCall && !left.isSimple) asmgen.out(" cmp #0")
asmgen.out(" cmp #0")
} else {
asmgen.assignExpressionToRegister(left, RegisterOrPair.AY)
asmgen.out(" sty P8ZP_SCRATCH_B1 | ora P8ZP_SCRATCH_B1") // TODO PROBABLY NOT OKAY FOR WORDS
}
when (operator) { when (operator) {
"==" -> asmgen.out(" bne $jumpIfFalseLabel") "==" -> asmgen.out(" bne $jumpIfFalseLabel")
"!=" -> asmgen.out(" beq $jumpIfFalseLabel") "!=" -> asmgen.out(" beq $jumpIfFalseLabel")
@ -115,6 +110,30 @@ internal class ExpressionsAsmGen(private val program: Program, private val asmge
else -> throw AssemblyError("invalid comparison operator $operator") else -> throw AssemblyError("invalid comparison operator $operator")
} }
} }
DataType.WORD -> {
asmgen.assignExpressionToRegister(left, RegisterOrPair.AY)
when (operator) {
"==" -> asmgen.out(" bne $jumpIfFalseLabel | cpy #0 | bne $jumpIfFalseLabel")
"!=" -> asmgen.out(" sty P8ZP_SCRATCH_B1 | ora P8ZP_SCRATCH_B1 | beq $jumpIfFalseLabel")
">" -> asmgen.out("""
cpy #0
bmi $jumpIfFalseLabel
bne +
cmp #0
beq $jumpIfFalseLabel
+ """)
"<" -> asmgen.out(" cpy #0 | bpl $jumpIfFalseLabel")
">=" -> asmgen.out(" cpy #0 | bmi $jumpIfFalseLabel")
"<=" -> asmgen.out("""
cpy #0
bmi +
bne $jumpIfFalseLabel
cmp #0
bne $jumpIfFalseLabel
+ """)
else -> throw AssemblyError("invalid comparison operator $operator")
}
}
DataType.FLOAT -> { DataType.FLOAT -> {
asmgen.assignExpressionToRegister(left, RegisterOrPair.FAC1) asmgen.assignExpressionToRegister(left, RegisterOrPair.FAC1)
asmgen.out(" jsr floats.SIGN") // SIGN(fac1) to A, $ff, $0, $1 for negative, zero, positive asmgen.out(" jsr floats.SIGN") // SIGN(fac1) to A, $ff, $0, $1 for negative, zero, positive

View File

@ -4,76 +4,24 @@
main { main {
sub start() { sub start() {
byte xx word xx
xx=0 xx=-$7f00
if xx>=0 { txt.print_w(xx)
txt.print("xx>=0\n")
} else {
txt.print("error1\n")
}
if xx<=0 {
txt.print("xx<=0\n")
} else {
txt.print("error1qq\n")
}
if xx>0 {
txt.print("xx>0 error\n")
} else {
txt.print("ok1\n")
}
if xx<0 {
txt.print("xx<0 error\n")
} else {
txt.print("ok1\n")
}
txt.nl() txt.nl()
xx=22
if xx>=0 { if xx>=0 {
txt.print("xx>=0\n") txt.print(">=0\n")
} else { } else {
txt.print("error2\n") txt.print("<0\n")
} }
if xx<=0 { if xx<=0 {
txt.print("xx<=0 error\n") txt.print("<=0\n")
} else { } else {
txt.print("ok2\n") txt.print(">0\n")
} }
if xx>0 {
txt.print("xx>0\n")
} else {
txt.print("error2\n")
}
if xx<0 {
txt.print("xx<0 error\n")
} else {
txt.print("ok2\n")
}
txt.nl()
xx=-11 return
if xx>=0 {
txt.print("xx>=0 error\n")
} else {
txt.print("ok3\n")
}
if xx<=0 {
txt.print("xx<=0\n")
} else {
txt.print("error3\n")
}
if xx>0 {
txt.print("xx>0 error\n")
} else {
txt.print("ok3\n")
}
if xx<0 {
txt.print("xx<0\n")
} else {
txt.print("error3\n")
}