mirror of
https://github.com/irmen/prog8.git
synced 2025-11-01 06:16:15 +00:00
added math.mul32(), verafx.muls now returns long
This commit is contained in:
Irmen de Jong
@@ -1122,7 +1122,7 @@ internal class AssignmentAsmGen(
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asmgen.out(" pla")
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asmgen.out(" sta cx16.r0 | sty cx16.r0+1")
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}
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asmgen.out(" jsr verafx.muls")
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asmgen.out(" jsr verafx.muls16")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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} else {
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@@ -1187,7 +1187,7 @@ internal class AssignmentAsmGen(
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asmgen.out("""
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sta cx16.r0
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sty cx16.r0+1
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jsr verafx.muls""")
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jsr verafx.muls16""")
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} else {
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asmgen.assignWordOperandsToAYAndVar(expr.right, expr.left, "prog8_math.multiply_words.multiplier")
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asmgen.out(" jsr prog8_math.multiply_words")
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@@ -2488,6 +2488,9 @@ $endLabel""")
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assignExpressionToRegister(value, RegisterOrPair.A, valueDt.isSigned)
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assignTypeCastedRegisters(target.asmVarname, targetDt.base, RegisterOrPair.A, valueDt.base)
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}
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valueDt.isLong -> {
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TODO("assign typecasted long to $targetDt ${value.position}")
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}
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valueDt.isWord || valueDt.isPointer -> {
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assignExpressionToRegister(value, RegisterOrPair.AY, valueDt.isSigned)
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assignTypeCastedRegisters(target.asmVarname, targetDt.base, RegisterOrPair.AY, valueDt.base)
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@@ -2983,7 +2986,15 @@ $endLabel""")
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else -> throw AssemblyError("non-word regs")
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}
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}
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BaseDataType.LONG -> TODO("assign typecasted to LONG")
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BaseDataType.LONG -> {
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when(regs) {
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RegisterOrPair.AX -> asmgen.out(" sta $targetAsmVarName | stx $targetAsmVarName+1")
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RegisterOrPair.AY -> asmgen.out(" sta $targetAsmVarName | sty $targetAsmVarName+1")
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RegisterOrPair.XY -> asmgen.out(" stx $targetAsmVarName | sty $targetAsmVarName+1")
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else -> throw AssemblyError("non-word regs")
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}
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asmgen.signExtendLongVariable(targetAsmVarName, BaseDataType.WORD)
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}
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BaseDataType.FLOAT -> {
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if(regs!=RegisterOrPair.AY)
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throw AssemblyError("only supports AY here")
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@@ -2323,7 +2323,7 @@ $shortcutLabel:""")
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if(value in asmgen.optimizedWordMultiplications) {
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asmgen.out(" lda $lsb | ldy $msb | jsr prog8_math.mul_word_$value | sta $lsb | sty $msb")
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} else {
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if(block?.options?.veraFxMuls==true)
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if(block?.options?.veraFxMuls==true) {
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// cx16 verafx hardware mul
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asmgen.out("""
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lda $lsb
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@@ -2334,9 +2334,10 @@ $shortcutLabel:""")
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ldy #>$value
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sta cx16.r1
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sty cx16.r1+1
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jsr verafx.muls
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jsr verafx.muls16
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sta $lsb
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sty $msb""")
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}
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else
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asmgen.out("""
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lda $lsb
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@@ -2821,9 +2822,10 @@ $shortcutLabel:""")
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ldy $name+1
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sta cx16.r0
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sty cx16.r0+1
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jsr verafx.muls
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jsr verafx.muls16
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sta $name
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sty $name+1""")
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} else {
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if(valueDt.isUnsignedByte) {
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asmgen.out(" lda $otherName | sta prog8_math.multiply_words.multiplier")
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@@ -2966,7 +2968,7 @@ $shortcutLabel:""")
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"+" -> asmgen.out(" lda $name | clc | adc $otherName | sta $name | lda $name+1 | adc $otherName+1 | sta $name+1")
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"-" -> asmgen.out(" lda $name | sec | sbc $otherName | sta $name | lda $name+1 | sbc $otherName+1 | sta $name+1")
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"*" -> {
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if(block?.options?.veraFxMuls==true)
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if(block?.options?.veraFxMuls==true) {
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// cx16 verafx hardware muls
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asmgen.out("""
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lda $name
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@@ -2977,9 +2979,10 @@ $shortcutLabel:""")
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ldy $otherName+1
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sta cx16.r1
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sty cx16.r1+1
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jsr verafx.muls
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jsr verafx.muls16
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sta $name
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sty $name+1""")
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}
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else
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asmgen.out("""
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lda $otherName
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@@ -3170,7 +3173,7 @@ $shortcutLabel:""")
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private fun inplacemodificationWordWithValue(name: String, dt: DataType, operator: String, value: PtExpression, block: PtBlock?) {
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require(dt.isWord)
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fun multiplyVarByWordInAX() {
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if(block?.options?.veraFxMuls==true)
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if(block?.options?.veraFxMuls==true) {
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// cx16 verafx hardware muls
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asmgen.out("""
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sta cx16.r1
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@@ -3179,9 +3182,10 @@ $shortcutLabel:""")
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ldx $name+1
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sta cx16.r0
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stx cx16.r0+1
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jsr verafx.muls
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jsr verafx.muls16
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sta $name
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sty $name+1""")
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}
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else
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asmgen.out("""
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sta prog8_math.multiply_words.multiplier
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@@ -686,6 +686,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, IRInstruction(Opcode.CMPI, IRDataType.WORD, reg1=tr.resultReg, immediate = 0), null)
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actualResultReg2 = loadStatusAsBooleanResult(Opcode.BSTNE, result)
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}
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valueDt.isLong -> TODO("typecast long ${cast.position}")
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valueDt.isFloat -> {
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actualResultReg2 = codeGen.registers.next(IRDataType.BYTE)
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result += IRCodeChunk(null, null).also {
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@@ -116,26 +116,29 @@ verafx {
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asmsub mult16(uword value1 @R0, uword value2 @R1) clobbers(X) -> uword @AY {
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; Returns the 16 bits unsigned result of R0*R1 in AY.
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; Returns the lower 16 bits unsigned result of R0*R1 in AY
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; Note: only the lower 16 bits! (the upper 16 bits are not valid for unsigned word multiplications, only for signed)
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; Verafx doesn't support unsigned values like this for full 32 bit result.
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; Note: clobbers VRAM $1f9bc - $1f9bf (inclusive)
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%asm {{
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lda cx16.r0
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sta P8ZP_SCRATCH_W1
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lda cx16.r0+1
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sta P8ZP_SCRATCH_W1+1
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jsr verafx.muls
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ldx P8ZP_SCRATCH_W1
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stx cx16.r0
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ldx P8ZP_SCRATCH_W1+1
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stx cx16.r0+1
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jmp muls16
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}}
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}
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asmsub muls16(word value1 @R0, word value2 @R1) clobbers(X) -> word @AY {
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; Returns just the lower 16 bits signed result of the multiplication in cx16.AY.
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; Note: clobbers R0, R1, and VRAM $1f9bc - $1f9bf (inclusive)
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%asm {{
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jsr muls
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lda cx16.r0L
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ldy cx16.r0H
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rts
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}}
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}
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asmsub muls(word value1 @R0, word value2 @R1) clobbers(X) -> word @AY, word @R0 {
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; Returns the 32 bits signed result in AY and R0 (lower word, upper word).
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asmsub muls(word value1 @R0, word value2 @R1) clobbers(X) -> long @R0R1_32 {
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; Returns the 32 bits signed result in R0:R1 (lower word, upper word).
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; Vera Fx multiplication support only works on signed values!
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; Note: clobbers VRAM $1f9bc - $1f9bf (inclusive)
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%asm {{
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@@ -171,12 +174,14 @@ verafx {
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stz cx16.VERA_DATA0 ; multiply and write out result
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lda #%00010001 ; $01 with Increment 1
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sta cx16.VERA_ADDR_H ; so we can read out the result
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lda cx16.VERA_DATA0 ; store the lower 16 bits of the result in AY
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lda cx16.VERA_DATA0 ; store the lower 16 bits of the result in R0
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ldy cx16.VERA_DATA0
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ldx cx16.VERA_DATA0 ; store the upper 16 bits of the result in R0
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stx cx16.r0s
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ldx cx16.VERA_DATA0
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stx cx16.r0s+1
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sta cx16.r0L
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sty cx16.r0H
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lda cx16.VERA_DATA0 ; store the upper 16 bits of the result in R1
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ldy cx16.VERA_DATA0 ; store the upper 16 bits of the result in R1
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sta cx16.r1L
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sty cx16.r1H
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stz cx16.VERA_FX_CTRL ; Cache write disable
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stz cx16.VERA_FX_MULT ; $9F2C reset multiply bit
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stz cx16.VERA_CTRL ; reset DCSEL
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@@ -220,6 +220,12 @@ _sinecosR8 .char trunc(127.0 * sin(range(180+45) * rad(360.0/180.0)))
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}}
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}
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sub mul32(uword a, uword b) -> long {
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; return 32 bits result of a*b
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cx16.r2 = a*b
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return mklong2(mul16_last_upper(), cx16.r2)
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}
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sub direction_sc(byte x1, byte y1, byte x2, byte y2) -> ubyte {
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; From a pair of signed coordinates around the origin, calculate discrete direction between 0 and 23 into A.
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cx16.r0L = 3 ; quadrant
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@@ -304,6 +304,12 @@ math {
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}}
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}
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sub mul32(uword a, uword b) -> long {
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; return 32 bits result of a*b
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cx16.r2 = a*b
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return mklong2(mul16_last_upper(), cx16.r2)
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}
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sub diff(ubyte b1, ubyte b2) -> ubyte {
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if b1>b2
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return b1-b2
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@@ -1239,7 +1239,10 @@ Available for the Cx16 target. Routines that use the Vera FX logic to accelerate
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But it depends on some Vera manipulation and 4 bytes in vram just below the PSG registers for storage.
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Note: there is a block level %option "verafxmuls" that automatically replaces all word multiplications in that block
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by calls to verafx, but be careful with it because it may interfere with other Vera operations or IRQs.
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The full 32 bits result value is returned in two result values: lower word, upper word.
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The full 32 bits result value is returned as a long.
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``muls16``
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Like ``muls`` but only returns the lower word of the result, which is sometimes useful if you're just interested in word values.
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``mult16``
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VeraFX hardware multiplication of two unsigned words.
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@@ -3,9 +3,7 @@ TODO
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LONG TYPE
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---------
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- scan through more library routines if there are opportunities to use a long param or returnvalue?
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- document the new long type! and mklong(a,b,c,d) and mklong2(w1,w2) , print_l , print_ulhex (& conv.str_l) and pokel, peekl, cbm.SETTIML/RDTIML, and the use of R0:R1 when doing LONG calculations
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- asmsub call convention: @R0R1_32 to specify a 32 bits long combined register R0:R1
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- document the new long type! and mklong(a,b,c,d) and mklong2(w1,w2) , print_l , print_ulhex (& conv.str_l) and pokel, peekl, cbm.SETTIML/RDTIML, math.mul32, verafx.muls/muls16, and the use of R0:R1 when doing LONG calculations, asmsub call convention: @R0R1_32 to specify a 32 bits long combined register R0:R1
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- how hard is it to also implement the other comparison operators (<,>,<=,>=) on longs?
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- implement LONG testcases in testmemory
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101
examples/test.p8
101
examples/test.p8
@@ -1,95 +1,32 @@
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%import textio
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%import math
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%import verafx
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%zeropage basicsafe
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main {
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%option verafxmuls
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sub start() {
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long @shared lv1 = 12345678
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long @shared lv2same = 12345678
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long @shared lv2different = 999999
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if lv1==0
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txt.print("wrong1\n")
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cx16.r5s = 22
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cx16.r6s = -999
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if lv1==0
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txt.print("wrong2\n")
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else
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txt.print("ok2\n")
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cx16.r0s = cx16.r5s * cx16.r6s
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txt.print_w(cx16.r0s)
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txt.nl()
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if lv1!=0
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txt.print("ok3\n")
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if lv1!=0
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txt.print("ok4\n")
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else
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txt.print("wrong4\n")
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long lv = cx16.r5s * cx16.r6s
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txt.print_l(lv)
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txt.nl()
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if lv1==999999
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txt.print("wrong5\n")
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if lv1==999999
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txt.print("wrong6\n")
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else
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txt.print("ok6\n")
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if lv1!=999999
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txt.print("ok7\n")
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if lv1!=999999
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txt.print("ok8\n")
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else
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txt.print("wrong8\n")
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if lv1==12345678
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txt.print("ok9\n")
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if lv1==12345678
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txt.print("ok10\n")
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else
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txt.print("wrong10\n")
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if lv1!=12345678
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txt.print("wrong11\n")
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if lv1!=12345678
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txt.print("wrong12\n")
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else
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txt.print("ok12\n")
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if lv1==lv2same
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txt.print("ok13\n")
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if lv1==lv2same
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txt.print("ok14\n")
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else
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txt.print("wrong14\n")
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if lv1!=lv2same
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txt.print("wrong15\n")
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if lv1!=lv2same
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txt.print("wrong16\n")
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else
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txt.print("ok16\n")
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if lv1==lv2different
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txt.print("wrong17\n")
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if lv1==lv2different
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txt.print("wrong18\n")
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else
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txt.print("ok18\n")
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if lv1!=lv2different
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txt.print("ok19\n")
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if lv1!=lv2different
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txt.print("ok20\n")
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else
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txt.print("wrong20\n")
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cx16.r5s = 5555
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cx16.r6s = -9999
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lv = cx16.r5s * cx16.r6s
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txt.print_l(lv)
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txt.nl()
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lv = verafx.muls(cx16.r5s, cx16.r6s)
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txt.print_l(lv)
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txt.nl()
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}
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}
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