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ir: count register uses
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@ -3,8 +3,6 @@ TODO
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For next release
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For next release
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^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^
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- ir: RegistersUsed should actually count the number of times a register is used too?
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...
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...
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@ -33,28 +33,21 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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out.write("</PROGRAM>\n")
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out.write("</PROGRAM>\n")
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out.close()
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out.close()
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val usedRegisters = mutableSetOf<Int>()
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var usedRegisters = 0
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val usedFpRegisters = mutableSetOf<Int>()
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irProgram.blocks.forEach {
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fun addUsed(used: RegistersUsed) {
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it.inlineAssembly.forEach { chunk ->
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used.inputRegs.forEach{ (reg, count) -> usedRegisters+=count }
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val used = chunk.usedRegisters()
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used.outputRegs.forEach{ (reg, count) -> usedRegisters+=count }
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usedRegisters += used.inputRegs + used.outputRegs
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used.inputFpRegs.forEach{ (reg, count) -> usedRegisters+=count }
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usedFpRegisters += used.inputFpRegs + used.outputFpRegs
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used.outputFpRegs.forEach{ (reg, count) -> usedRegisters+=count }
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}
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it.subroutines.forEach { sub ->
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sub.chunks.forEach { chunk ->
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val used = chunk.usedRegisters()
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usedRegisters += used.inputRegs + used.outputRegs
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usedFpRegisters += used.inputFpRegs + used.outputFpRegs
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}
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}
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it.asmSubroutines.forEach { asmsub ->
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val used = asmsub.usedRegisters()
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usedRegisters += used.inputRegs + used.outputRegs
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usedFpRegisters += used.inputFpRegs + used.outputFpRegs
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}
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}
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}
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println("($numLines lines in $numChunks code chunks, ${usedRegisters.size + usedFpRegisters.size} registers)")
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irProgram.blocks.forEach {
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it.inlineAssembly.forEach { chunk -> addUsed(chunk.usedRegisters()) }
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it.subroutines.flatMap { sub->sub.chunks }.forEach { chunk -> addUsed(chunk.usedRegisters()) }
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it.asmSubroutines.forEach { asmsub -> addUsed(asmsub.usedRegisters()) }
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}
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println("($numLines lines in $numChunks code chunks, $usedRegisters registers)")
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return outfile
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return outfile
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}
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}
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@ -676,7 +676,6 @@ data class IRInstruction(
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val reg2direction: OperandDirection
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val reg2direction: OperandDirection
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val fpReg1direction: OperandDirection
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val fpReg1direction: OperandDirection
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val fpReg2direction: OperandDirection
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val fpReg2direction: OperandDirection
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private val registersUsed: RegistersUsed
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init {
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init {
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require(labelSymbol?.first()!='_') {"label/symbol should not start with underscore $labelSymbol"}
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require(labelSymbol?.first()!='_') {"label/symbol should not start with underscore $labelSymbol"}
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@ -733,45 +732,43 @@ data class IRInstruction(
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else
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else
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require(reg1!=reg2) {"$opcode: reg1 and reg2 should be different"}
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require(reg1!=reg2) {"$opcode: reg1 and reg2 should be different"}
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}
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}
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val inputRegs = mutableSetOf<Int>()
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val outputRegs = mutableSetOf<Int>()
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val inputFpRegs = mutableSetOf<Int>()
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val outputFpRegs = mutableSetOf<Int>()
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when (reg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputRegs += reg1!!
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OperandDirection.OUTPUT -> outputRegs += reg1!!
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OperandDirection.INOUT -> {
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inputRegs += reg1!!
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outputRegs += reg1!!
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}
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}
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when (reg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputRegs += reg2!!
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else -> throw IllegalArgumentException("reg2 can only be input")
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}
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when (fpReg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs += fpReg1!!
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OperandDirection.OUTPUT -> outputFpRegs += fpReg1!!
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OperandDirection.INOUT -> {
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inputFpRegs += fpReg1!!
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outputFpRegs += fpReg1!!
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}
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}
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when (fpReg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs += fpReg2!!
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else -> throw IllegalArgumentException("fpReg2 can only be input")
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}
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registersUsed = RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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}
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}
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override fun usedRegisters() = registersUsed
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fun addUsedRegistersCounts(
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inputRegs: MutableMap<Int, Int>,
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outputRegs: MutableMap<Int, Int>,
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inputFpRegs: MutableMap<Int, Int>,
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outputFpRegs: MutableMap<Int, Int>
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) {
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when (this.reg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputRegs[this.reg1!!] = inputRegs.getValue(this.reg1)+1
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OperandDirection.OUTPUT -> outputRegs[this.reg1!!] = outputRegs.getValue(this.reg1)+1
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OperandDirection.INOUT -> {
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inputRegs[this.reg1!!] = inputRegs.getValue(this.reg1)+1
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outputRegs[this.reg1] = outputRegs.getValue(this.reg1)+1
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}
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}
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when (this.reg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> outputRegs[this.reg2!!] = outputRegs.getValue(this.reg2)+1
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else -> throw IllegalArgumentException("reg2 can only be input")
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}
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when (this.fpReg1direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs[this.fpReg1!!] = inputFpRegs.getValue(this.fpReg1)+1
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OperandDirection.OUTPUT -> outputFpRegs[this.fpReg1!!] = outputFpRegs.getValue(this.fpReg1)+1
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OperandDirection.INOUT -> {
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inputFpRegs[this.fpReg1!!] = inputFpRegs.getValue(this.fpReg1)+1
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outputFpRegs[this.fpReg1] = outputFpRegs.getValue(this.fpReg1)+1
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}
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}
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when (this.fpReg2direction) {
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OperandDirection.UNUSED -> {}
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OperandDirection.INPUT -> inputFpRegs[this.fpReg2!!] = inputFpRegs.getValue(this.fpReg2)+1
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else -> throw IllegalArgumentException("fpReg2 can only be input")
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}
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}
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override fun toString(): String {
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override fun toString(): String {
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val result = mutableListOf(opcode.name.lowercase())
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val result = mutableListOf(opcode.name.lowercase())
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@ -144,21 +144,13 @@ class IRAsmSubroutine(
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fun usedRegisters() = registersUsed
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fun usedRegisters() = registersUsed
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}
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}
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sealed class IRCodeLine {
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sealed class IRCodeLine
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abstract fun usedRegisters(): RegistersUsed
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}
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class IRCodeLabel(val name: String): IRCodeLine() {
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class IRCodeLabel(val name: String): IRCodeLine()
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override fun usedRegisters() = RegistersUsed.EMPTY
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}
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class IRCodeComment(val comment: String): IRCodeLine() {
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class IRCodeComment(val comment: String): IRCodeLine()
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override fun usedRegisters() = RegistersUsed.EMPTY
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}
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class IRCodeInlineBinary(val data: Collection<UByte>): IRCodeLine() {
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class IRCodeInlineBinary(val data: Collection<UByte>): IRCodeLine()
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override fun usedRegisters() = RegistersUsed.EMPTY
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}
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abstract class IRCodeChunkBase(val position: Position) {
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abstract class IRCodeChunkBase(val position: Position) {
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val lines = mutableListOf<IRCodeLine>()
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val lines = mutableListOf<IRCodeLine>()
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@ -173,16 +165,13 @@ class IRCodeChunk(position: Position): IRCodeChunkBase(position) {
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override fun isEmpty() = lines.isEmpty()
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override fun isEmpty() = lines.isEmpty()
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override fun isNotEmpty() = lines.isNotEmpty()
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override fun isNotEmpty() = lines.isNotEmpty()
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override fun usedRegisters(): RegistersUsed {
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override fun usedRegisters(): RegistersUsed {
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val inputRegs = mutableSetOf<Int>()
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val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputRegs = mutableSetOf<Int>()
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val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val inputFpRegs = mutableSetOf<Int>()
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val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputFpRegs = mutableSetOf<Int>()
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val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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lines.forEach {
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lines.forEach {
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val used = it.usedRegisters()
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if(it is IRInstruction)
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inputRegs += used.inputRegs
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it.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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outputRegs += used.outputRegs
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inputFpRegs += used.inputFpRegs
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outputFpRegs += used.outputFpRegs
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}
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}
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return RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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return RegistersUsed(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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}
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}
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@ -197,10 +186,11 @@ class IRCodeChunk(position: Position): IRCodeChunkBase(position) {
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}
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}
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class RegistersUsed(
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class RegistersUsed(
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val inputRegs: Set<Int>,
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// register num -> number of uses
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val outputRegs: Set<Int>,
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val inputRegs: Map<Int, Int>,
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val inputFpRegs: Set<Int>,
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val outputRegs: Map<Int, Int>,
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val outputFpRegs: Set<Int>
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val inputFpRegs: Map<Int, Int>,
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val outputFpRegs: Map<Int, Int>,
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) {
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) {
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override fun toString(): String {
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override fun toString(): String {
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return "input=$inputRegs, output=$outputRegs, inputFp=$inputFpRegs, outputFp=$outputFpRegs"
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return "input=$inputRegs, output=$outputRegs, inputFp=$inputFpRegs, outputFp=$outputFpRegs"
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@ -208,10 +198,6 @@ class RegistersUsed(
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fun isEmpty() = inputRegs.isEmpty() && outputRegs.isEmpty() && inputFpRegs.isEmpty() && outputFpRegs.isEmpty()
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fun isEmpty() = inputRegs.isEmpty() && outputRegs.isEmpty() && inputFpRegs.isEmpty() && outputFpRegs.isEmpty()
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fun isNotEmpty() = !isEmpty()
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fun isNotEmpty() = !isEmpty()
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companion object {
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val EMPTY = RegistersUsed(emptySet(), emptySet(), emptySet(), emptySet())
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}
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}
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}
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class IRInlineAsmChunk(val assembly: String, val isIR: Boolean, position: Position): IRCodeChunkBase(position) {
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class IRInlineAsmChunk(val assembly: String, val isIR: Boolean, position: Position): IRCodeChunkBase(position) {
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@ -229,19 +215,16 @@ class IRInlineAsmChunk(val assembly: String, val isIR: Boolean, position: Positi
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}
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}
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private fun registersUsedInAssembly(isIR: Boolean, assembly: String): RegistersUsed {
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private fun registersUsedInAssembly(isIR: Boolean, assembly: String): RegistersUsed {
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val inputRegs = mutableSetOf<Int>()
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val inputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val inputFpRegs = mutableSetOf<Int>()
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val inputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputRegs = mutableSetOf<Int>()
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val outputRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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val outputFpRegs = mutableSetOf<Int>()
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val outputFpRegs = mutableMapOf<Int, Int>().withDefault { 0 }
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if(isIR) {
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if(isIR) {
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assembly.lineSequence().forEach { line ->
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assembly.lineSequence().forEach { line ->
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val code = parseIRCodeLine(line.trim(), 0, mutableMapOf())
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val code = parseIRCodeLine(line.trim(), 0, mutableMapOf())
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val used = code.usedRegisters()
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if(code is IRInstruction)
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inputRegs += used.inputRegs
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code.addUsedRegistersCounts(inputRegs, outputRegs, inputFpRegs, outputFpRegs)
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outputRegs += used.outputRegs
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inputFpRegs += used.inputFpRegs
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outputFpRegs += used.outputFpRegs
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}
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}
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}
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}
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