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* restrict access to Program.modules, add tests

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This commit is contained in:
meisl
2021-08-01 22:47:11 +02:00
parent 007d8d2811
commit eb46852bb9
9 changed files with 218 additions and 74 deletions
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38
compiler/test/TestMemory.kt
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@@ -24,7 +24,7 @@ class TestMemory {
var memexpr = NumericLiteralValue.optimalInteger(0x0000, Position.DUMMY)
var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
val program = Program("test", mutableListOf(), DummyFunctions, DummyMemsizer)
val program = Program("test", DummyFunctions, DummyMemsizer)
assertTrue(C64Target.isInRegularRAM(target, program))
memexpr = NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY)
@@ -49,7 +49,7 @@ class TestMemory {
var memexpr = NumericLiteralValue.optimalInteger(0xa000, Position.DUMMY)
var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
val program = Program("test", mutableListOf(), DummyFunctions, DummyMemsizer)
val program = Program("test", DummyFunctions, DummyMemsizer)
assertFalse(C64Target.isInRegularRAM(target, program))
memexpr = NumericLiteralValue.optimalInteger(0xafff, Position.DUMMY)
@@ -68,7 +68,7 @@ class TestMemory {
@Test
fun testInValidRamC64_memory_identifiers() {
var target = createTestProgramForMemoryRefViaVar(0x1000, VarDeclType.VAR)
val program = Program("test", mutableListOf(), DummyFunctions, DummyMemsizer)
val program = Program("test", DummyFunctions, DummyMemsizer)
assertTrue(C64Target.isInRegularRAM(target, program))
target = createTestProgramForMemoryRefViaVar(0xd020, VarDeclType.VAR)
@@ -97,7 +97,7 @@ class TestMemory {
fun testInValidRamC64_memory_expression() {
val memexpr = PrefixExpression("+", NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY), Position.DUMMY)
val target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
val program = Program("test", mutableListOf(), DummyFunctions, DummyMemsizer)
val program = Program("test", DummyFunctions, DummyMemsizer)
assertFalse(C64Target.isInRegularRAM(target, program))
}
@@ -108,8 +108,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertTrue(C64Target.isInRegularRAM(target, program))
}
@@ -121,8 +122,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertTrue(C64Target.isInRegularRAM(target, program))
}
@@ -134,8 +136,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertFalse(C64Target.isInRegularRAM(target, program))
}
@@ -147,8 +150,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertTrue(C64Target.isInRegularRAM(target, program))
}
@@ -161,8 +165,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertTrue(C64Target.isInRegularRAM(target, program))
}
@@ -175,8 +180,9 @@ class TestMemory {
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
val program = Program("test", mutableListOf(module), DummyFunctions, DummyMemsizer)
module.linkParents(ParentSentinel)
val program = Program("test", DummyFunctions, DummyMemsizer)
.addModule(module)
module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
assertFalse(C64Target.isInRegularRAM(target, program))
}
}