mirror of
https://github.com/irmen/prog8.git
synced 2025-01-10 20:30:23 +00:00
vm: remove BEQ opcode -> CMPI + BSTEQ
This commit is contained in:
Irmen de Jong
parent
eb55da63ef
commit
eb64d92333
@ -562,14 +562,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val resultRegister = codeGen.registers.nextFree()
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val valueReg = codeGen.registers.nextFree()
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val label = codeGen.createLabelName()
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1), null)
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addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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if (notEquals) {
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addInstr(result, IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=valueReg, immediate = 0, labelSymbol = label), null)
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} else {
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addInstr(result, IRInstruction(Opcode.BEQ, IRDataType.BYTE, reg1=valueReg, immediate = 0, labelSymbol = label), null)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 1)
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg)
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if (notEquals) {
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it += IRInstruction(Opcode.BNE, IRDataType.BYTE, reg1=valueReg, immediate = 0, labelSymbol = label)
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} else {
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1=valueReg, immediate = 0)
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = label)
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}
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0)
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}
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, immediate = 0), null)
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result += IRCodeChunk(label, null)
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return ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1)
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} else {
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@ -415,13 +415,19 @@ class IRCodeGen(
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if(choice.statements.children.isEmpty()) {
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// no statements for this choice value, jump to the end immediately
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choice.values.children.map { it as PtNumber }.sortedBy { it.number }.forEach { value ->
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addInstr(result, IRInstruction(Opcode.BEQ, valueDt, reg1=valueTr.resultReg, immediate = value.number.toInt(), labelSymbol = endLabel), null)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, valueDt, reg1=valueTr.resultReg, immediate = value.number.toInt())
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = endLabel)
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}
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}
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} else {
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val choiceLabel = createLabelName()
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choices.add(choiceLabel to choice)
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choice.values.children.map { it as PtNumber }.sortedBy { it.number }.forEach { value ->
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addInstr(result, IRInstruction(Opcode.BEQ, valueDt, reg1=valueTr.resultReg, immediate = value.number.toInt(), labelSymbol = choiceLabel), null)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, valueDt, reg1=valueTr.resultReg, immediate = value.number.toInt())
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = choiceLabel)
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}
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}
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}
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}
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@ -464,7 +470,8 @@ class IRCodeGen(
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = indexReg, immediate = 0), null)
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result += IRCodeChunk(loopLabel, null).also {
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = tmpReg, reg2 = indexReg, labelSymbol = iterable.name)
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it += IRInstruction(Opcode.BEQ, IRDataType.BYTE, reg1 = tmpReg, immediate = 0, labelSymbol = endLabel)
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = tmpReg, immediate = 0)
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = endLabel)
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = tmpReg, labelSymbol = loopvarSymbol)
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}
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result += translateNode(forLoop.statements)
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@ -960,21 +967,30 @@ class IRCodeGen(
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fpReg1 = leftTr.resultFpReg,
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fpReg2 = rightTr.resultFpReg
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)
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val gotoOpcode = when (condition.operator) {
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"==" -> Opcode.BEQ
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"!=" -> Opcode.BNE
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"<" -> Opcode.BLTS
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">" -> Opcode.BGTS
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"<=" -> Opcode.BLES
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">=" -> Opcode.BGES
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else -> throw AssemblyError("weird operator")
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when(condition.operator) {
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// TODO: the converted list of operators
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"==" -> {
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0)
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it += branchInstr(goto, Opcode.BSTEQ)
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}
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else -> {
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// TODO: the old list of operators, still to be converted
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val gotoOpcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> Opcode.BLTS
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">" -> Opcode.BGTS
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"<=" -> Opcode.BLES
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">=" -> Opcode.BGES
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else -> throw AssemblyError("weird operator")
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}
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it += if (goto.address != null)
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, address = goto.address?.toInt())
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else if (goto.generatedLabel != null)
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = goto.generatedLabel)
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else
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = goto.identifier!!.name)
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}
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}
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it += if (goto.address != null)
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, address = goto.address?.toInt())
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else if (goto.generatedLabel != null)
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = goto.generatedLabel)
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else
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = goto.identifier!!.name)
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}
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return result
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} else {
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@ -989,6 +1005,14 @@ class IRCodeGen(
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}
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}
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// TODO use this everywhere
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private fun branchInstr(goto: PtJump, branchOpcode: Opcode) = if (goto.address != null)
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IRInstruction(branchOpcode, address = goto.address?.toInt())
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else if (goto.generatedLabel != null)
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IRInstruction(branchOpcode, labelSymbol = goto.generatedLabel)
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else
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IRInstruction(branchOpcode, labelSymbol = goto.identifier!!.name)
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private fun ifZeroIntThenJump(
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result: MutableList<IRCodeChunkBase>,
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ifElse: PtIfElse,
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@ -999,21 +1023,30 @@ class IRCodeGen(
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val condition = ifElse.condition as PtBinaryExpression
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val leftTr = expressionEval.translateExpression(condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val opcode = when (condition.operator) {
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"==" -> Opcode.BEQ
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"!=" -> Opcode.BNE
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"<" -> if (signed) Opcode.BLTS else Opcode.BLT
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">" -> if (signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if (signed) Opcode.BLES else Opcode.BLE
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">=" -> if (signed) Opcode.BGES else Opcode.BGE
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else -> throw AssemblyError("invalid comparison operator")
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when(condition.operator) {
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// TODO: converted list of operators
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"==" -> {
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = leftTr.resultReg, immediate = 0), null)
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addInstr(result, branchInstr(goto, Opcode.BSTEQ), null)
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}
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else -> {
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// TODO: to-be converted operators
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val opcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> if (signed) Opcode.BLTS else Opcode.BLT
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">" -> if (signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if (signed) Opcode.BLES else Opcode.BLE
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">=" -> if (signed) Opcode.BGES else Opcode.BGE
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else -> throw AssemblyError("invalid comparison operator")
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, address = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, labelSymbol = goto.identifier!!.name), null)
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}
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, address = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = leftTr.resultReg, immediate = 0, labelSymbol = goto.identifier!!.name), null)
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}
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private fun ifNonZeroIntThenJump(
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@ -1036,30 +1069,39 @@ class IRCodeGen(
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} else {
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val leftTr = expressionEval.translateExpression(condition.left)
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addToResult(result, leftTr, leftTr.resultReg, -1)
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val opcode: Opcode
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val number = (condition.right as? PtNumber)?.number?.toInt()
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if(number!=null) {
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val firstReg = leftTr.resultReg
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opcode = when (condition.operator) {
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"==" -> Opcode.BEQ
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"!=" -> Opcode.BNE
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"<" -> if(signed) Opcode.BLTS else Opcode.BLT
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">" -> if(signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if(signed) Opcode.BLES else Opcode.BLE
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">=" -> if(signed) Opcode.BGES else Opcode.BGE
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else -> throw AssemblyError("invalid comparison operator")
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when(condition.operator) {
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// TODO: the converted operators
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"==" -> {
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addInstr(result, IRInstruction(Opcode.CMPI, irDtLeft, reg1 = firstReg, immediate = number), null)
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addInstr(result, branchInstr(goto, Opcode.BSTEQ), null)
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}
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else -> {
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// TODO: to-be converted operators
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val opcode = when (condition.operator) {
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"!=" -> Opcode.BNE
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"<" -> if(signed) Opcode.BLTS else Opcode.BLT
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">" -> if(signed) Opcode.BGTS else Opcode.BGT
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"<=" -> if(signed) Opcode.BLES else Opcode.BLE
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">=" -> if(signed) Opcode.BGES else Opcode.BGE
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else -> throw AssemblyError("invalid comparison operator")
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, address = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, labelSymbol = goto.identifier!!.name), null)
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}
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}
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if (goto.address != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, address = goto.address?.toInt()), null)
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else if (goto.generatedLabel != null)
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDtLeft, reg1 = firstReg, immediate = number, labelSymbol = goto.identifier!!.name), null)
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} else {
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val rightTr = expressionEval.translateExpression(condition.right)
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addToResult(result, rightTr, rightTr.resultReg, -1)
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val firstReg: Int
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val secondReg: Int
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val opcode: Opcode
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when (condition.operator) {
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"==" -> {
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opcode = Opcode.BEQR
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@ -1108,6 +1150,7 @@ class IRCodeGen(
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private fun translateIfElseZeroComparison(ifElse: PtIfElse, irDtLeft: IRDataType, signed: Boolean): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val elseBranch: Opcode
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var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already
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val compResultReg: Int
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val branchDt: IRDataType
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val condition = ifElse.condition as PtBinaryExpression
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@ -1121,13 +1164,16 @@ class IRCodeGen(
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it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = rightFpReg, immediateFp = 0f)
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightFpReg)
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}
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elseBranch = when (condition.operator) {
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"==" -> Opcode.BNE
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"!=" -> Opcode.BEQ
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"<" -> Opcode.BGES
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">" -> Opcode.BLES
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"<=" -> Opcode.BGTS
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">=" -> Opcode.BLTS
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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}
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"<" -> elseBranch = Opcode.BGES
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">" -> elseBranch = Opcode.BLES
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"<=" -> elseBranch = Opcode.BGTS
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">=" -> elseBranch = Opcode.BLTS
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else -> throw AssemblyError("weird operator")
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}
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} else {
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@ -1136,13 +1182,16 @@ class IRCodeGen(
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val tr = expressionEval.translateExpression(condition.left)
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compResultReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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elseBranch = when (condition.operator) {
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"==" -> Opcode.BNE
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"!=" -> Opcode.BEQ
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"<" -> if (signed) Opcode.BGES else Opcode.BGE
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">" -> if (signed) Opcode.BLES else Opcode.BLE
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"<=" -> if (signed) Opcode.BGTS else Opcode.BGT
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">=" -> if (signed) Opcode.BLTS else Opcode.BLT
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when (condition.operator) {
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"==" -> elseBranch = Opcode.BNE
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"!=" -> {
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elseBranch = Opcode.BSTEQ
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useCmpi = true
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}
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"<" -> elseBranch = if (signed) Opcode.BGES else Opcode.BGE
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">" -> elseBranch = if (signed) Opcode.BLES else Opcode.BLE
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"<=" -> elseBranch = if (signed) Opcode.BGTS else Opcode.BGT
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">=" -> elseBranch = if (signed) Opcode.BLTS else Opcode.BLT
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else -> throw AssemblyError("weird operator")
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}
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}
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@ -1150,14 +1199,26 @@ class IRCodeGen(
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if(ifElse.elseScope.children.isEmpty()) {
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// just if
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(elseBranch, branchDt, reg1=compResultReg, immediate = 0, labelSymbol = afterIfLabel), null)
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if(useCmpi) {
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, branchDt, reg1=compResultReg, immediate = 0)
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it += IRInstruction(elseBranch, labelSymbol = afterIfLabel)
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}
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} else
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addInstr(result, IRInstruction(elseBranch, branchDt, reg1=compResultReg, immediate = 0, labelSymbol = afterIfLabel), null)
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result += translateNode(ifElse.ifScope)
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result += IRCodeChunk(afterIfLabel, null)
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} else {
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// if and else
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(elseBranch, branchDt, reg1=compResultReg, immediate = 0, labelSymbol = elseLabel), null)
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if(useCmpi) {
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMPI, branchDt, reg1=compResultReg, immediate = 0)
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it += IRInstruction(elseBranch, labelSymbol = elseLabel)
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}
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} else
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addInstr(result, IRInstruction(elseBranch, branchDt, reg1=compResultReg, immediate = 0, labelSymbol = elseLabel), null)
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result += translateNode(ifElse.ifScope)
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addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
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result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
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@ -1168,31 +1229,39 @@ class IRCodeGen(
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private fun translateIfElseNonZeroComparison(ifElse: PtIfElse, irDtLeft: IRDataType, signed: Boolean): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val elseBranchOpcode: Opcode
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val elseBranchFirstReg: Int
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val elseBranchSecondReg: Int
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val branchDt: IRDataType
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val condition = ifElse.condition as? PtBinaryExpression
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if(condition==null) {
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if(irDtLeft==IRDataType.FLOAT)
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throw AssemblyError("condition value should not be float")
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val tr = expressionEval.translateExpression(ifElse.condition)
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result += tr.chunks
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if(ifElse.elseScope.children.isNotEmpty()) {
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(Opcode.BEQ, irDtLeft, reg1=tr.resultReg, immediate = 0, labelSymbol = elseLabel), null)
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result += translateNode(ifElse.ifScope)
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addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
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result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
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result += IRCodeChunk(afterIfLabel, null)
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} else {
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(Opcode.BEQ, irDtLeft, reg1=tr.resultReg, immediate = 0, labelSymbol = afterIfLabel), null)
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result += translateNode(ifElse.ifScope)
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result += IRCodeChunk(afterIfLabel, null)
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}
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return result
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throw AssemblyError("if-else condition is not a binaryexpression, should have been converted?")
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// if(irDtLeft==IRDataType.FLOAT)
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// throw AssemblyError("condition value should not be float")
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// val tr = expressionEval.translateExpression(ifElse.condition)
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// result += tr.chunks
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// if(ifElse.elseScope.children.isNotEmpty()) {
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// val elseLabel = createLabelName()
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// result += IRCodeChunk(null, null).also {
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// it += IRInstruction(Opcode.CMPI, irDtLeft, reg1=tr.resultReg, immediate = 0)
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// it += IRInstruction(Opcode.BSTEQ, labelSymbol = elseLabel)
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// TODO("test this")
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// }
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// result += translateNode(ifElse.ifScope)
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// val afterIfLabel = createLabelName()
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// addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
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// result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
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// result += IRCodeChunk(afterIfLabel, null)
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// } else {
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// val afterIfLabel = createLabelName()
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// result += IRCodeChunk(null, null).also {
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// it += IRInstruction(Opcode.CMPI, irDtLeft, reg1=tr.resultReg, immediate = 0)
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// it += IRInstruction(Opcode.BSTEQ, labelSymbol = afterIfLabel)
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// TODO("test this")
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// }
|
||||
// result += translateNode(ifElse.ifScope)
|
||||
// result += IRCodeChunk(afterIfLabel, null)
|
||||
// }
|
||||
// return result
|
||||
} else {
|
||||
if (irDtLeft == IRDataType.FLOAT) {
|
||||
val leftTr = expressionEval.translateExpression(condition.left)
|
||||
@ -1200,35 +1269,32 @@ class IRCodeGen(
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
addToResult(result, rightTr, -1, rightTr.resultFpReg)
|
||||
val compResultReg = registers.nextFree()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(
|
||||
Opcode.FCOMP,
|
||||
IRDataType.FLOAT,
|
||||
reg1 = compResultReg,
|
||||
fpReg1 = leftTr.resultFpReg,
|
||||
fpReg2 = rightTr.resultFpReg
|
||||
),
|
||||
null
|
||||
)
|
||||
val elseBranch = when (condition.operator) {
|
||||
"==" -> Opcode.BNE
|
||||
"!=" -> Opcode.BEQ
|
||||
"<" -> Opcode.BGES
|
||||
">" -> Opcode.BLES
|
||||
"<=" -> Opcode.BGTS
|
||||
">=" -> Opcode.BLTS
|
||||
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1 = compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
|
||||
val elseBranch: Opcode
|
||||
var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already
|
||||
when (condition.operator) {
|
||||
"==" -> elseBranch = Opcode.BNE
|
||||
"!=" -> {
|
||||
elseBranch = Opcode.BSTEQ
|
||||
useCmpi = true
|
||||
}
|
||||
"<" -> elseBranch = Opcode.BGES
|
||||
">" -> elseBranch = Opcode.BLES
|
||||
"<=" -> elseBranch = Opcode.BGTS
|
||||
">=" -> elseBranch = Opcode.BLTS
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
if (ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = elseLabel),
|
||||
null
|
||||
)
|
||||
if(useCmpi) {
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0)
|
||||
it += IRInstruction(elseBranch, labelSymbol = elseLabel)
|
||||
}
|
||||
} else
|
||||
addInstr(result, IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = elseLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
@ -1236,11 +1302,13 @@ class IRCodeGen(
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result,
|
||||
IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = afterIfLabel),
|
||||
null
|
||||
)
|
||||
if(useCmpi) {
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = compResultReg, immediate = 0)
|
||||
it += IRInstruction(elseBranch, labelSymbol = afterIfLabel)
|
||||
}
|
||||
} else
|
||||
addInstr(result, IRInstruction(elseBranch, IRDataType.BYTE, reg1 = compResultReg, immediate = 0, labelSymbol = afterIfLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
@ -1251,26 +1319,31 @@ class IRCodeGen(
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val number = (condition.right as? PtNumber)?.number?.toInt()
|
||||
if (number!=null) {
|
||||
elseBranchOpcode = when (condition.operator) {
|
||||
"==" -> Opcode.BNE
|
||||
"!=" -> Opcode.BEQ
|
||||
"<" -> if(signed) Opcode.BGES else Opcode.BGE
|
||||
">" -> if(signed) Opcode.BLES else Opcode.BLE
|
||||
"<=" -> if(signed) Opcode.BGTS else Opcode.BGT
|
||||
">=" -> if(signed) Opcode.BLTS else Opcode.BLT
|
||||
val elseBranch: Opcode
|
||||
var useCmpi = false // for the branch opcodes that have been converted to CMPI + BSTxx form already
|
||||
when (condition.operator) {
|
||||
"==" -> elseBranch = Opcode.BNE
|
||||
"!=" -> {
|
||||
elseBranch = Opcode.BSTEQ
|
||||
useCmpi = true
|
||||
}
|
||||
"<" -> elseBranch = if(signed) Opcode.BGES else Opcode.BGE
|
||||
">" -> elseBranch = if(signed) Opcode.BLES else Opcode.BLE
|
||||
"<=" -> elseBranch = if(signed) Opcode.BGTS else Opcode.BGT
|
||||
">=" -> elseBranch = if(signed) Opcode.BLTS else Opcode.BLT
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
if (ifElse.elseScope.children.isNotEmpty()) {
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = leftTr.resultReg, immediate = number,
|
||||
labelSymbol = elseLabel
|
||||
), null
|
||||
)
|
||||
if(useCmpi) {
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.CMPI, branchDt, reg1 = leftTr.resultReg, immediate = number)
|
||||
it += IRInstruction(elseBranch, labelSymbol = elseLabel)
|
||||
}
|
||||
} else
|
||||
addInstr(result, IRInstruction(elseBranch, branchDt, reg1 = leftTr.resultReg, immediate = number, labelSymbol = elseLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
@ -1278,52 +1351,53 @@ class IRCodeGen(
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = leftTr.resultReg, immediate = number,
|
||||
labelSymbol = afterIfLabel
|
||||
), null
|
||||
)
|
||||
if(useCmpi) {
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.CMPI, branchDt, reg1 = leftTr.resultReg, immediate = number)
|
||||
it += IRInstruction(elseBranch, labelSymbol = afterIfLabel)
|
||||
}
|
||||
} else
|
||||
addInstr(result, IRInstruction(elseBranch, branchDt, reg1 = leftTr.resultReg, immediate = number, labelSymbol = afterIfLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
} else {
|
||||
val rightTr = expressionEval.translateExpression(condition.right)
|
||||
val elseBranch: Opcode
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
when (condition.operator) {
|
||||
"==" -> {
|
||||
elseBranchOpcode = Opcode.BNER
|
||||
elseBranch = Opcode.BNER
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
"!=" -> {
|
||||
elseBranchOpcode = Opcode.BEQR
|
||||
elseBranch = Opcode.BEQR
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
"<" -> {
|
||||
// else part when left >= right
|
||||
elseBranchOpcode = if (signed) Opcode.BGESR else Opcode.BGER
|
||||
elseBranch = if (signed) Opcode.BGESR else Opcode.BGER
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
// else part when left <= right --> right >= left
|
||||
elseBranchOpcode = if (signed) Opcode.BGESR else Opcode.BGER
|
||||
elseBranch = if (signed) Opcode.BGESR else Opcode.BGER
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// else part when left > right
|
||||
elseBranchOpcode = if (signed) Opcode.BGTSR else Opcode.BGTR
|
||||
elseBranch = if (signed) Opcode.BGTSR else Opcode.BGTR
|
||||
elseBranchFirstReg = leftTr.resultReg
|
||||
elseBranchSecondReg = rightTr.resultReg
|
||||
}
|
||||
|
||||
">=" -> {
|
||||
// else part when left < right --> right > left
|
||||
elseBranchOpcode = if (signed) Opcode.BGTSR else Opcode.BGTR
|
||||
elseBranch = if (signed) Opcode.BGTSR else Opcode.BGTR
|
||||
elseBranchFirstReg = rightTr.resultReg
|
||||
elseBranchSecondReg = leftTr.resultReg
|
||||
}
|
||||
@ -1333,13 +1407,7 @@ class IRCodeGen(
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg,
|
||||
labelSymbol = elseLabel
|
||||
), null
|
||||
)
|
||||
addInstr(result, IRInstruction(elseBranch, branchDt, reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg, labelSymbol = elseLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
|
||||
result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
|
||||
@ -1347,13 +1415,7 @@ class IRCodeGen(
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
addInstr(
|
||||
result, IRInstruction(
|
||||
elseBranchOpcode, branchDt,
|
||||
reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg,
|
||||
labelSymbol = afterIfLabel
|
||||
), null
|
||||
)
|
||||
addInstr(result, IRInstruction(elseBranch, branchDt, reg1 = elseBranchFirstReg, reg2 = elseBranchSecondReg, labelSymbol = afterIfLabel), null)
|
||||
result += translateNode(ifElse.ifScope)
|
||||
result += IRCodeChunk(afterIfLabel, null)
|
||||
}
|
||||
@ -1524,7 +1586,10 @@ class IRCodeGen(
|
||||
addToResult(result, countTr, countTr.resultReg, -1)
|
||||
if(constIntValue(repeat.count)==null) {
|
||||
// check if the counter is already zero
|
||||
addInstr(result, IRInstruction(Opcode.BEQ, irDt, reg1=countTr.resultReg, immediate = 0, labelSymbol = skipRepeatLabel), null)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.CMPI, irDt, reg1=countTr.resultReg, immediate = 0)
|
||||
it += IRInstruction(Opcode.BSTEQ, labelSymbol = skipRepeatLabel)
|
||||
}
|
||||
}
|
||||
result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
|
||||
@ -1,20 +1,12 @@
|
||||
%import textio
|
||||
%import floats
|
||||
|
||||
main {
|
||||
ubyte begin = 10
|
||||
ubyte end = 20
|
||||
|
||||
sub start() {
|
||||
ubyte xx
|
||||
for xx in begin to end step 3 {
|
||||
txt.print_ub(xx)
|
||||
txt.spc()
|
||||
}
|
||||
txt.nl()
|
||||
for xx in end to begin step -3 {
|
||||
txt.print_ub(xx)
|
||||
txt.spc()
|
||||
}
|
||||
txt.nl()
|
||||
float xx = 10.1
|
||||
ubyte yy= xx==10.1
|
||||
txt.print_ub(yy)
|
||||
if xx==10.1
|
||||
txt.print("equal")
|
||||
}
|
||||
}
|
||||
|
||||
@ -84,7 +84,6 @@ bstneg address - branch to location if Status bit Negat
|
||||
bstvc address - branch to location if Status bit Overflow is clear
|
||||
bstvs address - branch to location if Status bit Overflow is set
|
||||
beqr reg1, reg2, address - jump to location in program given by location, if reg1 == reg2
|
||||
beq reg1, value, address - jump to location in program given by location, if reg1 == immediate value
|
||||
bner reg1, reg2, address - jump to location in program given by location, if reg1 != reg2
|
||||
bne reg1, value, address - jump to location in program given by location, if reg1 != immediate value
|
||||
bgt reg1, value, address - jump to location in program given by location, if reg1 > immediate value (unsigned)
|
||||
@ -262,7 +261,6 @@ enum class Opcode {
|
||||
BSTVC,
|
||||
BSTVS,
|
||||
BEQR,
|
||||
BEQ,
|
||||
BNER,
|
||||
BNE,
|
||||
BGTR,
|
||||
@ -408,7 +406,6 @@ val OpcodesThatBranch = setOf(
|
||||
Opcode.BSTVC,
|
||||
Opcode.BSTVS,
|
||||
Opcode.BEQR,
|
||||
Opcode.BEQ,
|
||||
Opcode.BNER,
|
||||
Opcode.BNE,
|
||||
Opcode.BGTR,
|
||||
@ -559,7 +556,6 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.BSTVC to InstructionFormat.from("N,<a"),
|
||||
Opcode.BSTVS to InstructionFormat.from("N,<a"),
|
||||
Opcode.BEQR to InstructionFormat.from("BW,<r1,<r2,<a"),
|
||||
Opcode.BEQ to InstructionFormat.from("BW,<r1,<i,<a"),
|
||||
Opcode.BNER to InstructionFormat.from("BW,<r1,<r2,<a"),
|
||||
Opcode.BNE to InstructionFormat.from("BW,<r1,<i,<a"),
|
||||
Opcode.BGTR to InstructionFormat.from("BW,<r1,<r2,<a"),
|
||||
|
||||
@ -23,10 +23,10 @@ class TestInstructions: FunSpec({
|
||||
}
|
||||
|
||||
test("with value") {
|
||||
val ins = IRInstruction(Opcode.BEQ, IRDataType.BYTE, reg1=42, immediate = 0, address = 99)
|
||||
ins.opcode shouldBe Opcode.BEQ
|
||||
val ins = IRInstruction(Opcode.ADD, IRDataType.BYTE, reg1=42, immediate = 0, address = 99)
|
||||
ins.opcode shouldBe Opcode.ADD
|
||||
ins.type shouldBe IRDataType.BYTE
|
||||
ins.reg1direction shouldBe OperandDirection.READ
|
||||
ins.reg1direction shouldBe OperandDirection.READWRITE
|
||||
ins.fpReg1direction shouldBe OperandDirection.UNUSED
|
||||
ins.reg1 shouldBe 42
|
||||
ins.reg2 shouldBe null
|
||||
@ -34,14 +34,14 @@ class TestInstructions: FunSpec({
|
||||
ins.immediate shouldBe 0
|
||||
ins.immediateFp shouldBe null
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.toString() shouldBe "beq.b r42,0,$63"
|
||||
ins.toString() shouldBe "add.b r42,0,$63"
|
||||
}
|
||||
|
||||
test("with label") {
|
||||
val ins = IRInstruction(Opcode.BEQ, IRDataType.WORD, reg1=11, immediate = 0, labelSymbol = "a.b.c")
|
||||
ins.opcode shouldBe Opcode.BEQ
|
||||
val ins = IRInstruction(Opcode.ADD, IRDataType.WORD, reg1=11, immediate = 0, labelSymbol = "a.b.c")
|
||||
ins.opcode shouldBe Opcode.ADD
|
||||
ins.type shouldBe IRDataType.WORD
|
||||
ins.reg1direction shouldBe OperandDirection.READ
|
||||
ins.reg1direction shouldBe OperandDirection.READWRITE
|
||||
ins.fpReg1direction shouldBe OperandDirection.UNUSED
|
||||
ins.reg1 shouldBe 11
|
||||
ins.reg2 shouldBe null
|
||||
@ -49,7 +49,7 @@ class TestInstructions: FunSpec({
|
||||
ins.immediate shouldBe 0
|
||||
ins.immediateFp shouldBe null
|
||||
ins.labelSymbol shouldBe "a.b.c"
|
||||
ins.toString() shouldBe "beq.w r11,0,a.b.c"
|
||||
ins.toString() shouldBe "add.w r11,0,a.b.c"
|
||||
}
|
||||
|
||||
test("with output registers") {
|
||||
@ -106,19 +106,19 @@ class TestInstructions: FunSpec({
|
||||
|
||||
test("missing type should fail") {
|
||||
shouldThrow<IllegalArgumentException> {
|
||||
IRInstruction(Opcode.BEQ, reg1=42, address=99)
|
||||
IRInstruction(Opcode.ADD, reg1=42, address=99)
|
||||
}
|
||||
}
|
||||
|
||||
test("missing registers should fail") {
|
||||
shouldThrowWithMessage<IllegalArgumentException>("missing reg1") {
|
||||
IRInstruction(Opcode.BEQ, IRDataType.BYTE, immediate = 0, address=99)
|
||||
IRInstruction(Opcode.ADD, IRDataType.BYTE, immediate = 0, address=99)
|
||||
}
|
||||
}
|
||||
|
||||
test("missing address should fail") {
|
||||
shouldThrowWithMessage<IllegalArgumentException>("missing an address or labelsymbol") {
|
||||
IRInstruction(Opcode.BEQ, IRDataType.BYTE, immediate = 0, reg1=42)
|
||||
IRInstruction(Opcode.INCM, IRDataType.BYTE)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -197,7 +197,6 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
Opcode.BGTSR -> InsBGTSR(ins)
|
||||
Opcode.BGER -> InsBGER(ins)
|
||||
Opcode.BGESR -> InsBGESR(ins)
|
||||
Opcode.BEQ -> InsBEQ(ins)
|
||||
Opcode.BNE -> InsBNE(ins)
|
||||
Opcode.BGT -> InsBGT(ins)
|
||||
Opcode.BLT -> InsBLT(ins)
|
||||
@ -679,14 +678,6 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsBEQ(i: IRInstruction) {
|
||||
val (left: UInt, right: UInt) = getBranchOperandsImmU(i)
|
||||
if(left==right)
|
||||
branchTo(i)
|
||||
else
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsBNER(i: IRInstruction) {
|
||||
val (left: Int, right: Int) = getBranchOperands(i)
|
||||
if(left!=right)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user