diff --git a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AsmAssignment.kt b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AsmAssignment.kt
index 50dab25eb..29efe73b7 100644
--- a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AsmAssignment.kt
+++ b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AsmAssignment.kt
@@ -41,11 +41,12 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
 {
     val constMemoryAddress by lazy { memory?.addressExpression?.constValue(program)?.number?.toInt() ?: 0}
     val constArrayIndexValue by lazy { array?.indexer?.constIndex() }
-    val asmVarname: String
-        get() = if(array==null)
+    val asmVarname: String by lazy {
+        if (array == null)
             variableAsmName!!
         else
             asmgen.asmVariableName(array.arrayvar)
+    }
 
     lateinit var origAssign: AsmAssignment
 
diff --git a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AssignmentAsmGen.kt b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AssignmentAsmGen.kt
index a24fe73ac..a9bba57dd 100644
--- a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AssignmentAsmGen.kt
+++ b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AssignmentAsmGen.kt
@@ -949,7 +949,8 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
                     lda  #<$sourceName
                     ldy  #>$sourceName+1
                     sta  P8ESTACK_LO,x
-                    sty  P8ESTACK_HI,x
+                    tya
+                    sta  P8ESTACK_HI,x
                     dex""")
             }
             else -> throw AssemblyError("string-assign to weird target")
@@ -1581,7 +1582,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
             }
             TargetStorageKind.STACK -> {
                 when(regs) {
-                    RegisterOrPair.AY -> asmgen.out("  sta  P8ESTACK_LO,x |  sty  P8ESTACK_HI,x |  dex")
+                    RegisterOrPair.AY -> asmgen.out("  sta  P8ESTACK_LO,x |  tya |  sta  P8ESTACK_HI,x |  dex")
                     RegisterOrPair.AX, RegisterOrPair.XY -> throw AssemblyError("can't use X here")
                     in Cx16VirtualRegisters -> {
                         val srcReg = asmgen.asmSymbolName(regs)