Apple-2-SW/prog8
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added missing byte to long type assignment

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Irmen de Jong
2025-10-09 02:52:33 +02:00
parent f85ccd837d
commit f0a67fff8a
3 changed files with 23 additions and 2 deletions
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2
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AsmAssignment.kt
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@@ -121,7 +121,7 @@ internal class AsmAssignTarget(val kind: TargetStorageKind,
in combinedLongRegisters -> { in combinedLongRegisters -> {
val dt = if(signed) DataType.LONG val dt = if(signed) DataType.LONG
else else
TODO("unsigned long") TODO("unsigned long $pos")
AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, dt, scope, pos, register = registers) AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, dt, scope, pos, register = registers)
} }
else -> throw AssemblyError("weird register $registers") else -> throw AssemblyError("weird register $registers")

22
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AssignmentAsmGen.kt
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@@ -2533,6 +2533,7 @@ $endLabel""")
assignRegisterByte(target, CpuRegister.A, valueDt.isSigned, true) assignRegisterByte(target, CpuRegister.A, valueDt.isSigned, true)
return return
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${value.position}")
else -> {} else -> {}
} }
} else if(valueDt.isUnsignedWord) { } else if(valueDt.isUnsignedWord) {
@@ -2554,6 +2555,7 @@ $endLabel""")
// 'cast' uword into a 16 bits register, just assign it // 'cast' uword into a 16 bits register, just assign it
return assignExpressionToRegister(value, target.register!!, targetDt.isSigned) return assignExpressionToRegister(value, target.register!!, targetDt.isSigned)
} }
in combinedLongRegisters -> TODO("assign wprd to long reg ${value.position}")
else -> {} else -> {}
} }
} }
@@ -3197,7 +3199,7 @@ $endLabel""")
sta cx16.${target.register.toString().lowercase()} sta cx16.${target.register.toString().lowercase()}
sty cx16.${target.register.toString().lowercase()}+1""") sty cx16.${target.register.toString().lowercase()}+1""")
} }
else -> throw AssemblyError("can't load address in a single 8-bit register") else -> throw AssemblyError("can only load address into 16 bit register")
} }
} }
TargetStorageKind.POINTER -> pointergen.assignAddressOf(PtrTarget(target), sourceName) TargetStorageKind.POINTER -> pointergen.assignAddressOf(PtrTarget(target), sourceName)
@@ -3436,6 +3438,7 @@ $endLabel""")
else else
asmgen.out(" lda #0 | sta cx16.${target.register.toString().lowercase()}+1") asmgen.out(" lda #0 | sta cx16.${target.register.toString().lowercase()}+1")
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("can't load word in a single 8-bit register") else -> throw AssemblyError("can't load word in a single 8-bit register")
} }
} else { } else {
@@ -3450,6 +3453,7 @@ $endLabel""")
lda $varName+1 lda $varName+1
sta cx16.${target.register.toString().lowercase()}+1""") sta cx16.${target.register.toString().lowercase()}+1""")
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("can't load word in a single 8-bit register") else -> throw AssemblyError("can't load word in a single 8-bit register")
} }
} }
@@ -3627,6 +3631,7 @@ $endLabel""")
lda #0 lda #0
sta cx16.${target.register.toString().lowercase()}+1""") sta cx16.${target.register.toString().lowercase()}+1""")
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
} }
@@ -3958,6 +3963,7 @@ $endLabel""")
if(extendWord) if(extendWord)
extendToMSBofVirtualReg(CpuRegister.A, reg, signed) extendToMSBofVirtualReg(CpuRegister.A, reg, signed)
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
CpuRegister.X -> when(target.register!!) { CpuRegister.X -> when(target.register!!) {
@@ -4009,6 +4015,7 @@ $endLabel""")
if(extendWord) if(extendWord)
extendToMSBofVirtualReg(CpuRegister.X, reg, signed) extendToMSBofVirtualReg(CpuRegister.X, reg, signed)
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
CpuRegister.Y -> when(target.register!!) { CpuRegister.Y -> when(target.register!!) {
@@ -4062,6 +4069,7 @@ $endLabel""")
if(extendWord) if(extendWord)
extendToMSBofVirtualReg(CpuRegister.Y, reg, signed) extendToMSBofVirtualReg(CpuRegister.Y, reg, signed)
} }
in combinedLongRegisters -> TODO("assign byte to long reg ${target.position}")
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
} }
@@ -4726,6 +4734,7 @@ $endLabel""")
lda #0 lda #0
sta cx16.${target.register.toString().lowercase()}+1""") sta cx16.${target.register.toString().lowercase()}+1""")
} }
in combinedLongRegisters -> TODO("assign memory byte into long ${target.position}")
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
TargetStorageKind.POINTER -> pointergen.assignByteMemory(PtrTarget(target), address) TargetStorageKind.POINTER -> pointergen.assignByteMemory(PtrTarget(target), address)
@@ -4761,6 +4770,15 @@ $endLabel""")
lda #0 lda #0
sta cx16.${target.register.toString().lowercase()}+1""") sta cx16.${target.register.toString().lowercase()}+1""")
} }
in combinedLongRegisters -> {
val startreg = target.register.startregname()
asmgen.out("""
sta cx16.$startreg
lda #0
sta cx16.$startreg+1
sta cx16.$startreg+2
sta cx16.$startreg+3""")
}
else -> throw AssemblyError("weird register") else -> throw AssemblyError("weird register")
} }
} }
@@ -4975,6 +4993,7 @@ $endLabel""")
RegisterOrPair.AY -> asmgen.out(" pha | tya | eor #255 | tay | pla | eor #255") RegisterOrPair.AY -> asmgen.out(" pha | tya | eor #255 | tay | pla | eor #255")
RegisterOrPair.XY -> asmgen.out(" txa | eor #255 | tax | tya | eor #255 | tay") RegisterOrPair.XY -> asmgen.out(" txa | eor #255 | tax | tya | eor #255 | tay")
in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers") in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers")
in combinedLongRegisters -> TODO("in place negate long invert ${target.position}")
else -> throw AssemblyError("invalid reg dt for word invert") else -> throw AssemblyError("invalid reg dt for word invert")
} }
} }
@@ -5103,6 +5122,7 @@ $endLabel""")
tay""") tay""")
} }
in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers") in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers")
in combinedLongRegisters -> TODO("in place negate long reg ${target.position}")
else -> throw AssemblyError("invalid reg dt for word neg") else -> throw AssemblyError("invalid reg dt for word neg")
} }
} }

1
examples/test.p8
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@@ -18,6 +18,7 @@ main {
; txt.spc() ; txt.spc()
; txt.print_w(lsw(lv1 >> 8) as word) ; txt.print_w(lsw(lv1 >> 8) as word)
txt.nl() txt.nl()
txt.nl() txt.nl()
lv1 = -9876543 lv1 = -9876543