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https://github.com/irmen/prog8.git
synced 2025-02-18 20:30:43 +00:00
ir: fix more register typing errors
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parent
427451a23f
commit
f42e12bc13
@ -259,17 +259,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val endLabel = codeGen.createLabelName()
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val elementTr = translateExpression(check.needle)
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addToResult(result, elementTr, elementTr.resultReg, -1)
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val boolResultRegister = if(elementDt.isByteOrBool) elementTr.resultReg else codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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for(value in haystack){
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it += IRInstruction(Opcode.CMPI, irType(elementDt), elementTr.resultReg, immediate = value)
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = gottemLabel)
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}
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, elementTr.resultReg, immediate = 0)
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, boolResultRegister, immediate = 0)
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it += IRInstruction(Opcode.JUMP, labelSymbol = endLabel)
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}
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, elementTr.resultReg, immediate = 1), gottemLabel)
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, boolResultRegister, immediate = 1), gottemLabel)
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result += IRCodeChunk(endLabel, null)
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return ExpressionCodeResult(result, IRDataType.BYTE, elementTr.resultReg, -1)
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return ExpressionCodeResult(result, IRDataType.BYTE, boolResultRegister, -1)
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}
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elementDt.isFloat -> throw AssemblyError("containmentchecks for floats should always be done on an array variable with subroutine")
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else -> throw AssemblyError("weird dt $elementDt")
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@ -448,8 +449,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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BaseDataType.UBYTE -> {
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when(valueDt.base) {
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BaseDataType.BOOL, BaseDataType.BYTE, BaseDataType.UWORD, BaseDataType.WORD -> {
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actualResultReg2 = tr.resultReg // just keep the LSB as it is
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BaseDataType.BOOL, BaseDataType.BYTE -> {
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actualResultReg2 = tr.resultReg
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}
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BaseDataType.UWORD, BaseDataType.WORD -> {
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1=actualResultReg2, reg2=tr.resultReg, immediate = 0), null)
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}
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BaseDataType.FLOAT -> {
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actualResultReg2 = codeGen.registers.nextFree()
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@ -460,8 +465,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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BaseDataType.BYTE -> {
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when(valueDt.base) {
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BaseDataType.BOOL, BaseDataType.UBYTE, BaseDataType.UWORD, BaseDataType.WORD -> {
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actualResultReg2 = tr.resultReg // just keep the LSB as it is
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BaseDataType.BOOL, BaseDataType.UBYTE -> {
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actualResultReg2 = tr.resultReg
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}
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BaseDataType.UWORD, BaseDataType.WORD -> {
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.LSIG, IRDataType.BYTE, reg1=actualResultReg2, reg2=tr.resultReg, immediate = 0), null)
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}
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BaseDataType.FLOAT -> {
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actualResultReg2 = codeGen.registers.nextFree()
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@ -60,6 +60,11 @@ IR/VM
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- add BZ and BNZ instructions? To replace CMPI #0 + Branch?
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- fix TODO("IR rol/ror on split words array")
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- fix "<< in array" / ">> in array"
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- sometimes source lines get missing in the output p8ir, for example the first assignment is gone in:
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sub start() {
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cx16.r0L = cx16.r1 as ubyte
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cx16.r0sL = cx16.r1s as byte
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}
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- implement missing operators in AssignmentGen (array shifts etc)
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- fix call() return value handling
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- try to get rid of LSIG opcode again (but this will introduce byte reads from word typed registers...)
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@ -1,90 +1,14 @@
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%import textio
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%import floats
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%zeropage basicsafe
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%option no_sysinit
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main {
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ubyte @shared width
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sub start() {
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bool derp
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float @shared f1,f2
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txt.nl()
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cx16.r0 = $aaaa
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cx16.r1 = $2222
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f1 = 10000
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cx16.r0=10000
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; true false false
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; true true false
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; times 2.
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txt.print_bool(f1 > 8000)
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txt.spc()
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txt.print_bool(f1 > 10000)
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txt.spc()
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txt.print_bool(f1 > 20000)
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txt.nl()
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txt.print_bool(f1 >= 8000)
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txt.spc()
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txt.print_bool(f1 >= 10000)
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txt.spc()
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txt.print_bool(f1 >= 20000)
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txt.nl()
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txt.print_bool(cx16.r0 > 8000)
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txt.spc()
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txt.print_bool(cx16.r0 > 10000)
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txt.spc()
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txt.print_bool(cx16.r0 > 20000)
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txt.nl()
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txt.print_bool(cx16.r0 >= 8000)
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txt.spc()
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txt.print_bool(cx16.r0 >= 10000)
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txt.spc()
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txt.print_bool(cx16.r0 >= 20000)
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txt.nl()
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cx16.r0L=0
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derp=true
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if cx16.r0L==0 and derp
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txt.print("fl is 0\n")
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else
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txt.print("fl is not 0\n")
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if cx16.r0L!=0 and derp
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txt.print("fl is not 0\n")
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else
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txt.print("fl is 0\n")
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cx16.r0L = 1
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if cx16.r0L==0 and derp
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txt.print("fl is 0\n")
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else
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txt.print("fl is not 0\n")
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if cx16.r0L!=0 and derp
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txt.print("fl is not 0\n")
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else
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txt.print("fl is 0\n")
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cx16.r0L=99
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derp=true
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if cx16.r0L==99 and derp
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txt.print("fl is 99\n")
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else
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txt.print("fl is not 99\n")
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if cx16.r0L!=99 and derp
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txt.print("fl is not 99\n")
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else
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txt.print("fl is 99\n")
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cx16.r0L = 122
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if cx16.r0L==99 and derp
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txt.print("fl is 99\n")
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else
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txt.print("fl is not 99\n")
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if cx16.r0L!=99 and derp
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txt.print("fl is not 99\n")
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else
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txt.print("fl is 99\n")
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if width==22 or width==33 {
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cx16.r1++
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}
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}
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}
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@ -143,7 +143,7 @@ class IRFileWriter(private val irProgram: IRProgram, outfileOverride: Path?) {
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regs.append(" r$regnum -> $types")
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if (types.size > 1) {
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regs.append(" !!!! more than one type !!!!\n")
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println("IR: Detected multi-type register usage: $regnum->$types in ${chunk.label} at ${chunk.sourceLinesPositions.firstOrNull()}")
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println("IR: Detected multi-type register usage: $regnum->$types in ${chunk.label} at perhaps ${chunk.sourceLinesPositions.firstOrNull()}")
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}
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else
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regs.append("\n")
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@ -976,6 +976,13 @@ data class IRInstruction(
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}
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private fun determineReg1Type(): IRDataType? {
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if(type==IRDataType.FLOAT) {
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// some float instructions have an integer register as well.
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if(opcode in arrayOf(Opcode.FFROMUB, Opcode.FFROMSB, Opcode.FTOUB, Opcode.FTOSB, Opcode.FCOMP))
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return IRDataType.BYTE
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else
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return IRDataType.WORD
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}
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if(opcode==Opcode.JUMPI || opcode==Opcode.CALLI || opcode==Opcode.STOREZI)
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return IRDataType.WORD
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if(opcode==Opcode.EXT || opcode==Opcode.EXTS)
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@ -990,7 +997,7 @@ data class IRInstruction(
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IRDataType.WORD -> TODO("concat.w from long type")
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else -> null
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}
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if(opcode==Opcode.ASRNM || opcode==Opcode.LSRNM || opcode==Opcode.LSLNM)
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if(opcode==Opcode.ASRNM || opcode==Opcode.LSRNM || opcode==Opcode.LSLNM || opcode==Opcode.SQRT)
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return IRDataType.BYTE
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return this.type
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}
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