mirror of
https://github.com/irmen/prog8.git
synced 2024-07-23 15:29:28 +00:00
fixed sbc and adc
This commit is contained in:
Irmen de Jong
parent
b400010426
commit
fec8db6a75
@ -2,5 +2,6 @@
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<project version="4">
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<component name="VcsDirectoryMappings">
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<mapping directory="$PROJECT_DIR$" vcs="Git" />
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<mapping directory="$PROJECT_DIR$/sim65/test/6502_functional_tests" vcs="Git" />
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</component>
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</project>
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@ -34,7 +34,7 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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fun hexW(number: Address, allowSingleByte: Boolean = false): String {
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val msb = number ushr 8
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val lsb = number and 255
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val lsb = number and 0xff
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return if (msb == 0 && allowSingleByte)
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hexB(lsb)
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else
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@ -332,20 +332,20 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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private fun amZpx() {
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// note: zeropage index will not leave Zp when page boundray is crossed
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fetchedAddress = (readPc() + X) and 255
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fetchedAddress = (readPc() + X) and 0xff
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}
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private fun amZpy() {
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// note: zeropage index will not leave Zp when page boundray is crossed
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fetchedAddress = (readPc() + Y) and 255
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fetchedAddress = (readPc() + Y) and 0xff
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}
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private fun amRel() {
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val relative = readPc()
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fetchedAddress = if (relative >= 0x80)
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PC - (256 - relative)
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else
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PC + relative
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fetchedAddress = if (relative >= 0x80) {
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PC - (256 - relative) and 0xffff
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} else
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PC + relative and 0xffff
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}
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private fun amAbs() {
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@ -386,8 +386,8 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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private fun amIzx() {
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// note: not able to fetch an adress which crosses the page boundary
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fetchedAddress = readPc()
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val lo = read((fetchedAddress + X) and 255)
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val hi = read((fetchedAddress + X + 1) and 255)
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val lo = read((fetchedAddress + X) and 0xff)
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val hi = read((fetchedAddress + X + 1) and 0xff)
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fetchedAddress = lo or (hi shl 8)
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}
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@ -395,23 +395,22 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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// note: not able to fetch an adress which crosses the page boundary
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fetchedAddress = readPc()
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val lo = read(fetchedAddress)
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val hi = read((fetchedAddress + 1) and 255)
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fetchedAddress = Y + (lo or (hi shl 8)) and 65535
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val hi = read((fetchedAddress + 1) and 0xff)
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fetchedAddress = Y + (lo or (hi shl 8)) and 0xffff
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}
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private fun getFetched(): Int {
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return if (currentInstruction.mode == AddrMode.Imm ||
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currentInstruction.mode == AddrMode.Acc ||
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currentInstruction.mode == AddrMode.Imp)
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fetchedData
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else
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read(fetchedAddress)
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}
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private fun getFetched() =
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if (currentInstruction.mode == AddrMode.Imm ||
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currentInstruction.mode == AddrMode.Acc ||
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currentInstruction.mode == AddrMode.Imp)
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fetchedData
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else
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read(fetchedAddress)
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private fun readPc(): Int = bus.read(PC++).toInt()
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private fun pushStackAddr(address: Address) {
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val lo = address and 255
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val lo = address and 0xff
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val hi = (address ushr 8)
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pushStack(hi)
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pushStack(lo)
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@ -717,26 +716,26 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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// and https://sourceforge.net/p/vice-emu/code/HEAD/tree/trunk/vice/src/6510core.c#l598
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// (the implementation below is based on the code used by Vice)
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var tmp = (A and 0xf) + (operand and 0xf) + (if (Status.C) 1 else 0)
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if (tmp > 0x9) tmp += 0x6
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if (tmp > 9) tmp += 6
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tmp = if (tmp <= 0x0f) {
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(tmp and 0xf) + (A and 0xf0) + (operand and 0xf0)
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} else {
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(tmp and 0xf) + (A and 0xf0) + (operand and 0xf0) + 0x10
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}
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Status.Z = ((A + operand + (if (Status.C) 1 else 0)) and 0xff) == 0
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Status.N = (tmp and 0b10000000) != 0
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Status.V = ((A xor tmp) and 0x80) != 0 && ((A xor operand) and 0x80) == 0
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if (tmp > 0x90) tmp += 0x60
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Status.C = tmp > 0xf0
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A = tmp and 255
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Status.Z = A + operand + (if (Status.C) 1 else 0) and 0xff == 0
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Status.N = tmp and 0b10000000 != 0
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Status.V = (A xor tmp) and 0x80 != 0 && (A xor operand) and 0b10000000 == 0
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if (tmp and 0x1f0 > 0x90) tmp += 0x60
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Status.C = tmp > 0xf0 // original: (tmp and 0xff0) > 0xf0
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A = tmp and 0xff
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} else {
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// normal add
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val tmp = operand + A + if (Status.C) 1 else 0
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Status.N = (tmp and 0b10000000) != 0
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Status.Z = (tmp and 255) == 0
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Status.V = ((A xor operand) and 0x80) == 0 && ((A xor tmp) and 0x80) != 0
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Status.C = tmp > 255
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A = tmp and 255
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Status.Z = (tmp and 0xff) == 0
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Status.V = (A xor operand).inv() and (A xor tmp) and 0b10000000 != 0
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Status.C = tmp > 0xff
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A = tmp and 0xff
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}
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}
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@ -749,13 +748,13 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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private fun iAsl() {
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if (currentInstruction.mode == AddrMode.Acc) {
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Status.C = (A and 0b10000000) != 0
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A = (A shl 1) and 255
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A = (A shl 1) and 0xff
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Status.Z = A == 0
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Status.N = (A and 0b10000000) != 0
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} else {
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val data = read(fetchedAddress)
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Status.C = (data and 0b10000000) != 0
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val shifted = (data shl 1) and 255
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val shifted = (data shl 1) and 0xff
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write(fetchedAddress, shifted)
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Status.Z = shifted == 0
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Status.N = (shifted and 0b10000000) != 0
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@ -848,20 +847,20 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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}
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private fun iDec() {
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val data = (read(fetchedAddress) - 1) and 255
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val data = (read(fetchedAddress) - 1) and 0xff
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write(fetchedAddress, data)
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Status.Z = data == 0
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Status.N = (data and 0b10000000) != 0
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}
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private fun iDex() {
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X = (X - 1) and 255
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X = (X - 1) and 0xff
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Status.Z = X == 0
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Status.N = (X and 0b10000000) != 0
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}
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private fun iDey() {
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Y = (Y - 1) and 255
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Y = (Y - 1) and 0xff
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Status.Z = Y == 0
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Status.N = (Y and 0b10000000) != 0
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}
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@ -873,20 +872,20 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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}
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private fun iInc() {
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val data = (read(fetchedAddress) + 1) and 255
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val data = (read(fetchedAddress) + 1) and 0xff
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write(fetchedAddress, data)
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Status.Z = data == 0
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Status.N = (data and 0b10000000) != 0
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}
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private fun iInx() {
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X = (X + 1) and 255
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X = (X + 1) and 0xff
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Status.Z = X == 0
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Status.N = (X and 0b10000000) != 0
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}
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private fun iIny() {
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Y = (Y + 1) and 255
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Y = (Y + 1) and 0xff
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Status.Z = Y == 0
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Status.N = (Y and 0b10000000) != 0
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}
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@ -968,13 +967,13 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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val oldCarry = Status.C
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if (currentInstruction.mode == AddrMode.Acc) {
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Status.C = (A and 0b10000000) != 0
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A = (A shl 1 and 255) or (if (oldCarry) 1 else 0)
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A = (A shl 1 and 0xff) or (if (oldCarry) 1 else 0)
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Status.Z = A == 0
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Status.N = (A and 0b10000000) != 0
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} else {
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val data = read(fetchedAddress)
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Status.C = (data and 0b10000000) != 0
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val shifted = (data shl 1 and 255) or (if (oldCarry) 1 else 0)
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val shifted = (data shl 1 and 0xff) or (if (oldCarry) 1 else 0)
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write(fetchedAddress, shifted)
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Status.Z = shifted == 0
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Status.N = (shifted and 0b10000000) != 0
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@ -1011,29 +1010,29 @@ class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu {
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private fun iSbc() {
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val operand = getFetched()
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val tmp = (A - operand - if (Status.C) 0 else 1) and 65535
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val tmp = (A - operand - if (Status.C) 0 else 1) and 0xffff
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Status.V = (A xor operand) and (A xor tmp) and 0b10000000 != 0
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if (Status.D) {
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// BCD subtract
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// see http://www.6502.org/tutorials/decimal_mode.html
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// and http://nesdev.com/6502.txt
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// and https://sourceforge.net/p/vice-emu/code/HEAD/tree/trunk/vice/src/6510core.c#l1396
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// (the implementation below is based on the code used by Vice)
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var tmpA = ((A and 0xf) - (operand and 0xf) - if (Status.C) 0 else 1) and 65535
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var tmpA = ((A and 0xf) - (operand and 0xf) - if (Status.C) 0 else 1) and 0xffff
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tmpA = if ((tmpA and 0x10) != 0) {
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((tmpA - 6) and 0xf) or (A and 0xf0) - (operand and 0xf0) - 0x10
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} else {
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(tmpA and 0xf) or (A and 0xf0) - (operand and 0xf0)
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}
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if ((tmpA and 0x100) != 0) tmpA -= 0x60
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A = tmpA and 255
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A = tmpA and 0xff
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} else {
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// normal subtract
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A = tmp and 255
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A = tmp and 0xff
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}
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Status.C = tmp < 0x100
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Status.Z = (tmp and 255) == 0
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Status.Z = (tmp and 0xff) == 0
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Status.N = (tmp and 0b10000000) != 0
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Status.V = ((A xor tmp) and 0x80) != 0 && ((A xor operand) and 0x80) != 0
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}
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private fun iSec() {
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1
sim65/test/6502_functional_tests
Submodule
1
sim65/test/6502_functional_tests
Submodule
@ -0,0 +1 @@
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Subproject commit fe99e5616243a1bdbceaf5907390ce4443de7db0
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29
sim65/test/Test6502Functional.kt
Normal file
29
sim65/test/Test6502Functional.kt
Normal file
@ -0,0 +1,29 @@
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import org.junit.jupiter.api.Test
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import sim65.components.Bus
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import sim65.components.Cpu6502
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import sim65.components.Ram
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import kotlin.test.assertEquals
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class Test6502Functional {
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@Test
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fun testFunctional() {
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val cpu = Cpu6502(false)
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val bus = Bus()
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val ram = Ram(0, 0xffff)
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ram.load("test/6502_functional_tests/bin_files/6502_functional_test.bin", 0)
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bus.add(cpu)
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bus.add(ram)
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cpu.reset()
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cpu.PC = 0x0400
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while(cpu.totalCycles < 50000000) {
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cpu.clock()
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}
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cpu.printState()
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val d = cpu.disassemble(ram, cpu.PC-20, cpu.PC+20)
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println(d.joinToString ("\n"))
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}
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}
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@ -23,18 +23,24 @@ class Test6502TestSuite {
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// create the system bus and add device to it.
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// note that the order is relevant w.r.t. where reads and writes are going.
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ram.set(0x02, 0)
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ram.set(0xa002, 0)
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ram.set(0xa003, 0x80)
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ram.set(Cpu6502.IRQ_vector, 0x48)
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ram.set(Cpu6502.IRQ_vector + 1, 0xff)
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ram.set(Cpu6502.RESET_vector, 0x01)
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ram.set(Cpu6502.RESET_vector + 1, 0x08)
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ram.set(0x01fe, 0xff)
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ram.set(0x01ff, 0x7f)
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ram.set(0x8000, 2)
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ram.set(0xa474, 2)
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ram[0x02] = 0
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ram[0xa002] = 0
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ram[0xa003] = 0x80
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ram[Cpu6502.IRQ_vector] = 0x48
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ram[Cpu6502.IRQ_vector + 1] = 0xff
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ram[Cpu6502.RESET_vector] = 0x01
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ram[Cpu6502.RESET_vector + 1] = 0x08
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ram[0x01fe] = 0xff
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ram[0x01ff] = 0x7f
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ram[0x8000] = 2
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ram[0xa474] = 2
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// setup the irq/brk routine
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for(b in listOf(0x48, 0x8A, 0x48, 0x98, 0x48, 0xBA, 0xBD, 0x04,
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0x01, 0x29, 0x10, 0xF0, 0x03, 0x6C, 0x16, 0x03,
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0x6C, 0x14, 0x03).withIndex()) {
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ram[0xff48+b.index] = b.value.toShort()
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}
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bus.add(cpu)
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bus.add(ram)
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}
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@ -446,11 +452,13 @@ class Test6502TestSuite {
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}
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@Test
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@Disabled("c64 6510 specific component")
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fun testCntdef() {
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runTest("cntdef")
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}
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@Test
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@Disabled("c64 6510 specific component")
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fun testCnto2() {
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runTest("cnto2")
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}
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@ -944,6 +952,7 @@ class Test6502TestSuite {
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}
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@Test
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@Disabled("c64 specific component")
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fun testNmi() {
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runTest("nmi")
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}
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@ -1,29 +0,0 @@
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* = $8000
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sec
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lda #$a0
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sta $2000
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ldx $2000
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txa
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tay
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iny
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sty $2001
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ldy #0
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loop lda text,y
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beq end
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sta $d000
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inc $d001
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iny
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jmp loop
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end nop
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bvs loop
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.byte $02 ; invalid opcode
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.byte $02 ; invalid opcode
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.byte $02 ; invalid opcode
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text .enc "screen"
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.text "hello!",0
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.enc "none"
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