mirror of
https://github.com/irmen/prog8.git
synced 2024-09-10 09:54:32 +00:00
added immediate value vm logical instructions because these are so common
This commit is contained in:
parent
314398ba4c
commit
ff1fc28287
@ -111,21 +111,21 @@ internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen:
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code += VmCodeInstruction(Opcode.EXT, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.EXT, VmDataType.BYTE, reg1=resultRegister)
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}
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}
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DataType.BYTE -> {
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DataType.BYTE -> {
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val andReg = codeGen.vmRegisters.nextFree()
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val notNegativeLabel = codeGen.createLabelName()
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val notNegativeLabel = codeGen.createLabelName()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=andReg, value=0x80)
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val compareReg = codeGen.vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.AND, VmDataType.BYTE, reg1=andReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.LOADR, VmDataType.BYTE, reg1=compareReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=andReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.AND, VmDataType.BYTE, reg1=compareReg, value=0x80)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=compareReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.EXT, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.EXT, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeLabel(notNegativeLabel)
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code += VmCodeLabel(notNegativeLabel)
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}
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}
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DataType.WORD -> {
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DataType.WORD -> {
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val andReg = codeGen.vmRegisters.nextFree()
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val notNegativeLabel = codeGen.createLabelName()
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val notNegativeLabel = codeGen.createLabelName()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.WORD, reg1=andReg, value=0x8000)
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val compareReg = codeGen.vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.AND, VmDataType.WORD, reg1=andReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.LOADR, VmDataType.WORD, reg1=compareReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.WORD, reg1=andReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.AND, VmDataType.WORD, reg1=compareReg, value=0x8000)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.WORD, reg1=compareReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.WORD, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.WORD, reg1=resultRegister)
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code += VmCodeLabel(notNegativeLabel)
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code += VmCodeLabel(notNegativeLabel)
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}
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}
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@ -149,10 +149,8 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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code += VmCodeInstruction(Opcode.NEG, vmDt, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.NEG, vmDt, reg1=resultRegister)
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}
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}
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"~" -> {
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"~" -> {
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val regMask = codeGen.vmRegisters.nextFree()
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val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
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val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
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code += VmCodeInstruction(Opcode.LOAD, vmDt, reg1=regMask, value=mask)
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1=resultRegister, value=mask)
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=regMask)
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}
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}
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else -> throw AssemblyError("weird prefix operator")
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else -> throw AssemblyError("weird prefix operator")
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}
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}
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@ -390,9 +388,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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code += translate(comparisonCall, resultRegister, -1)
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code += translate(comparisonCall, resultRegister, -1)
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if(!notEquals)
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if(!notEquals)
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code += VmCodeInstruction(Opcode.INV, vmDt, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.INV, vmDt, reg1=resultRegister)
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val maskReg = codeGen.vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1=resultRegister, value=1)
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code += VmCodeInstruction(Opcode.LOAD, vmDt, reg1=maskReg, value=1)
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1=resultRegister, reg2=maskReg)
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} else {
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} else {
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val rightResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.left, resultRegister, -1)
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@ -462,10 +458,15 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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private fun operatorXor(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorXor(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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if(binExpr.right is PtNumber) {
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt())
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=rightResultReg)
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} else {
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg)
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}
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return code
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return code
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}
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}
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@ -479,10 +480,15 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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if(binExpr.right is PtNumber) {
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt())
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1=resultRegister, reg2=rightResultReg)
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} else {
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg)
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}
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return code
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return code
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}
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}
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@ -496,10 +502,15 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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private fun operatorOr(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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private fun operatorOr(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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if(binExpr.right is PtNumber) {
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt())
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code += VmCodeInstruction(Opcode.OR, vmDt, reg1=resultRegister, reg2=rightResultReg)
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} else {
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg)
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}
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return code
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return code
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}
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}
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@ -3,7 +3,8 @@ TODO
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For next release
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For next release
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^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^
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- vm: add logical instructions taking immediate value as well
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- fix compiler crash (abs(fl)) ; WHY IS THIS GETTING A BOOLEAN CAST???
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- vm why is bb = bb2 and true generating so large code?
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...
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...
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@ -1,18 +1,13 @@
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%import textio
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%import textio
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%import floats
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%zeropage basicsafe
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%zeropage basicsafe
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main {
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main {
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sub start() {
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sub start() {
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bool @shared zz
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float fl
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ubyte xx
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fl = -3.14
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ubyte yy
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floats.print_f(abs(fl)) ; WHY IS THIS GETTING A BOOLEAN CAST???
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txt.nl()
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while xx<42 {
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xx = yy+99
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xx = yy*5
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}
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txt.print_ub(xx)
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}
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}
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}
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}
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@ -126,9 +126,12 @@ LOGICAL/BITWISE
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---------------
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---------------
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All have type b or w.
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All have type b or w.
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and reg1, reg2 - reg1 = reg1 bitwise and reg2
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andr reg1, reg2 - reg1 = reg1 bitwise and reg2
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or reg1, reg2 - reg1 = reg1 bitwise or reg2
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and reg1, value - reg1 = reg1 bitwise and value
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xor reg1, reg2 - reg1 = reg1 bitwise xor reg2
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orr reg1, reg2 - reg1 = reg1 bitwise or reg2
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or reg1, value - reg1 = reg1 bitwise or value
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xorr reg1, reg2 - reg1 = reg1 bitwise xor reg2
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xor reg1, value - reg1 = reg1 bitwise xor value
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inv reg1 - reg1 = bitwise invert of reg1 (all bits flipped)
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inv reg1 - reg1 = bitwise invert of reg1 (all bits flipped)
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
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asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
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@ -265,10 +268,13 @@ enum class Opcode {
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EXT,
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EXT,
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EXTS,
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EXTS,
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ANDR,
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AND,
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AND,
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ANDM,
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ANDM,
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ORR,
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OR,
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OR,
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ORM,
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ORM,
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XORR,
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XOR,
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XOR,
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XORM,
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XORM,
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INV,
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INV,
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@ -567,11 +573,14 @@ val instructionFormats = mutableMapOf(
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Opcode.CMP to InstructionFormat.from("BW,r1,r2"),
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Opcode.CMP to InstructionFormat.from("BW,r1,r2"),
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Opcode.EXT to InstructionFormat.from("BW,r1"),
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Opcode.EXT to InstructionFormat.from("BW,r1"),
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Opcode.EXTS to InstructionFormat.from("BW,r1"),
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Opcode.EXTS to InstructionFormat.from("BW,r1"),
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Opcode.AND to InstructionFormat.from("BW,r1,r2"),
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Opcode.ANDR to InstructionFormat.from("BW,r1,r2"),
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Opcode.AND to InstructionFormat.from("BW,r1,v"),
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Opcode.ANDM to InstructionFormat.from("BW,r1,v"),
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Opcode.ANDM to InstructionFormat.from("BW,r1,v"),
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Opcode.OR to InstructionFormat.from("BW,r1,r2"),
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Opcode.ORR to InstructionFormat.from("BW,r1,r2"),
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Opcode.OR to InstructionFormat.from("BW,r1,v"),
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Opcode.ORM to InstructionFormat.from("BW,r1,v"),
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Opcode.ORM to InstructionFormat.from("BW,r1,v"),
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Opcode.XOR to InstructionFormat.from("BW,r1,r2"),
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Opcode.XORR to InstructionFormat.from("BW,r1,r2"),
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Opcode.XOR to InstructionFormat.from("BW,r1,v"),
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Opcode.XORM to InstructionFormat.from("BW,r1,v"),
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Opcode.XORM to InstructionFormat.from("BW,r1,v"),
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Opcode.INV to InstructionFormat.from("BW,r1"),
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Opcode.INV to InstructionFormat.from("BW,r1"),
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Opcode.INVM to InstructionFormat.from("BW,v"),
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Opcode.INVM to InstructionFormat.from("BW,v"),
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@ -163,10 +163,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.SQRT -> InsSQRT(ins)
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Opcode.SQRT -> InsSQRT(ins)
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Opcode.EXT -> InsEXT(ins)
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Opcode.EXT -> InsEXT(ins)
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Opcode.EXTS -> InsEXTS(ins)
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Opcode.EXTS -> InsEXTS(ins)
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Opcode.ANDR -> InsANDR(ins)
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Opcode.AND -> InsAND(ins)
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Opcode.AND -> InsAND(ins)
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Opcode.ANDM -> InsANDM(ins)
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Opcode.ANDM -> InsANDM(ins)
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Opcode.ORR -> InsORR(ins)
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Opcode.OR -> InsOR(ins)
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Opcode.OR -> InsOR(ins)
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Opcode.ORM -> InsORM(ins)
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Opcode.ORM -> InsORM(ins)
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Opcode.XORR -> InsXORR(ins)
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Opcode.XOR -> InsXOR(ins)
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Opcode.XOR -> InsXOR(ins)
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Opcode.XORM ->InsXORM(ins)
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Opcode.XORM ->InsXORM(ins)
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Opcode.INV -> InsINV(ins)
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Opcode.INV -> InsINV(ins)
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@ -1295,7 +1298,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsAND(i: Instruction) {
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private fun InsANDR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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when(i.type!!) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left and right).toUByte())
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left and right).toUByte())
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@ -1305,6 +1308,15 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsAND(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) and i.value!!.toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) and i.value!!.toUShort())
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VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
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}
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pc++
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}
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private fun InsANDM(i: Instruction) {
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private fun InsANDM(i: Instruction) {
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val address = i.value!!
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val address = i.value!!
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when(i.type!!) {
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when(i.type!!) {
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@ -1323,7 +1335,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsOR(i: Instruction) {
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private fun InsORR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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when(i.type!!) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left or right).toUByte())
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left or right).toUByte())
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@ -1333,6 +1345,15 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsOR(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) or i.value!!.toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) or i.value!!.toUShort())
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VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
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}
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pc++
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}
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private fun InsORM(i: Instruction) {
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private fun InsORM(i: Instruction) {
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val address = i.value!!
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val address = i.value!!
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when(i.type!!) {
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when(i.type!!) {
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@ -1351,7 +1372,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsXOR(i: Instruction) {
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private fun InsXORR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
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when(i.type!!) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left xor right).toUByte())
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (left xor right).toUByte())
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@ -1361,6 +1382,15 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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pc++
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}
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}
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private fun InsXOR(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) xor i.value!!.toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) xor i.value!!.toUShort())
|
||||||
|
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||||
|
}
|
||||||
|
pc++
|
||||||
|
}
|
||||||
|
|
||||||
private fun InsXORM(i: Instruction) {
|
private fun InsXORM(i: Instruction) {
|
||||||
val address = i.value!!
|
val address = i.value!!
|
||||||
when(i.type!!) {
|
when(i.type!!) {
|
||||||
|
Loading…
Reference in New Issue
Block a user