mirror of
https://github.com/irmen/prog8.git
synced 2024-07-05 22:29:04 +00:00
265 lines
7.4 KiB
Lua
265 lines
7.4 KiB
Lua
%import textio
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%import graphics
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%import test_stack
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%zeropage basicsafe
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%option no_sysinit
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; TODO full-screen graphics mode library, in development. (as replacement for the graphics routines in ROM that are constrained to 200 vertical pixels and lores mode only)
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main {
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sub start () {
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ubyte[] modes = [0, 1, 128]
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ubyte mode
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for mode in modes {
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gfx2.set_mode(mode)
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; gfx2.location(20, 50)
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; repeat 200 {
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; gfx2.next_pixel(255)
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; }
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draw()
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cx16.wait(120)
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}
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}
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sub draw() {
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uword offset
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ubyte angle
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uword x
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uword y
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when gfx2.active_mode {
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0, 1 -> {
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for offset in 0 to 90 step 3 {
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for angle in 0 to 255 {
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x = $0008+sin8u(angle)/2
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y = $0008+cos8u(angle)/2
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gfx2.plot(x+offset*2,y+offset, lsb(x+y))
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}
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}
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}
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128 -> {
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for offset in 0 to 190 step 6 {
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for angle in 0 to 255 {
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x = $0008+sin8u(angle)
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y = $0008+cos8u(angle)
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gfx2.plot(x+offset*2,y+offset, 1)
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}
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}
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}
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}
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}
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}
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gfx2 {
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; read-only control variables:
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ubyte active_mode = 255
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uword width = 0
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uword height = 0
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ubyte bpp = 0
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sub set_mode(ubyte mode) {
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; mode 0 = bitmap 320 x 240 x 1c monochrome
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; mode 1 = bitmap 320 x 240 x 256c
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; mode 128 = bitmap 640 x 480 x 1c monochrome
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; ...other modes?
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when mode {
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0 -> {
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; 320 x 240 x 1c
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 64
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cx16.VERA_DC_VSCALE = 64
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cx16.VERA_L1_CONFIG = %00000100
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = 0
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width = 320
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height = 240
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bpp = 1
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}
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1 -> {
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; 320 x 240 x 256c
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 64
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cx16.VERA_DC_VSCALE = 64
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cx16.VERA_L1_CONFIG = %00000111
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = 0
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width = 320
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height = 240
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bpp = 8
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}
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128 -> {
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; 640 x 480 x 1c
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 128
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cx16.VERA_DC_VSCALE = 128
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cx16.VERA_L1_CONFIG = %00000100
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = %00000001
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width = 640
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height = 480
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bpp = 1
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}
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}
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active_mode = mode
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clear_screen()
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}
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sub clear_screen() {
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cx16.VERA_CTRL = 0
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cx16.VERA_ADDR_H = %00010000
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cx16.VERA_ADDR_M = 0
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cx16.VERA_ADDR_L = 0
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when active_mode {
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0 -> {
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; 320 x 240 x 1c
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repeat 240/2/8
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cs_innerloop640()
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}
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1 -> {
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; 320 x 240 x 256c
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repeat 240/2
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cs_innerloop640()
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}
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128 -> {
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; 640 x 480 x 1c
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repeat 480/8
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cs_innerloop640()
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}
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}
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}
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sub plot(uword x, uword y, ubyte color) {
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ubyte[8] bits = [128, 64, 32, 16, 8, 4, 2, 1]
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uword addr
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ubyte value
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when active_mode {
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0 -> {
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addr = x/8 + y*(320/8)
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value = bits[lsb(x)&7]
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cx16.vpoke_or(addr, 0, value)
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}
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128 -> {
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addr = x/8 + y*(640/8)
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value = bits[lsb(x)&7]
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cx16.vpoke_or(addr, 0, value)
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}
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1 -> {
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void addr_mul_320_add_24(y, x) ; 24 bits result is in r0 and r1L
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ubyte bank = lsb(cx16.r1)
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cx16.vpoke(cx16.r0, bank, color)
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}
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}
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; activate vera auto-increment mode so next_pixel() can be used after this
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cx16.VERA_ADDR_H = (cx16.VERA_ADDR_H & %00000111) | %00010000
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return
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}
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sub location(uword x, uword y) {
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uword address
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when active_mode {
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0 -> {
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address = y*(320/8) + x/8
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cx16.vaddr(address, 0, 0, 1)
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}
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128 -> {
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address = y*(640/8) + x/8
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cx16.vaddr(address, 0, 0, 1)
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}
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1 -> {
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void addr_mul_320_add_24(y, x) ; 24 bits result is in r0 and r1L
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ubyte bank = lsb(cx16.r1)
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cx16.vaddr(cx16.r0, bank, 0, 1)
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}
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}
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}
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asmsub next_pixel(ubyte color @A) {
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; -- sets the next pixel byte to the graphics chip.
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; for 8 bpp screens this will plot 1 pixel. for 1 bpp screens it will actually plot 8 pixels at once (bitmask).
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%asm {{
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sta cx16.VERA_DATA0
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rts
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}}
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}
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sub next_pixels(uword pixels, uword amount) {
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repeat msb(amount) {
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repeat 256 {
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cx16.VERA_DATA0 = @(pixels)
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pixels++
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}
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}
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repeat lsb(amount) {
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cx16.VERA_DATA0 = @(pixels)
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pixels++
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}
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}
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asmsub cs_innerloop640() {
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%asm {{
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ldy #80
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- stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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dey
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bne -
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rts
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}}
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}
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asmsub addr_mul_320_add_24(uword address @R0, uword value @AY) -> uword @R0, ubyte @R1 {
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%asm {{
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda cx16.r0
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sta P8ZP_SCRATCH_B1
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lda cx16.r0+1
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sta cx16.r1
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sta P8ZP_SCRATCH_REG
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lda cx16.r0
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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sta cx16.r0
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lda P8ZP_SCRATCH_B1
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clc
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adc P8ZP_SCRATCH_REG
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sta cx16.r0+1
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bcc +
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inc cx16.r1
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+ ; now add the value to this 24-bits number
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lda cx16.r0
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clc
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adc P8ZP_SCRATCH_W1
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sta cx16.r0
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lda cx16.r0+1
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adc P8ZP_SCRATCH_W1+1
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sta cx16.r0+1
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bcc +
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inc cx16.r1
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+ lda cx16.r1
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rts
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}}
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}
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}
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