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585 lines
25 KiB
Python
585 lines
25 KiB
Python
"""
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Programming Language for 6502/6510 microprocessors, codename 'Sick'
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This is the code generator for assignment statements.
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Written by Irmen de Jong (irmen@razorvine.net) - license: GNU GPL 3.0
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"""
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from typing import Callable
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from ..plyparse import Scope, Assignment, AugAssignment, Register, LiteralValue, SymbolName, VarDef, Dereference
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from . import CodeError, preserving_registers, to_hex, Context
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from ..datatypes import REGISTER_BYTES, VarType, DataType
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from ..compile import Zeropage
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def generate_assignment(ctx: Context) -> None:
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assert isinstance(ctx.stmt, Assignment)
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assert not isinstance(ctx.stmt.right, Assignment), "assignment should have been flattened"
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ctx.out("\v\t\t\t; " + ctx.stmt.lineref)
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ctx.out("\v; @todo assignment: {} = {}".format(ctx.stmt.left, ctx.stmt.right))
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# @todo assignment
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def generate_aug_assignment(ctx: Context) -> None:
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# for instance: value += 33
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# (note that with += and -=, values 0..255 usually occur as the more efficient incrdecr statements instead)
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# left: Register, SymbolName, or Dereference. right: Expression/LiteralValue
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out = ctx.out
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stmt = ctx.stmt
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assert isinstance(stmt, AugAssignment)
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out("\v\t\t\t; " + stmt.lineref)
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lvalue = stmt.left
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rvalue = stmt.right
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if isinstance(lvalue, Register):
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if isinstance(rvalue, LiteralValue):
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if type(rvalue.value) is int:
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assert rvalue.value >= 0, "augassign value can't be < 0"
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_generate_aug_reg_int(out, lvalue, stmt.operator, rvalue.value, "", ctx.scope)
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else:
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raise CodeError("constant integer literal or variable required for now", rvalue) # XXX
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elif isinstance(rvalue, SymbolName):
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symdef = ctx.scope.lookup(rvalue.name)
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if isinstance(symdef, VarDef):
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if symdef.vartype == VarType.CONST:
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if symdef.datatype.isinteger():
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assert symdef.value.const_value() >= 0, "augassign value can't be <0" # type: ignore
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_generate_aug_reg_int(out, lvalue, stmt.operator, symdef.value.const_value(), "", ctx.scope) # type: ignore
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else:
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raise CodeError("aug. assignment value must be integer", rvalue)
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elif symdef.datatype == DataType.BYTE:
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_generate_aug_reg_int(out, lvalue, stmt.operator, 0, symdef.name, ctx.scope)
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else:
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raise CodeError("variable must be of type byte for now", rvalue) # XXX
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else:
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raise CodeError("can only use variable name as symbol for aug assign rvalue", rvalue)
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elif isinstance(rvalue, Register):
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if lvalue.datatype == DataType.BYTE and rvalue.datatype == DataType.WORD:
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raise CodeError("cannot assign a combined 16-bit register to a single 8-bit register", rvalue)
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_generate_aug_reg_reg(out, lvalue, stmt.operator, rvalue, ctx.scope)
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elif isinstance(rvalue, Dereference):
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print("warning: {}: using indirect/dereferece is very costly".format(rvalue.sourceref))
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if rvalue.datatype != DataType.BYTE:
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raise CodeError("aug. assignment value must be a byte for now", rvalue)
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if isinstance(rvalue.operand, (LiteralValue, SymbolName)):
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if isinstance(rvalue.operand, LiteralValue):
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what = to_hex(rvalue.operand.value)
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else:
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symdef = rvalue.my_scope().lookup(rvalue.operand.name)
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if isinstance(symdef, VarDef) and symdef.vartype == VarType.MEMORY:
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what = to_hex(symdef.value.value) # type: ignore
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else:
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what = rvalue.operand.name
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out("\vpha\n\vtya\n\vpha") # save A, Y on stack
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out("\vlda " + what)
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out("\vsta il65_lib.SCRATCH_ZPWORD1")
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out("\vlda {:s}+1".format(what))
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out("\vsta il65_lib.SCRATCH_ZPWORD1+1")
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out("\vldy #0")
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out("\vlda (il65_lib.SCRATCH_ZPWORD1), y")
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a_reg = Register(name="A", sourceref=stmt.sourceref) # type: ignore
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if 'A' in lvalue.name:
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raise CodeError("can't yet use register A in this aug assign lhs", lvalue.sourceref) # @todo
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_generate_aug_reg_reg(out, lvalue, stmt.operator, a_reg, ctx.scope)
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if lvalue.name in REGISTER_BYTES:
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out("\vst{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name.lower()))
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else:
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out("\vst{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name[0].lower()))
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out("\vst{:s} il65_lib.SCRATCH_ZP2".format(lvalue.name[1].lower()))
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out("\vpla\n\vtay\n\vpla") # restore A, Y from stack
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if lvalue.name in REGISTER_BYTES:
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out("\vld{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name.lower()))
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else:
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out("\vld{:s} il65_lib.SCRATCH_ZP2".format(lvalue.name[0].lower()))
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out("\vld{:s} il65_lib.SCRATCH_ZP2".format(lvalue.name[1].lower()))
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elif isinstance(rvalue.operand, Register):
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assert rvalue.operand.datatype == DataType.WORD
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reg = rvalue.operand.name
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out("\vst{:s} il65_lib.SCRATCH_ZPWORD1".format(reg[0].lower()))
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out("\vst{:s} il65_lib.SCRATCH_ZPWORD1+1".format(reg[1].lower()))
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out("\vpha\n\vtya\n\vpha") # save A, Y on stack
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out("\vldy #0")
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out("\vlda (il65_lib.SCRATCH_ZPWORD1), y")
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a_reg = Register(name="A", sourceref=stmt.sourceref) # type: ignore
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if 'A' in lvalue.name:
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raise CodeError("can't yet use register A in this aug assign lhs", lvalue.sourceref) # @todo
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_generate_aug_reg_reg(out, lvalue, stmt.operator, a_reg, ctx.scope)
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if lvalue.name != 'X':
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if lvalue.name in REGISTER_BYTES:
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out("\vst{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name.lower()))
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else:
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out("\vst{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name[0].lower()))
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out("\vst{:s} il65_lib.SCRATCH_ZP2".format(lvalue.name[1].lower()))
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out("\vpla\n\vtay\n\vpla") # restore A, Y from stack
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if lvalue.name != 'X':
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if lvalue.name in REGISTER_BYTES:
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out("\vld{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name.lower()))
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else:
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out("\vld{:s} il65_lib.SCRATCH_ZP1".format(lvalue.name[0].lower()))
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out("\vld{:s} il65_lib.SCRATCH_ZP2".format(lvalue.name[1].lower()))
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else:
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raise CodeError("invalid dereference operand type", rvalue)
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else:
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raise CodeError("invalid rvalue type", rvalue)
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elif isinstance(lvalue, SymbolName):
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raise NotImplementedError("symbolname augassign", lvalue) # XXX
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else:
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raise CodeError("aug. assignment only implemented for registers and symbols for now", lvalue, stmt.sourceref) # XXX
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def _generate_aug_reg_int(out: Callable, lvalue: Register, operator: str, rvalue: int, rname: str, scope: Scope) -> None:
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if rname:
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right_str = rname
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else:
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# an immediate value is provided in rvalue
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right_str = "#" + str(rvalue)
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if operator == "+=":
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assert 0 <= rvalue <= 255, "+= value should be 0..255 for now at " + str(lvalue.sourceref) # @todo
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if rvalue > 0:
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_gen_aug_plus_reg_int(lvalue, out, right_str, scope)
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elif operator == "-=":
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assert 0 <= rvalue <= 255, "-= value should be 0..255 for now at " + str(lvalue.sourceref) # @todo
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if rvalue > 0:
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_gen_aug_minus_reg_int(lvalue, out, right_str, scope)
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elif operator == "&=":
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assert 0 <= rvalue <= 255, "&= value should be 0..255 for now at " + str(lvalue.sourceref) # @todo
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if rvalue == 0:
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# output '=0'
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assignment = Assignment(sourceref=lvalue.sourceref) # type: ignore
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assignment.nodes.append(lvalue)
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assignment.nodes.append(LiteralValue(value=0, sourceref=lvalue.sourceref)) # type: ignore
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ctx = Context(out=out, stmt=assignment, scope=scope, floats_enabled=False) # type: ignore
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generate_assignment(ctx)
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else:
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_gen_aug_and_reg_int(lvalue, out, right_str, scope)
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elif operator == "|=":
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assert 0 <= rvalue <= 255, "|= value should be 0..255 for now at " + str(lvalue.sourceref) # @todo
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if rvalue > 0:
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_gen_aug_or_reg_int(lvalue, out, right_str, scope)
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elif operator == "^=":
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assert 0 <= rvalue <= 255, "^= value should be 0..255 for now at " + str(lvalue.sourceref) # @todo
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if rvalue > 0:
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_gen_aug_xor_reg_int(lvalue, out, right_str, scope)
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elif operator == ">>=":
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_gen_aug_shiftright_reg_int(lvalue, out, rname, rvalue, scope)
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elif operator == "<<=":
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_gen_aug_shiftleft_reg_int(lvalue, out, rname, rvalue, scope)
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else:
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raise ValueError("invalid operator: " + operator, str(lvalue.sourceref)) # @todo implement more operators such as *=, /=
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def _generate_aug_reg_reg(out: Callable, lvalue: Register, operator: str, rvalue: Register, scope: Scope) -> None:
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if operator == "+=":
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_gen_aug_plus_reg_reg(lvalue, out, rvalue, scope)
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elif operator == "-=":
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_gen_aug_minus_reg_reg(lvalue, out, rvalue, scope)
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elif operator == "&=":
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_gen_aug_and_reg_reg(lvalue, out, rvalue, scope)
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elif operator == "|=":
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_gen_aug_or_reg_reg(lvalue, out, rvalue, scope)
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elif operator == "^=":
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_gen_aug_xor_reg_reg(lvalue, out, rvalue, scope)
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elif operator == ">>=":
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_gen_aug_shiftright_reg_reg(lvalue, out, rvalue, scope)
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elif operator == "<<=":
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_gen_aug_shiftleft_reg_reg(lvalue, out, rvalue, scope)
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else:
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raise ValueError("invalid operator: " + operator, str(lvalue.sourceref)) # @todo implement more operators such as *=, /=
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def _gen_aug_shiftleft_reg_int(lvalue: Register, out: Callable, rname: str, rvalue: int, scope: Scope) -> None:
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if rname:
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assert lvalue.name in REGISTER_BYTES, "only single registers for now" # @todo <<=.word
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if lvalue.name == "A":
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preserve_regs = {'X'}
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elif lvalue.name == "X":
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preserve_regs = {'A'}
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out("\vtxa")
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elif lvalue.name == "Y":
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preserve_regs = {'A', 'X'}
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out("\vtya")
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with preserving_registers(preserve_regs, scope, out):
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out("\vldx " + rname)
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out("\vjsr il65_lib.asl_A_by_X")
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# put A back into target register
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if lvalue.name == "X":
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out("\vtax")
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elif lvalue.name == "Y":
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out("\vtay")
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else:
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def shifts_A(times: int) -> None:
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if times >= 8:
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out("\vlda #0")
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else:
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for _ in range(min(8, times)):
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out("\vasl a")
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if lvalue.name == "A":
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shifts_A(rvalue)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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shifts_A(rvalue)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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shifts_A(rvalue)
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out("\vtay")
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else:
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raise CodeError("unsupported register for aug assign", str(lvalue)) # @todo <<=.word
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def _gen_aug_shiftright_reg_int(lvalue: Register, out: Callable, rname: str, rvalue: int, scope: Scope) -> None:
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if rname:
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assert lvalue.name in REGISTER_BYTES, "only single registers for now" # @todo >>=.word
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if lvalue.name == "A":
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preserve_regs = {'X'}
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elif lvalue.name == "X":
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preserve_regs = {'A'}
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out("\vtxa")
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elif lvalue.name == "Y":
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preserve_regs = {'A', 'X'}
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out("\vtya")
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with preserving_registers(preserve_regs, scope, out):
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out("\vldx " + rname)
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out("\vjsr il65_lib.lsr_A_by_X")
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# put A back into target register
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if lvalue.name == "X":
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out("\vtax")
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if lvalue.name == "Y":
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out("\vtay")
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else:
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def shifts_A(times: int) -> None:
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if times >= 8:
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out("\vlda #0")
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else:
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for _ in range(min(8, times)):
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out("\vlsr a")
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if lvalue.name == "A":
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shifts_A(rvalue)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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shifts_A(rvalue)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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shifts_A(rvalue)
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out("\vtay")
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else:
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raise CodeError("unsupported register for aug assign", str(lvalue)) # @todo >>=.word
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def _gen_aug_xor_reg_int(lvalue: Register, out: Callable, right_str: str, scope: Scope) -> None:
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if lvalue.name == "A":
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out("\veor " + right_str)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\veor " + right_str)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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out("\veor " + right_str)
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out("\vtay")
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else:
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raise CodeError("unsupported register for aug assign", str(lvalue)) # @todo ^=.word
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def _gen_aug_or_reg_int(lvalue: Register, out: Callable, right_str: str, scope: Scope) -> None:
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if lvalue.name == "A":
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out("\vora " + right_str)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vora " + right_str)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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out("\vora " + right_str)
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out("\vtay")
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else:
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raise CodeError("unsupported register for aug assign", str(lvalue)) # @todo |=.word
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def _gen_aug_and_reg_int(lvalue: Register, out: Callable, right_str: str, scope: Scope) -> None:
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if lvalue.name == "A":
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out("\vand " + right_str)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vand " + right_str)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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out("\vand " + right_str)
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out("\vtay")
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else:
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raise CodeError("unsupported register for aug assign", str(lvalue)) # @todo &=.word
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def _gen_aug_minus_reg_int(lvalue: Register, out: Callable, right_str: str, scope: Scope) -> None:
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if lvalue.name == "A":
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out("\vsec")
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out("\vsbc " + right_str)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vsec")
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out("\vsbc " + right_str)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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out("\vsec")
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out("\vsbc " + right_str)
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out("\vtay")
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elif lvalue.name == "AX":
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out("\vsec")
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out("\vsbc " + right_str)
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out("\vbcs +")
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out("\vdex")
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out("+")
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elif lvalue.name == "AY":
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out("\vsec")
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out("\vsbc " + right_str)
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out("\vbcs +")
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out("\vdey")
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out("+")
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elif lvalue.name == "XY":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vsec")
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out("\vsbc " + right_str)
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out("\vtax")
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out("\vbcs +")
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out("\vdey")
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out("+")
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else:
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raise ValueError("invalid register", str(lvalue))
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def _gen_aug_plus_reg_int(lvalue: Register, out: Callable, right_str: str, scope: Scope) -> None:
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if lvalue.name == "A":
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out("\vclc")
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out("\vadc " + right_str)
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elif lvalue.name == "X":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vclc")
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out("\vadc " + right_str)
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out("\vtax")
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elif lvalue.name == "Y":
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with preserving_registers({'A'}, scope, out):
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out("\vtya")
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out("\vclc")
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out("\vadc " + right_str)
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out("\vtay")
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elif lvalue.name == "AX":
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out("\vclc")
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out("\vadc " + right_str)
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out("\vbcc +")
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out("\vinx")
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out("+")
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elif lvalue.name == "AY":
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out("\vclc")
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out("\vadc " + right_str)
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out("\vbcc +")
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out("\viny")
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out("+")
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elif lvalue.name == "XY":
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with preserving_registers({'A'}, scope, out):
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out("\vtxa")
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out("\vclc")
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out("\vadc " + right_str)
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out("\vtax")
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out("\vbcc +")
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out("\viny")
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out("+")
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else:
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raise ValueError("invalid register", str(lvalue))
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def _gen_aug_shiftleft_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
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if rvalue.name not in REGISTER_BYTES:
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raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo <<=.word
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if lvalue.name == "A":
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out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
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out("\vasl " + to_hex(Zeropage.SCRATCH_B1))
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elif lvalue.name == "X":
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out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vasl " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vasl " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo <<=.word
|
|
|
|
|
|
def _gen_aug_shiftright_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo >>=.word
|
|
if lvalue.name == "A":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
out("\vlsr " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vlsr " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vlsr " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo >>=.word
|
|
|
|
|
|
def _gen_aug_xor_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo ^=.word
|
|
if lvalue.name == "A":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
out("\veor " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\veor " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\veor " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo ^=.word
|
|
|
|
|
|
def _gen_aug_or_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo |=.word
|
|
if lvalue.name == "A":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
out("\vora " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vora " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vora " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo |=.word
|
|
|
|
|
|
def _gen_aug_and_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo &=.word
|
|
if lvalue.name == "A":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
out("\vand " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vand " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vand " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo &=.word
|
|
|
|
|
|
def _gen_aug_minus_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo -=.word
|
|
if lvalue.name == "A":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
out("\vsec")
|
|
out("\vsbc " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vsec")
|
|
out("\vsbc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vsec")
|
|
out("\vsbc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
else:
|
|
raise CodeError("unsupported lvalue register for aug assign", str(lvalue)) # @todo -=.word
|
|
|
|
|
|
def _gen_aug_plus_reg_reg(lvalue: Register, out: Callable, rvalue: Register, scope: Scope) -> None:
|
|
if rvalue.name not in REGISTER_BYTES:
|
|
raise CodeError("unsupported rvalue register for aug assign", str(rvalue)) # @todo +=.word
|
|
out("\vst{:s} {:s}".format(rvalue.name.lower(), to_hex(Zeropage.SCRATCH_B1)))
|
|
if lvalue.name == "A":
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
elif lvalue.name == "X":
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
elif lvalue.name == "Y":
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtya")
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtay")
|
|
elif lvalue.name == "AX":
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vbcc +")
|
|
out("\vinx")
|
|
out("+")
|
|
elif lvalue.name == "AY":
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vbcc +")
|
|
out("\viny")
|
|
out("+")
|
|
elif lvalue.name == "XY":
|
|
with preserving_registers({'A'}, scope, out):
|
|
out("\vtxa")
|
|
out("\vclc")
|
|
out("\vadc " + to_hex(Zeropage.SCRATCH_B1))
|
|
out("\vtax")
|
|
out("\vbcc +")
|
|
out("\viny")
|
|
out("+")
|
|
else:
|
|
raise ValueError("invalid register", str(lvalue))
|