mirror of
https://github.com/irmen/prog8.git
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294 lines
14 KiB
Kotlin
294 lines
14 KiB
Kotlin
package prog8.codegen.intermediate
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.Position
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import prog8.code.core.SignedDatatypes
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import prog8.intermediate.IRCodeChunk
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import prog8.intermediate.IRCodeInstruction
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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internal class AssignmentGen(private val codeGen: IntermediateCodeGen, private val expressionEval: ExpressionGen) {
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internal fun translate(assignment: PtAssignment): IRCodeChunk {
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if(assignment.target.children.single() is PtMachineRegister)
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throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
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return if (assignment.isInplaceAssign)
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translateInplaceAssign(assignment)
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else
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translateRegularAssign(assignment)
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}
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private fun translateInplaceAssign(assignment: PtAssignment): IRCodeChunk {
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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return if(ident!=null) {
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assignSelfInMemory(ident.targetName.joinToString("."), assignment.value, assignment)
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} else if(memory != null) {
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if(memory.address is PtNumber)
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assignSelfInMemoryKnownAddress((memory.address as PtNumber).number.toInt(), assignment.value, assignment)
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else
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fallbackAssign(assignment)
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} else if(array!=null) {
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// NOTE: naive fallback assignment here will sometimes generate code that loads the index value multiple times
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// in a register. It's way too much work to optimize that here - instead, we trust that the generated IL assembly
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// will be optimized later and have the double assignments removed.
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fallbackAssign(assignment)
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} else {
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fallbackAssign(assignment)
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}
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}
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private fun assignSelfInMemoryKnownAddress(
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address: Int,
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value: PtExpression,
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origAssign: PtAssignment
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): IRCodeChunk {
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val vmDt = codeGen.vmType(value.type)
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val code = IRCodeChunk(origAssign.position)
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when(value) {
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is PtIdentifier -> return code // do nothing, x=x null assignment.
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is PtMachineRegister -> return code // do nothing, reg=reg null assignment
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is PtPrefix -> return inplacePrefix(value.operator, vmDt, address, null, value.position)
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is PtBinaryExpression -> return inplaceBinexpr(value.operator, value.right, vmDt, value.type in SignedDatatypes, address, null, origAssign)
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is PtMemoryByte -> {
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return if (!codeGen.options.compTarget.machine.isIOAddress(address.toUInt()))
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code // do nothing, mem=mem null assignment.
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else {
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// read and write a (i/o) memory location to itself.
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val tempReg = codeGen.vmRegisters.nextFree()
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code += IRCodeInstruction(Opcode.LOADM, vmDt, reg1 = tempReg, value = address)
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code += IRCodeInstruction(Opcode.STOREM, vmDt, reg1 = tempReg, value = address)
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code
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}
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}
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else -> return fallbackAssign(origAssign)
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}
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}
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private fun assignSelfInMemory(
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symbol: String,
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value: PtExpression,
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origAssign: PtAssignment
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): IRCodeChunk {
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val vmDt = codeGen.vmType(value.type)
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val code = IRCodeChunk(origAssign.position)
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when(value) {
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is PtIdentifier -> return code // do nothing, x=x null assignment.
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is PtMachineRegister -> return code // do nothing, reg=reg null assignment
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is PtPrefix -> return inplacePrefix(value.operator, vmDt, null, symbol, value.position)
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is PtBinaryExpression -> return inplaceBinexpr(value.operator, value.right, vmDt, value.type in SignedDatatypes, null, symbol, origAssign)
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is PtMemoryByte -> {
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val tempReg = codeGen.vmRegisters.nextFree()
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code += IRCodeInstruction(Opcode.LOADM, vmDt, reg1 = tempReg, labelSymbol = symbol)
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code += IRCodeInstruction(Opcode.STOREM, vmDt, reg1 = tempReg, labelSymbol = symbol)
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return code
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}
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else -> return fallbackAssign(origAssign)
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}
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}
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private fun fallbackAssign(origAssign: PtAssignment): IRCodeChunk {
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if (codeGen.options.slowCodegenWarnings)
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codeGen.errors.warn("indirect code for in-place assignment", origAssign.position)
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return translateRegularAssign(origAssign)
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}
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private fun inplaceBinexpr(
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operator: String,
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operand: PtExpression,
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vmDt: VmDataType,
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signed: Boolean,
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knownAddress: Int?,
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symbol: String?,
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origAssign: PtAssignment
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): IRCodeChunk {
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if(knownAddress!=null) {
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when (operator) {
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"+" -> return expressionEval.operatorPlusInplace(knownAddress, null, vmDt, operand)
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"-" -> return expressionEval.operatorMinusInplace(knownAddress, null, vmDt, operand)
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"*" -> return expressionEval.operatorMultiplyInplace(knownAddress, null, vmDt, operand)
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"/" -> return expressionEval.operatorDivideInplace(knownAddress, null, vmDt, signed, operand)
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"|" -> return expressionEval.operatorOrInplace(knownAddress, null, vmDt, operand)
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"&" -> return expressionEval.operatorAndInplace(knownAddress, null, vmDt, operand)
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"^" -> return expressionEval.operatorXorInplace(knownAddress, null, vmDt, operand)
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"<<" -> return expressionEval.operatorShiftLeftInplace(knownAddress, null, vmDt, operand)
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">>" -> return expressionEval.operatorShiftRightInplace(knownAddress, null, vmDt, signed, operand)
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else -> {}
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}
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} else {
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symbol!!
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when (operator) {
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"+" -> return expressionEval.operatorPlusInplace(null, symbol, vmDt, operand)
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"-" -> return expressionEval.operatorMinusInplace(null, symbol, vmDt, operand)
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"*" -> return expressionEval.operatorMultiplyInplace(null, symbol, vmDt, operand)
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"/" -> return expressionEval.operatorDivideInplace(null, symbol, vmDt, signed, operand)
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"|" -> return expressionEval.operatorOrInplace(null, symbol, vmDt, operand)
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"&" -> return expressionEval.operatorAndInplace(null, symbol, vmDt, operand)
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"^" -> return expressionEval.operatorXorInplace(null, symbol, vmDt, operand)
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"<<" -> return expressionEval.operatorShiftLeftInplace(null, symbol, vmDt, operand)
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">>" -> return expressionEval.operatorShiftRightInplace(null, symbol, vmDt, signed, operand)
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else -> {}
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}
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}
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return fallbackAssign(origAssign)
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}
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private fun inplacePrefix(operator: String, vmDt: VmDataType, knownAddress: Int?, addressSymbol: String?, position: Position): IRCodeChunk {
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val code= IRCodeChunk(position)
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when(operator) {
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"+" -> { }
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"-" -> {
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code += if(knownAddress!=null)
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IRCodeInstruction(Opcode.NEGM, vmDt, value = knownAddress)
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else
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IRCodeInstruction(Opcode.NEGM, vmDt, labelSymbol = addressSymbol)
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}
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"~" -> {
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val regMask = codeGen.vmRegisters.nextFree()
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val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
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code += IRCodeInstruction(Opcode.LOAD, vmDt, reg1=regMask, value = mask)
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code += if(knownAddress!=null)
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IRCodeInstruction(Opcode.XORM, vmDt, reg1=regMask, value = knownAddress)
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else
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IRCodeInstruction(Opcode.XORM, vmDt, reg1=regMask, labelSymbol = addressSymbol)
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}
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else -> throw AssemblyError("weird prefix operator")
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}
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return code
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}
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private fun translateRegularAssign(assignment: PtAssignment): IRCodeChunk {
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// note: assigning array and string values is done via an explicit memcopy/stringcopy function call.
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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val vmDt = codeGen.vmType(assignment.value.type)
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val code = IRCodeChunk(assignment.position)
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var resultRegister = -1
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var resultFpRegister = -1
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val zero = codeGen.isZero(assignment.value)
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if(!zero) {
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// calculate the assignment value
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if (vmDt == VmDataType.FLOAT) {
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resultFpRegister = codeGen.vmRegisters.nextFreeFloat()
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code += expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
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} else {
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resultRegister = if (assignment.value is PtMachineRegister) {
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(assignment.value as PtMachineRegister).register
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} else {
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val reg = codeGen.vmRegisters.nextFree()
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code += expressionEval.translateExpression(assignment.value, reg, -1)
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reg
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}
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}
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}
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if(ident!=null) {
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val symbol = ident.targetName.joinToString(".")
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code += if(zero) {
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IRCodeInstruction(Opcode.STOREZM, vmDt, labelSymbol = symbol)
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} else {
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if (vmDt == VmDataType.FLOAT)
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IRCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, labelSymbol = symbol)
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else
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IRCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, labelSymbol = symbol)
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}
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}
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else if(array!=null) {
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val variable = array.variable.targetName.joinToString(".")
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val itemsize = codeGen.program.memsizer.memorySize(array.type)
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if(array.variable.type==DataType.UWORD) {
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// indexing a pointer var instead of a real array or string
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if(itemsize!=1)
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throw AssemblyError("non-array var indexing requires bytes dt")
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if(array.index.type!=DataType.UBYTE)
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throw AssemblyError("non-array var indexing requires bytes index")
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val idxReg = codeGen.vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, idxReg, -1)
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if(zero) {
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// there's no STOREZIX instruction
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resultRegister = codeGen.vmRegisters.nextFree()
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code += IRCodeInstruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=0)
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}
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code += IRCodeInstruction(Opcode.STOREIX, vmDt, reg1=resultRegister, reg2=idxReg, labelSymbol = variable)
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return code
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}
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val fixedIndex = constIntValue(array.index)
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if(zero) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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code += IRCodeInstruction(Opcode.STOREZM, vmDt, labelSymbol = "$variable+$offset")
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} else {
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val indexReg = codeGen.vmRegisters.nextFree()
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code += loadIndexReg(array, itemsize, indexReg, array.position)
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code += IRCodeInstruction(Opcode.STOREZX, vmDt, reg1=indexReg, labelSymbol = variable)
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}
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} else {
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if(vmDt== VmDataType.FLOAT) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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code += IRCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, labelSymbol = "$variable+$offset")
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} else {
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val indexReg = codeGen.vmRegisters.nextFree()
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code += loadIndexReg(array, itemsize, indexReg, array.position)
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code += IRCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, labelSymbol = variable)
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}
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} else {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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code += IRCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, labelSymbol = "$variable+$offset")
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} else {
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val indexReg = codeGen.vmRegisters.nextFree()
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code += loadIndexReg(array, itemsize, indexReg, array.position)
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code += IRCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, labelSymbol = variable)
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}
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}
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}
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}
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else if(memory!=null) {
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require(vmDt== VmDataType.BYTE)
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if(zero) {
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if(memory.address is PtNumber) {
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code += IRCodeInstruction(Opcode.STOREZM, vmDt, value=(memory.address as PtNumber).number.toInt())
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} else {
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val addressReg = codeGen.vmRegisters.nextFree()
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code += expressionEval.translateExpression(memory.address, addressReg, -1)
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code += IRCodeInstruction(Opcode.STOREZI, vmDt, reg1=addressReg)
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}
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} else {
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if(memory.address is PtNumber) {
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code += IRCodeInstruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt())
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} else {
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val addressReg = codeGen.vmRegisters.nextFree()
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code += expressionEval.translateExpression(memory.address, addressReg, -1)
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code += IRCodeInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg)
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}
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}
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}
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else
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throw AssemblyError("weird assigntarget")
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return code
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}
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private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int, position: Position): IRCodeChunk {
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val code = IRCodeChunk(position)
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if(itemsize==1) {
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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}
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else {
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val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
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mult.children += array.index
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mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
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code += expressionEval.translateExpression(mult, indexReg, -1)
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}
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return code
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}
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} |