mirror of
https://github.com/irmen/prog8.git
synced 2024-11-20 18:31:51 +00:00
235 lines
5.9 KiB
Lua
235 lines
5.9 KiB
Lua
%import textio
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%import diskio
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%import floats
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%import graphics
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%import test_stack
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%zeropage basicsafe
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%option no_sysinit
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main {
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; uword adres
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; ubyte adreshi
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sub start () {
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txt.print("hello\n")
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uword xx
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xx = 777
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%asm {{
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lda xx
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ldy xx+1
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jsr math.mul_word_20
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sta xx
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sty xx+1
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}}
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txt.print_uw(xx)
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txt.chrout('\n')
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xx = 777
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%asm {{
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lda xx
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ldy xx+1
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jsr math.mul_word_40
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sta xx
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sty xx+1
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}}
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txt.print_uw(xx)
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txt.chrout('\n')
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xx = 777
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%asm {{
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lda xx
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ldy xx+1
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jsr math.mul_word_80
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sta xx
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sty xx+1
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}}
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txt.print_uw(xx)
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txt.chrout('\n')
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return
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gfx2.set_mode(128)
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gfx2.clear_screen()
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uword offset
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ubyte angle
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uword x
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uword y
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when gfx2.active_mode {
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0 -> {
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for offset in 0 to 90 step 3 {
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for angle in 0 to 255 {
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x = $0008+sin8u(angle)/2
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y = $0008+cos8u(angle)/2
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gfx2.plot(x+offset*2,y+offset, lsb(x+y))
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}
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}
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}
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128 -> {
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for offset in 0 to 190 step 6 {
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for angle in 0 to 255 {
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x = $0008+sin8u(angle)
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y = $0008+cos8u(angle)
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gfx2.plot(x+offset*2,y+offset, 1)
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}
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}
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}
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}
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}
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}
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gfx2 {
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ubyte active_mode = 255
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uword width = 0
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uword height = 0
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ubyte bpp = 0
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sub set_mode(ubyte mode) {
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; mode 0 = bitmap 320 x 240 x 256c
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; mode 128 = bitmap 640 x 480 x 1c monochrome
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; ...
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when mode {
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0 -> {
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; 320 x 240 x 256c
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 64
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cx16.VERA_DC_VSCALE = 64
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cx16.VERA_L1_CONFIG = %00000111
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = 0
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width = 320
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height = 240
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bpp = 8
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}
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128 -> {
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; 640 x 480 x 1c
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 128
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cx16.VERA_DC_VSCALE = 128
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cx16.VERA_L1_CONFIG = %00000100
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = %00000001
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width = 640
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height = 480
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bpp = 1
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}
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}
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active_mode = mode
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}
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sub clear_screen() {
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when active_mode {
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0 -> {
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; 320 x 240 x 256c
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cx16.VERA_CTRL = 0
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cx16.VERA_ADDR_H = %00010000
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cx16.VERA_ADDR_M = 0
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cx16.VERA_ADDR_L = 0
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repeat 240/4
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cs_innerloop1280()
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}
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128 -> {
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; 640 x 480 x 1c
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cx16.VERA_CTRL = 0
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cx16.VERA_ADDR_H = %00010000
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cx16.VERA_ADDR_M = 0
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cx16.VERA_ADDR_L = 0
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repeat 480/16
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cs_innerloop1280()
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}
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}
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}
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asmsub cs_innerloop1280() {
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%asm {{
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ldy #160
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- stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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dey
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bne -
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rts
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}}
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}
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sub plot(uword x, uword y, ubyte color) {
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uword addr
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ubyte addrhi
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when active_mode {
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0 -> {
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; TODO problem when y>=204 and x=..something... then the address gets > 64K; so we really need 24 bit address calculations...
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addr = y
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addr_mul_24_320()
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addr_add_word_24(x)
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cx16.vpoke(addrhi, addr, color)
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}
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128 -> {
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ubyte[8] bits = [128, 64, 32, 16, 8, 4, 2, 1]
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addr = 0
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addr += y*(640/8)
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addr += x/8
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ubyte pix = cx16.vpeek(0, addr) | bits[lsb(x)&7]
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cx16.vpoke(0, addr, pix)
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}
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}
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; TODO when subs are in front of real code, they generate in place and fuck up the code. Move them to the bottom?
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asmsub addr_mul_24_320() {
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; addr = addr * 256 + addr * 64, bits 16-23 into addrhi
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%asm {{
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lda addr
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sta P8ZP_SCRATCH_B1
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lda addr+1
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sta addrhi
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sta P8ZP_SCRATCH_REG
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lda addr
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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asl a
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rol P8ZP_SCRATCH_REG
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sta addr
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lda P8ZP_SCRATCH_B1
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clc
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adc P8ZP_SCRATCH_REG
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sta addr+1
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bcc +
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inc addrhi
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+ rts
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}}
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}
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asmsub addr_add_word_24(uword w @ AY) {
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%asm {{
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clc
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adc addr
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sta addr
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tya
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adc addr+1
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sta addr+1
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bcc +
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inc addrhi
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+ rts
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}}
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}
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}
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}
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