From 1f20c1cfca7f8f17bdfdf96ae13fb4add5e68d69 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 29 Jan 2017 15:38:12 -0800 Subject: [PATCH] basic functionality for IIc+ --- rom5x/B0_FCDE_patch_coldstart.s | 5 +++ rom5x/B1_CF00_rom5x.s | 39 ++++++++++++++++++++++++ rom5x/B1_FCE1_go_to_rom5x.s | 6 ++++ rom5x/README.md | 2 ++ rom5x/Rakefile | 54 +++++++++++++++++++++++++++++++++ rom5x/iic+.defs | 36 ++++++++++++++++++++++ 6 files changed, 142 insertions(+) create mode 100644 rom5x/B0_FCDE_patch_coldstart.s create mode 100644 rom5x/B1_CF00_rom5x.s create mode 100644 rom5x/B1_FCE1_go_to_rom5x.s create mode 100644 rom5x/README.md create mode 100644 rom5x/Rakefile create mode 100644 rom5x/iic+.defs diff --git a/rom5x/B0_FCDE_patch_coldstart.s b/rom5x/B0_FCDE_patch_coldstart.s new file mode 100644 index 0000000..d7849d2 --- /dev/null +++ b/rom5x/B0_FCDE_patch_coldstart.s @@ -0,0 +1,5 @@ +#include "iic+.defs" +.text +* = $fcde + sta rombank + diff --git a/rom5x/B1_CF00_rom5x.s b/rom5x/B1_CF00_rom5x.s new file mode 100644 index 0000000..332105f --- /dev/null +++ b/rom5x/B1_CF00_rom5x.s @@ -0,0 +1,39 @@ +#include "iic+.defs" +.text +* = rom5x + asl butn1 ; check option key + bcc rd5x ; not pressed, see if RD recoverable + lda #"O" ; flashing "O" + sta $7d0 ; tell user +exit5x lda #>(r5xrtn-1) + pha + lda #<(r5xrtn-1) + pha + ldy #$00 ; in case someone assumes this later + jmp swrts2 +rd5x jsr rdinit ; init ram card and registers + lda pwrup,y ; get power up flag + cmp #pwrbyte ; already initialized? + beq exit5x ; exit if so + jsr testsize ; does not wreck x or y + lda numbanks,y ; get discovered # banks + beq exit5x ; no memory + stz addrl,x ; set slinky address 0 + stz addrm,x + stz addrh,x + lda data,x ; get first byte + cmp #$01 ; boot block? + bne exit5x ; nope + lda data,x ; next byte + beq exit5x ; not bootable if 0 + cmp #$ff ; other likely byte for fresh RAM + beq exit5x ; not bootable if $ff + lda #pwrbyte ; sta pwrup,y + lda #"R" ; tell user + sta $7d0 ; on screen + bra exit5x +rdinit bit rx_mslot*$100 ; activate registers + ldy #rx_mslot ; slot offset + ldy #rx_devno ; register offset + rts + diff --git a/rom5x/B1_FCE1_go_to_rom5x.s b/rom5x/B1_FCE1_go_to_rom5x.s new file mode 100644 index 0000000..deb8cbf --- /dev/null +++ b/rom5x/B1_FCE1_go_to_rom5x.s @@ -0,0 +1,6 @@ +#include "iic+.defs" +.text +* = $fce1 + sta set80col ; instruction we patched over + jmp rom5x + diff --git a/rom5x/README.md b/rom5x/README.md new file mode 100644 index 0000000..081ad04 --- /dev/null +++ b/rom5x/README.md @@ -0,0 +1,2 @@ +# DO NOT EVEN TRY THIS YET :-) + diff --git a/rom5x/Rakefile b/rom5x/Rakefile new file mode 100644 index 0000000..1bb07bb --- /dev/null +++ b/rom5x/Rakefile @@ -0,0 +1,54 @@ +source_rom = "iic+_rom5.bin" +dest_rom = "iic+_rom5x.bin" +rom_base = 0xc000 + +source_files = Rake::FileList.new('*.s') + +desc "Default: clean and build it" +task :default => [:clean, :assemble, :build_rom] do + sh "ls -l #{dest_rom}" +end + +desc "Clean object files" +task :clean do + sh "rm -f #{dest_rom}" + sh "rm -f *.o65" + sh "rm -f *.o65.lbl" +end + +desc "Assemble all source files" +task :assemble => source_files.ext('.o65') + +rule ".o65" => ".s" do |t| + sh "xa -c -o #{t.name} -l #{t.name}.lbl #{t.source}" +end + +desc "Build ROM" +task :build_rom => [:assemble] do + puts "Building ROM image..." + obj_files = Rake::FileList.new('*.o65') + rom = File.read(source_rom) + obj_files.each do |t| + if t =~ /B(\h)_(\h{4})/ + bnum = $1.to_i(16) + badd = $2.to_i(16) + addr = bnum * 16384 + badd - rom_base + puts "Loading #{t} into bank #{bnum} @ #{badd.to_s(16)}, file addr #{addr.to_s(16)}" + fc = File.read(t) + fc.each_byte do |b| + rom.setbyte(addr, b) + addr += 1 + end + else + puts "I dont know where to load #{t}" + end + end + File.write(dest_rom, rom) + puts "ROM image done: #{dest_rom}" +end + +desc "Build SST27SF512 Image" +task :sf512 => [:build_rom] do + sh "cat #{dest_rom} #{dest_rom} > sf512_#{dest_rom}" +end + diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs new file mode 100644 index 0000000..b22fc74 --- /dev/null +++ b/rom5x/iic+.defs @@ -0,0 +1,36 @@ +; hardware +set80col = $c001 +rombank = $c028 +butn0 = $c061 +butn1 = $c062 +addrl = $bff8 +addrm = $bff9 +addrh = $bffa +data = $bffb + +; screen holes +; same as //c firmware listing, need to add $c4 for mem card in slot 4 +sl_scrn1 = $478 - $c0 +sl_scrn2 = $4f8 - $c0 +sl_scrn3 = $578 - $c0 +sl_scrn4 = $5f8 - $c0 +sl_scrn5 = $678 - $c0 +sl_scrn6 = $6f8 - $c0 +sl_scrn7 = $778 - $c0 +sl_scrn8 = $7f8 - $c0 +numbanks = sl_scrn1 +pwrup = sl_scrn7 +sl_devno = $778 + +; values +pwrbyte = $a5 +rx_slot = $4 +rx_mslot = rx_slot + $c0 +rx_devno = rx_slot * $10 + $88 + +; entry points +r5xrtn = $fce1 +rom5x = $cf00 +testsize = $d99f +swrts2 = $c784 +