From 79187ea31e6d7d7ab8d4feb47d206c8faefe553d Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 2 Apr 2017 11:53:48 -0700 Subject: [PATCH] optimize accel5x and fix #4 --- rom4x/Rakefile | 2 +- rom5x/B1_D6CE_rom5x_misc.s | 2 +- rom5x/B1_FD00_accel5x.s | 59 ++++++++++++++++++++++---------------- rom5x/iic+.defs | 2 +- 4 files changed, 37 insertions(+), 28 deletions(-) diff --git a/rom4x/Rakefile b/rom4x/Rakefile index 241e416..4863165 100644 --- a/rom4x/Rakefile +++ b/rom4x/Rakefile @@ -48,7 +48,7 @@ task :build_rom => [:assemble] do rom.setbyte(addr, b) addr += 1 end - puts "\tNote: patched pver #{nzc} nonzero bytes!" if nzc > 0 + puts "\tNote: patched over #{nzc} nonzero bytes!" if nzc > 0 else puts "I dont know where to load #{t}" end diff --git a/rom5x/B1_D6CE_rom5x_misc.s b/rom5x/B1_D6CE_rom5x_misc.s index 38b8337..699974d 100644 --- a/rom5x/B1_D6CE_rom5x_misc.s +++ b/rom5x/B1_D6CE_rom5x_misc.s @@ -80,7 +80,7 @@ msg1 = * .byte $04,$2e,"6 Boot 5.25" .byte $04,$ae,"7 Accelerator" .byte $07,$5f,"By M.G." -msg2: .byte $07,$db,"ROM 5X 02/10/17" +msg2: .byte $07,$db,"ROM 5X 04/02/17" .byte $05,$ae,$00 ; cursor pos in menu msg3: .byte $05,$b0,"SURE? ",$00 diff --git a/rom5x/B1_FD00_accel5x.s b/rom5x/B1_FD00_accel5x.s index 48b2b56..0790cc6 100644 --- a/rom5x/B1_FD00_accel5x.s +++ b/rom5x/B1_FD00_accel5x.s @@ -207,18 +207,15 @@ coldst: lda KBDSAVE ora #$80 sta KBDSAVE jsr MIGINIT -warmst: ldx ACWL - ldy ACWH - lda KBDSAVE +warmst: lda KBDSAVE cmp #ESCKEY bne doinit ; toggle accelerator speed - tya + lda ACWH ; kept in ACWH eor #$08 ; toggle bit 4 - tay + sta ACWH doinit: jsr AUNLK ; unlock registers - jsr ACOND ; set enabled according to y reg - jsr ASETR ; set registers + jsr ASETR1 ; set registers jsr ALOCK ; lock accelerator ; set powerup bytes lda #PWRUPV0 @@ -285,10 +282,19 @@ exinit: rts sta ZIP5A lda #$10 tsb ACWH - rts + lda #$80 + trb ACWH ; z flag is 0 if bit 7 was 0 + bne :+ ; if DHiRes was off + bit ZIP5E ; otherwise make sure it is on + bra :++ +: bit ZIP5F ; make sure it is off +: rts .endproc ; ALOCK ; unlock accelerator registers .proc AUNLK + lda $c07f ; RdDHiRes - bit 7 = 1 if off, 0 if on + and #$80 + tsb ACWH ; put in ACWH lda #$5A sta ZIP5A sta ZIP5A @@ -321,9 +327,10 @@ exinit: rts ora ACWH ; merge in existing ACWH less the bits we cleared above tay ;jsr AUNLK ; Apple code unlocks in write command, prob a bug. - jsr ASETR - ;jsr ALOCK - rts + ;jsr ASETR + ;jsr ALOCK ; bug cont'd. + ;rts + ; fall through .endproc ; AWRIT ; set accelerator registers ; x = new ACWL @@ -342,28 +349,29 @@ exinit: rts ora ZIP5FSV ; merge with existing $c05f values sta ZIP5FSV ; and put back ; now set ZIP registers from MIG RAM - jsr ASETR1 + ;jsr ASETR1 ; plx ; pla ; plp - rts + ;rts + ; fall through .endproc ; ASETR1 ; set accelerator registers from saved values in MIG .proc ASETR1 - ldy ACWH - jsr ACOND ; conditionally enable accelerator - tya - and #$08 ; is it disabled? - bne setdn ; if so, don't change other registers - ldx #$03 ; otherwise set all registers from MIG + ldx #$03 ; set all registers from MIG + stx ZIP5B ; turn on accelerator for writing @loop: lda ZIP5CSV,x sta ZIP5C,x +.if ::TESTBLD + sta MIGRAM+$0c,x ; copy to unused locs for inspection +.endif .if ::ADEBUG sta $300,x ; DEBUG .endif dex bpl @loop -setdn: rts + ldy ACWH ; ACWH + jmp ACOND ; leave accelerator in configured state .endproc ; ASETR1 cmdtable: .word AINIT @@ -396,12 +404,13 @@ cmdtable: .endproc ; AWSPD .endif IACWL: .byte %01100111 ; initial ACWL - same as $C05C -IACWH: .byte %00010000 ; initial ACWH - b6 = 1=paddle fast, b4 = reg 1=lock/0=unlock - ; b3 = 1=accel disable, rest reserved +IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock + ; b3 = 1=accel disable, rest reserved by apple + ; rom5x: b7 = state of DHiRes when accelerator was unlocked IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay .byte %00000000 ; Initial $C05D - $00 = 4MHz .byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc - .byte %00000000 ; Initial $C05F - b7=0 enable L/C accel, b6=0 paddle sync + .byte %01000000 ; Initial $C05F - b7=0 enable L/C accel, b6=1 paddle sync (slow) .if ::ACCMENU ; accelerator config menu ; ---------|---------|---------|---------| @@ -433,8 +442,8 @@ amenu1: jsr disp ; disp menu with Accel Off sta $06c6 sta $06c7 dpdl: lda ZIP5FSV ; 5F register has paddle delay - and #$40 ; bit 6 = paddle delay (1 = defeat) - beq dspd ; 0 = on, skip + and #$40 ; bit 6 = paddle delay (1 = slow) + bne dspd ; 1 = on, skip lda #$e6 ; change on to off in menu sta $0746 sta $0747 diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs index fb0247a..4a91d71 100644 --- a/rom5x/iic+.defs +++ b/rom5x/iic+.defs @@ -1,6 +1,6 @@ ; options newbeep = 0 ; 1 = use IIc+ beep -spdpct = 1 ; 1 = use percent speeds in accel config +spdpct = 0 ; 1 = use percent speeds in accel config ; hardware