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Merge branch 'accel5x'

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mgcaret 2017-04-08 14:03:23 -07:00
commit bbb10a55d8
30 changed files with 902 additions and 183 deletions
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5
.gitignore vendored
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@ -3,5 +3,10 @@
*.bin
*.swp
*.zip
*.o
*.lst
*.b
*.po
copyrom.sh
rom5x/accel5x

2
README.md
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@ -125,7 +125,7 @@ It may work with other ROM dumps, it will *not* work with any other ROM version,
Place the ROM dump in the directory with the other files and name it `iic_rom4.bin` for ROM 4X and `iic+_rom5.bin` for ROM 5X.
Now you will need a 65C02 cross assembler. The code was developed using [xa](http://www.floodgap.com/retrotech/xa/), mainly because it was available as a prebuilt binary in my preferred Linux distro's package repositories and supported the 65C02 opcodes.
Now you will need a 65C02 cross assembler. The current codebase is developed using ca65 from the [cc65](http://www.cc65.org/) project. (Note: The code was developed originally using [xa](http://www.floodgap.com/retrotech/xa/)).
Finally you will need [Ruby](https://www.ruby-lang.org/en/) and [Rake](https://github.com/ruby/rake).

6
notes/rom5_zeros.txt
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@ -13,7 +13,7 @@ C572 - 8 bytes
C7FB - 8 bytes
C7FC - 7 bytes
CE00 - 512 bytes not usable (MIG space)
D134 - 76 bytes
D3B5 - 75 bytes - Accelerator menu text
D516 - 234 bytes - ROM 5X boot
D6CE - 306 bytes - ROM 5X misc routines
DB63 - 157 bytes - ROM 5X reset
@ -23,9 +23,9 @@ F7ED - 19 bytes
FB3C - 196 bytes - FBE2 ROM 5X dispatch
- Future: classic beep
FC3C - 12 bytes
FCC9 - 55 bytes
FCC9 - 55 bytes - Accelerator speeds table
FE96 - 352 bytes - but reserve 65816 vectors
- Future ROM 5X accelerator enhancements
- Accelerator enhancements
Other potential usable space:
Aux Bank

14
rom4x/B0_C552_patch_bootfail.s
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@ -1,14 +1,14 @@
#include "iic.defs"
.text
* = $c552
.psc02
.code
.include "iic.defs"
.org $c552
jsr setnorm
jsr init
bra cbtfail
.dsb coma-*,$ea
.res coma-*,$ea
bra coma ; Make sure coma routine exists
.db 0 ; rom4x present
cbtfail jsr setvid
.byte 0 ; rom4x present
cbtfail: jsr setvid
jsr setkbd
lda #>(nbtfail-1)
pha

6
rom4x/B0_C763_switcher.s
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@ -1,6 +1,6 @@
#include "iic.defs"
.text
* = gorst4x
.code
.include "iic.defs"
.org gorst4x
sta rombank ; gorst4x
jmp rst4xrtn ; in other bank jmp reset4x
sta rombank ; gobt4x

7
rom4x/B0_FAB4_patch_pwrup.s
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@ -1,7 +1,6 @@
; patch PWRUP to call boot4x
#include "iic.defs"
.text
* = $fab4
.code
.include "iic.defs"
.org $fab4
nop
jmp gobt4x

7
rom4x/B0_FAC8_patch_reset.s
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@ -1,7 +1,6 @@
; patch RESET.X to call reset4x
#include "iic.defs"
.text
* = $fac8
.code
.include "iic.defs"
.org $fac8
jmp gorst4x

6
rom4x/B1_C763_switcher.s
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@ -1,6 +1,6 @@
#include "iic.defs"
.text
* = gorst4x
.code
.include "iic.defs"
.org gorst4x
sta rombank ; gorst4x
jmp reset4x ; in other bank jmp rstxrtn
sta rombank ; gobt4x

109
rom4x/B1_E000_rom4x.s
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@ -1,15 +1,16 @@
#include "iic.defs"
.text
* = reset4x
.psc02
.code
.include "iic.defs"
.org reset4x
stz power2 + rx_mslot ; action = normal boot
asl butn1 ; closed apple
bcs ckdiag
exitrst jmp gorst4x ; return to RESET.X
exitrst: jmp gorst4x ; return to RESET.X
; check to see if both apples are down
ckdiag bit butn0 ; open apple
ckdiag: bit butn0 ; open apple
bmi exitrst ; return to RESET.X
; present menu because only closed apple is down
menu4x jsr gobanner ; "Apple //c"
menu4x: jsr gobanner ; "Apple //c"
ldx #$00 ; menu start
jsr disp ; show it
jsr gtkey
@ -22,13 +23,13 @@ menu4x jsr gobanner ; "Apple //c"
lda #<(monitor-1)
pha
jmp swrts2 ; rts to enter monitor
ckkey1 cmp #$b2 ; "2"
ckkey1: cmp #$b2 ; "2"
beq doconf
cmp #$b4 ; "4"
bne ckkey2
doconf jsr confirm
doconf: jsr confirm
bne menu4x ; go back to menu4x
ckkey2 sec
ckkey2: sec
sbc #$b0 ; ascii->number
bmi menu4x ; < 0 not valid
cmp #$08
@ -37,35 +38,35 @@ ckkey2 sec
stz softev + 1 ; deinit coldstart
stz pwerdup ; ditto
bra exitrst
gtkey lda #$60
gtkey: lda #$60
sta ($0),y ; cursor
sta kbdstrb ; clr keyboard
kbdin lda kbd ; get key
kbdin: lda kbd ; get key
bpl kbdin
sta kbdstrb ; clear keyboard
sta ($0),y ; put it on screen
rts
; display message, input x = message start relative to msg1
disp stz $0 ; load some safe defaults
disp: stz $0 ; load some safe defaults
lda #$04
sta $1
ldy #$0 ; needs to be zero
disp0 lda msg1,x ; get message byte
disp0: lda msg1,x ; get message byte
bne disp1 ; proceed if nonzero
rts ; exit if 0
disp1 inx ; next byte either way
disp1: inx ; next byte either way
cmp #$20 ; ' '
bcc disp2 ; start of ptr if < 20
eor #$80 ; invert high bit
sta ($0),y ; write to mem
inc $0 ; inc address low byte
bra disp0 ; back to the beginning
disp2 sta $1 ; write address high
disp2: sta $1 ; write address high
lda msg1,x ; get it
sta $0 ; write address low
inx ; set next msg byte
bra disp0 ; back to the beginning
confirm pha
confirm: pha
ldx #(msg3-msg1) ; ask confirm
jsr disp
jsr gtkey
@ -82,20 +83,20 @@ confirm pha
; else are characters to display and will have their
; upper bit inverted before being written to the screen.
msg1 = *
.db $05,$06,"0 Monitor"
.db $05,$86,"1 Reboot"
.db $06,$06,"2 Zero RAM Card and Reboot"
.db $06,$86,"3 Diagnostics"
.db $07,$06,"4 RAM Card Diagnostics"
.db $07,$86,"5 Boot SmartPort"
.db $04,$2e,"6 Boot Int. 5.25"
.db $04,$ae,"7 Boot Ext. 5.25"
.db $07,$5f,"By M.G."
msg2 .db $07,$db,"ROM 4X 01/01/17"
.db $05,$ae,$00 ; cursor pos in menu
msg3 .db $05,$b0,"SURE? ",$00
.dsb boot4x - *, 0
* = boot4x
.byte $05,$06,"0 Monitor"
.byte $05,$86,"1 Reboot"
.byte $06,$06,"2 Zero RAM Card and Reboot"
.byte $06,$86,"3 Diagnostics"
.byte $07,$06,"4 RAM Card Diagnostics"
.byte $07,$86,"5 Boot SmartPort"
.byte $04,$2e,"6 Boot Int. 5.25"
.byte $04,$ae,"7 Boot Ext. 5.25"
.byte $07,$5f,"By M.G."
msg2: .byte $07,$db,"ROM 4X 01/01/17"
.byte $05,$ae,$00 ; cursor pos in menu
msg3: .byte $05,$b0,"SURE? ",$00
.res boot4x - *, 0
.org boot4x
jsr gobanner ; "Apple //c"
jsr rdrecov ; try to recover ramdisk
lda power2 + rx_mslot ; get action saved by reset4x
@ -103,14 +104,14 @@ msg3 .db $05,$b0,"SURE? ",$00
ldx #(msg2-msg1) ; short banner offset
jsr disp ; display it
lda power2 + rx_mslot ; boot selection
btc2 cmp #$02 ; clear ramcard
btc2: cmp #$02 ; clear ramcard
bne btc3
jsr rdclear ; do clear
bra boot4
btc3 cmp #$03 ; Diags
btc3: cmp #$03 ; Diags
bne btc4
jmp $c7c4
btc4 cmp #$04 ; RX diags
btc4: cmp #$04 ; RX diags
bne btc5
ldx #$ff
txs ; reset stack
@ -124,33 +125,33 @@ btc4 cmp #$04 ; RX diags
lda numbanks,y ; get the card size in banks
bne dordiag ; do diag if memory present
jmp swrts2 ; otherwise jump to monitor
dordiag jmp $db3a ; diags
dordiag: jmp $db3a ; diags
;bra boot4
btc5 cmp #$05 ; boot smartport
btc5: cmp #$05 ; boot smartport
beq boot5
btc6 cmp #$06 ; boot int drive
btc6: cmp #$06 ; boot int drive
beq boot6
btc7 cmp #$07 ; boot ext drive
btc7: cmp #$07 ; boot ext drive
bne boot4 ; none of the above
; copy small routine to $800 to boot
; external 5.25
ldy #(bt4xend-bootext+1)
btc7lp lda bootext,y
btc7lp: lda bootext,y
sta $800,y
dey
bpl btc7lp
lda #$08 ; copy done
bra bootsl
boot4 lda #rx_mslot ; boot slot 4
boot4: lda #rx_mslot ; boot slot 4
bra bootsl
boot5 lda #$c5 ; boot slot 5
boot5: lda #$c5 ; boot slot 5
bra bootsl
boot6 lda #$c6 ; boot slot 6
bootsl ldx #$00 ; low byte of slot
bootadr stx $0 ; store address
boot6: lda #$c6 ; boot slot 6
bootsl: ldx #$00 ; low byte of slot
bootadr: stx $0 ; store address
sta $1 ; return to bank 0 does jmp (0)
endbt4x jmp gobt4x ; continue boot
rdrecov jsr rdinit ; init ramcard
endbt4x: jmp gobt4x ; continue boot
rdrecov: jsr rdinit ; init ramcard
lda pwrup,y ; get power up flag
cmp #pwrbyte ; already initialized?
beq recovdn ; exit if initialized
@ -169,11 +170,11 @@ rdrecov jsr rdinit ; init ramcard
beq recovdn ; not bootable
lda #pwrbyte
sta pwrup,y ; set power byte
lda #"R" ; tell user
lda #'R' ; tell user
sta $7d0 ; on screen
recovdn rts
recovdn: rts
; zero ram card space
rdclear jsr rdinit ; init ramcard
rdclear: jsr rdinit ; init ramcard
jsr testsize ; get size
lda numbanks,y ; # of 64Ks to write
beq clrdone ; no memory
@ -182,10 +183,10 @@ rdclear jsr rdinit ; init ramcard
stz addrl,x ; slinky address 0
stz addrm,x
stz addrh,x
clbnklp inc $400 ; poor mans progress meter
clbnklp: inc $400 ; poor mans progress meter
ldy #$00
cl64klp ldx #$00 ; loop for all pages in bank
cl256lp txa ; loop for all bytes in page
cl64klp: ldx #$00 ; loop for all pages in bank
cl256lp: txa ; loop for all bytes in page
ldx #rx_devno
stz data,x ; write a zero to card
tax
@ -196,17 +197,17 @@ cl256lp txa ; loop for all bytes in page
ldx #rx_mslot
dec numbanks,x
bne clbnklp ; if more banks
clrdone ldx #rx_mslot
clrdone: ldx #rx_mslot
stz pwrup,x ; zero powerup byte
lda #$a0 ; ' '
sta $400 ; clear progress
rts
rdinit bit rx_mslot*$100 ; activate registers
rdinit: bit rx_mslot*$100 ; activate registers
ldy #rx_mslot ; slot offset
ldx #rx_devno ; register offset
rts
; next is snippet of code to boot external 5.25
bootext lda #$e0
bootext: lda #$e0
ldy #$01
ldx #$60
jmp $c60b

10
rom4x/B1_E300_new_bootfail.s
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@ -1,8 +1,8 @@
#include "iic.defs"
.text
* = nbtfail
.code
.include "iic.defs"
.org nbtfail
ldx #msglen
lp1 lda bootmsg,x
lp1: lda bootmsg,x
ora #$80
sta $7d0+19-msglen/2,x
dex
@ -14,6 +14,6 @@ lp1 lda bootmsg,x
lda #<(basic-1)
pha
jmp swrts2
bootmsg .db "No bootable device."
bootmsg: .byte "No bootable device."
msglen = * - bootmsg - 1

24
rom4x/Rakefile
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@ -12,33 +12,43 @@ end
desc "Clean object files"
task :clean do
sh "rm -f #{dest_rom}"
sh "rm -f *.o65"
sh "rm -f *.o65.lbl"
sh "rm -f sf512_#{dest_rom}"
sh "rm -f *.o"
sh "rm -f *.lst"
sh "rm -f *.b"
end
desc "Assemble all source files"
task :assemble => source_files.ext('.o65')
task :assemble => source_files.ext('.b')
rule ".o65" => ".s" do |t|
sh "xa -c -o #{t.name} -l #{t.name}.lbl #{t.source}"
rule ".o" => ".s" do |t|
sh "ca65 -l #{t.name}.lst #{t.source}"
end
rule ".b" => ".o" do |t|
sh "ld65 -t none -o #{t.name} #{t.source}"
end
desc "Build ROM"
task :build_rom => [:assemble] do
puts "Building ROM image..."
obj_files = Rake::FileList.new('*.o65')
obj_files = Rake::FileList.new('*.b')
rom = File.read(source_rom)
obj_files.each do |t|
if t =~ /B(\h)_(\h{4})/
bnum = $1.to_i(16)
badd = $2.to_i(16)
addr = bnum * 16384 + badd - rom_base
puts "Loading #{t} into bank #{bnum} @ #{badd.to_s(16)}, file addr #{addr.to_s(16)}"
fc = File.read(t)
fl = fc.bytes.count
puts "Loading #{t} into bank #{bnum} @ #{badd.to_s(16)}, file addr $#{addr.to_s(16)}, len $#{fl.to_s(16)} (#{fl})"
nzc = 0
fc.each_byte do |b|
nzc += 1 if rom.getbyte(addr) != 0 && rom.getbyte(addr) != b
rom.setbyte(addr, b)
addr += 1
end
puts "\tNote: patched over #{nzc} nonzero bytes!" if nzc > 0
else
puts "I dont know where to load #{t}"
end

6
rom5x/B0_CFF9_switch_cmd.s
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@ -5,9 +5,9 @@
; load the command $EA and proceed the same way.
; thus we get two dispatch codes in 6 bytes.
#include "iic+.defs"
.text
* = $cff9 ; 7 bytes available here, but don't count on $CFFF
.include "iic+.defs"
.code
.org $cff9 ; 7 bytes available here, but don't count on $CFFF
lda #$a9 ; lda opcode
nop ; jmp/jsr $cffa does lda #$ea
jmp $fbdf ; jump to bell1 hijack

6
rom5x/B0_FAB4_patch_pwrup.s
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@ -1,7 +1,7 @@
; patch PWRUP to call boot5x
#include "iic+.defs"
.text
* = $fab4
.include "iic+.defs"
.code
.org $fab4
nop
jmp gobt5x

6
rom5x/B0_FAC8_patch_reset.s
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@ -1,7 +1,7 @@
; patch RESET.X to call reset5x
#include "iic+.defs"
.text
* = $fac8
.include "iic+.defs"
.code
.org $fac8
jmp gorst5x

2
rom5x/B0_FB68_center_title.s
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@ -3,6 +3,6 @@
; then displayed it two characters to the *right* rather than one
; or to to the left. It's a major
; pet peeve of mine, more so than the beep.
.text
.code
sta $040d,y

4
rom5x/B0_FBDF_bell1_hijack.s
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@ -15,7 +15,7 @@
; Obviously, $40 should beep the speaker, anything
; else can do whatever we want.
.text
* = $fbdf
.code
.org $fbdf
sta $c028

4
rom5x/B1_C53D_patch_out_rom_cksum.s
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@ -5,8 +5,8 @@
; calculates the checksum. It returns with carry set = error and
; carry clear = OK. So we just patch the JSR to always clear the
; carry. For now.
* = $C53D
.text
.code
.org $C53D
nop
nop
clc

7
rom5x/B1_D3B5_accmenu.s Normal file
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@ -0,0 +1,7 @@
.code
.include "iic+.defs"
.org $d3b5
.proc ACCMENU
.include "accelmenu.h"
.endproc

53
rom5x/B1_D516_boot5x.s
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@ -1,20 +1,21 @@
#include "iic+.defs"
.text
* = boot5x ; 234 bytes available, code assembles to 231
.code
.psc02
.include "iic+.defs"
.org boot5x ; 234 bytes available, code assembles to 222
jsr titl5x ; "Apple IIc +"
jsr rdrecov ; try to recover ramdisk
lda power2 + rx_mslot ; get action saved by reset5x
beq boot4 ; if zero, continue boot
jsr bann5x ; display ROM 5X footer
lda power2 + rx_mslot ; boot selection
btc2 cmp #$02 ; clear ramcard
btc2: cmp #$02 ; clear ramcard
bne btc3
jsr rdclear ; do clear
bra boot4
btc3 cmp #$03 ; Diags
btc3: cmp #$03 ; Diags
bne btc4
jmp $c7c4
btc4 cmp #$04 ; RX diags
btc4: cmp #$04 ; RX diags
bne btc5
ldx #$ff
txs ; reset stack
@ -28,25 +29,25 @@ btc4 cmp #$04 ; RX diags
lda numbanks,y ; get the card size in banks
bne dordiag ; do diag if memory present
jmp swrts2 ; otherwise jump to monitor
dordiag jmp $db3a ; diags
btc5 cmp #$05 ; boot smartport
dordiag: jmp $db3a ; diags
btc5: cmp #$05 ; boot smartport
beq boot5
; fall through if none of the above
boot4 lda #rx_mslot ; boot slot 4
boot4: lda #rx_mslot ; boot slot 4
bra bootsl
boot5 lda #$c5 ; boot slot 5
boot5: lda #$c5 ; boot slot 5
bra bootsl
boot6 lda #$c6 ; boot slot 6
bootsl ldx #$00 ; low byte of slot
bootadr stx $0 ; store address
boot6: lda #$c6 ; boot slot 6
bootsl: ldx #$00 ; low byte of slot
bootadr: stx $0 ; store address
sta $1 ; return to bank 0 does jmp (0)
endbt4x lda #>(bt5xrtn-1)
endbt4x: lda #>(bt5xrtn-1)
pha
lda #<(bt5xrtn-1)
pha
lda $1
jmp swrts2
rdrecov jsr rdinit ; init ramcard
rdrecov: jsr rdinit ; init ramcard
lda pwrup,y ; get power up flag
cmp #pwrbyte ; already initialized?
beq recovdn ; exit if initialized
@ -65,11 +66,11 @@ rdrecov jsr rdinit ; init ramcard
beq recovdn ; not bootable
lda #pwrbyte
sta pwrup,y ; set power byte
lda #"R" ; tell user
lda #'R' ; tell user
sta $7d0 ; on screen
recovdn rts
recovdn: rts
; zero ram card space
rdclear jsr rdinit ; init ramcard
rdclear: jsr rdinit ; init ramcard
jsr testsize ; get size
lda numbanks,y ; # of 64Ks to write
beq clrdone ; no memory
@ -78,10 +79,10 @@ rdclear jsr rdinit ; init ramcard
stz addrl,x ; slinky address 0
stz addrm,x
stz addrh,x
clbnklp inc $400 ; poor mans progress meter
clbnklp: inc $400 ; poor mans progress meter
ldy #$00
cl64klp ldx #$00 ; loop for all pages in bank
cl256lp txa ; loop for all bytes in page
cl64klp: ldx #$00 ; loop for all pages in bank
cl256lp: txa ; loop for all bytes in page
ldx #rx_devno
stz data,x ; write a zero to card
tax
@ -92,20 +93,14 @@ cl256lp txa ; loop for all bytes in page
ldx #rx_mslot
dec numbanks,x
bne clbnklp ; if more banks
clrdone ldx #rx_mslot
clrdone: ldx #rx_mslot
stz pwrup,x ; zero powerup byte
lda #$a0 ; ' '
sta $400 ; clear progress
rts
rdinit bit rx_mslot*$100 ; activate registers
rdinit: bit rx_mslot*$100 ; activate registers
ldy #rx_mslot ; slot offset
ldx #rx_devno ; register offset
rts
; next is snippet of code to boot external 5.25
bootext lda #$e0
ldy #$01
ldx #$60
jmp $c60b
bt4xend = *

51
rom5x/B1_D6CE_rom5x_misc.s
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@ -1,44 +1,45 @@
#include "iic+.defs"
.text
* = misc5x ; max 306 bytes
.code
.psc02
.include "iic+.defs"
.org misc5x ; max 306 bytes
bra domenu ; Display menu
bra dobann ; Display banner (title + By MG)
bra gtkey ; get a key
bra confirm ; ask SURE?
bra ntitle ; display "Apple IIc +"
dobann jsr ntitle
dobann: jsr ntitle
ldx #(msg2-msg1) ; msg display entry point
jmp disp
domenu jsr ntitle ; "Apple ||c +"
domenu: jsr ntitle ; "Apple ||c +"
ldx #$00 ; menu start
jsr disp ; show it
rts
gtkey lda #$60
gtkey: lda #$60
sta ($0),y ; cursor
sta kbdstrb ; clr keyboard
kbdin lda kbd ; get key
kbdin: lda kbd ; get key
bpl kbdin
sta kbdstrb ; clear keyboard
sta ($0),y ; put it on screen
rts
; display message, input x = message start relative to msg1
disp ldy #$0 ; needs to be zero
disp0 lda msg1,x ; get message byte
disp: ldy #$0 ; needs to be zero
disp0: lda msg1,x ; get message byte
bne disp1 ; proceed if nonzero
rts ; exit if 0
disp1 inx ; next byte either way
disp1: inx ; next byte either way
cmp #$20 ; ' '
bcc disp2 ; start of ptr if < 20
eor #$80 ; invert high bit
sta ($0),y ; write to mem
inc $0 ; inc address low byte
bra disp0 ; back to the beginning
disp2 sta $1 ; write address high
disp2: sta $1 ; write address high
lda msg1,x ; get it
sta $0 ; write address low
inx ; set next msg byte
bra disp0 ; back to the beginning
confirm pha
confirm: pha
ldx #(msg3-msg1) ; ask confirm
jsr disp
jsr gtkey
@ -55,7 +56,7 @@ confirm pha
; we then jump to swrts2 which switches banks and RTS to
; display "Apple IIc +", which then RTS to swrts, which
; switches banks back to here and RTS to our caller.
ntitle lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack
ntitle: lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack
pha
lda #<(swrts2-1)
pha
@ -70,16 +71,16 @@ ntitle lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack
; else are characters to display and will have their
; upper bit inverted before being written to the screen.
msg1 = *
.db $05,$06,"0 Monitor"
.db $05,$86,"1 Reboot"
.db $06,$06,"2 Zero RAM Card"
.db $06,$86,"3 Sys Diags"
.db $07,$06,"4 RAM Card Diags"
.db $07,$86,"5 Boot 3.5/SmartPort"
.db $04,$2e,"6 Boot 5.25"
; .db $04,$ae,"7 Accelerator"
.db $07,$5f,"By M.G."
msg2 .db $07,$db,"ROM 5X 02/10/17"
.db $05,$ae,$00 ; cursor pos in menu
msg3 .db $05,$b0,"SURE? ",$00
.byte $05,$06,"0 Monitor"
.byte $05,$86,"1 Reboot"
.byte $06,$06,"2 Zero RAM Card"
.byte $06,$86,"3 Sys Diags"
.byte $07,$06,"4 RAM Card Diags"
.byte $07,$86,"5 Boot 3.5/SmartPort"
.byte $04,$2e,"6 Boot 5.25"
.byte $04,$ae,"7 Accelerator"
.byte $07,$5f,"By M.G."
msg2: .byte $07,$db,"ROM 5X 04/02/17"
.byte $05,$ae,$00 ; cursor pos in menu
msg3: .byte $05,$b0,"SURE? ",$00

23
rom5x/B1_DB63_reset5x.s
View File

@ -1,6 +1,7 @@
#include "iic+.defs"
.text
* = reset5x ; max 157 bytes
.code
.psc02
.include "iic+.defs"
.org reset5x ; max 157 bytes
stz power2 + rx_mslot ; action = normal reset
lda #>(rst5xrtn-1) ; common case
pha
@ -8,12 +9,12 @@
pha ; note that this stays on stack
asl butn1 ; option (closed apple)
bcs ckdiag
exitrst jmp swrts2
exitrst: jmp swrts2
; check to see if cmd_option (both apples) are down
ckdiag bit butn0 ; command (open apple)
ckdiag: bit butn0 ; command (open apple)
bmi exitrst ; return to RESET.X
; present menu because only closed apple is down
menu jsr menu5x ; display menu
menu: jsr menu5x ; display menu
jsr gkey5x
cmp #$b0 ; "0"
bne ckkey1
@ -24,13 +25,17 @@ menu jsr menu5x ; display menu
lda #<(monitor-1)
pha
jmp swrts2 ; rts to enter monitor
ckkey1 cmp #$b2 ; "2"
ckkey1: cmp #$b2 ; "2"
beq doconf
cmp #$b4 ; "4"
bne ckkey2
doconf jsr conf5x
doconf: jsr conf5x
bne menu ; go back to menu4x
ckkey2 sec
ckkey2: cmp #$b7 ; "7"
bne ckkey3
jsr $fd02 ; accelerator menu
bra menu
ckkey3: sec
sbc #$b0 ; ascii->number
bmi menu ; < 0 not valid
cmp #$07 ; we will use 7 for accelerator later

14
rom5x/B1_FB3C_rom5x_dispatch.s
View File

@ -1,17 +1,22 @@
#include "iic+.defs"
.text
* = $fb3c ; ~165 bytes free here
.code
.psc02
.include "iic+.defs"
.org $fb3c ; ~165 bytes free here
cmp #$a9 ; reset patch
bne chk2
jmp reset5x
chk2: cmp #$ea ; boot patch
bne chk3
jmp boot5x
.if newbeep
chk3:
.else
chk3: cmp #$40 ; beep
bne dowait
; "classic air raid beep"
; inspired by http://quinndunki.com/blondihacks/?p=2471
jsr $fcb5 ; (new) WAIT for .1 sec delay
; jsr $fcb5 ; (new) WAIT for .1 sec delay
jsr owait
ldy #$c0
obell2: lda #$0c
jsr owait ; old wait for correct sound
@ -19,6 +24,7 @@ obell2: lda #$0c
dey
bne obell2
bra dexit ; back to caller
.endif
dowait: jsr $fcb5 ; do delay if anything else
lda #>($fbe2-1) ; return to other bank here (in BELL1)
pha ; by pushing address onto

6
rom5x/B1_FBE2_bell1_hijack_b1.s
View File

@ -1,5 +1,5 @@
#include "iic+.defs"
.text
* = $fbe2 ; ~29 bytes free here
.code
.include "iic+.defs"
.org $fbe2 ; ~29 bytes free here
jmp $fb3c

5
rom5x/B1_FCC9_spdtab.s Normal file
View File

@ -0,0 +1,5 @@
.code
.include "iic+.defs"
.org $fcc9
.include "spdtab.h"

600
rom5x/B1_FD00_accel5x.s Normal file
View File

@ -0,0 +1,600 @@
; Improved Apple IIc Plus accelerator firmware
; by M.G.
; Improvements over apple-supplied code:
; * bugs fixed
; * reset+<esc> toggles acclerator on/off rather than setting slow
; * warm reset preserves configured settings
; * additional commands to read/write accelerator speed
; * reset+<tab> configuration menu
; Config menu can be called independently from other alt
; bank firmware, such as ROM 5X
; note that in the current state, the code cannot be inserted
; into the ROM without moving the menu text and the speeds
; table.
.ifdef testaccel
TESTBLD = 1
.else
TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II hw/emulator at $2000
; this disables the bank switch and uses the main RAM at $0E00 to simulate the
; MIG RAM. Will configure a Zip Chip as if it were the IIc+ Accelerator.
.endif
XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands
ACCMENU = 1 ; set to 1 to enable accelerator menu
ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set)
.psc02
.if TESTBLD
; test build of accel code
spdpct = 1
.else
.include "iic+.defs"
.endif
; zero page
ZPAGE = $00
COUNTER = ZPAGE+0 ; used as a generic counter for loops
CALLSP = ZPAGE+1 ; stack pointer at call time
COMMAND = ZPAGE+2 ; command to execute
UBFPTRL = ZPAGE+3 ; user buffer pointer - low byte
UBFPTRH = ZPAGE+4 ; ditto - high byte
EXITCOD = ZPAGE+5 ; exit code from command
; stack
STACK = $0100
; I/O
IOPAGE = $C000
KBD = IOPAGE+$00
KBDSTR = IOPAGE+$10
ZIP5A = IOPAGE+$5A
ZIP5B = IOPAGE+$5B
ZIP5C = IOPAGE+$5C
ZIP5D = IOPAGE+$5D
ZIP5E = IOPAGE+$5E
ZIP5F = IOPAGE+$5F
; MIG
.if ::TESTBLD
MIGBASE = $0E00
.else
MIGBASE = $CE00
.endif
MIGRAM = MIGBASE
PWRUPB0 = MIGRAM+0 ; powerup byte
PWRUPB1 = MIGRAM+1 ; powerup byte
ACWL = MIGRAM+2 ; accelerator control word - low, also ZIP $C05C reg
ACWH = MIGRAM+3 ; accelerator control word - high
KBDSAVE = MIGRAM+4 ; saved keystroke
ZIP5CSV = MIGRAM+5 ; configured $C05C register
ZIP5DSV = MIGRAM+6 ; configured $C05D register
ZIP5ESV = MIGRAM+7 ; configured $C05E register
ZIP5FSV = MIGRAM+8 ; configured $C05F register
ZPSAVE = MIGRAM+$10 ; 8 zero page values saved here
MIGPAG0 = MIGBASE+$A0 ; MIG set page 0
MIGPAGI = MIGBASE+$20 ; MIG increment page
; fixed values
PWRUPV0 = $33
PWRUPV1 = $55
ESCKEY = $9B
TABKEY = $89
; routines we use
WAIT = $FCA8
AUXWAIT = $FCB5
NORMAL = $FC27
SWRTS2 = $C784
.if ::TESTBLD
.org $2000
lda #$00
pha
jsr ACCEL
rts
.else
.org $FD00
.endif
.proc ACCEL
bra accel1
jmp AMENU
accel1: php
sei
phy
phx
bit MIGPAG0
bit MIGPAGI
bit MIGPAGI
; save used ZP locations
ldx #$07
@loop: lda ZPAGE,x
sta ZPSAVE,x
stz ZPAGE,x
dex
bpl @loop
; get command & any parameters
tsx
txa
tay
iny
lda STACK+6,x
sta COMMAND
cmp #$05 ; read accelerator - first command with pointer parameter
stx CALLSP
bcc noparm ; no parameter command
lda STACK+7,x
sta UBFPTRL
lda STACK+8,x
sta UBFPTRH
iny
iny
inx
inx
noparm: inx
txs
ldx CALLSP
lda #$05
sta COUNTER
@loop: lda STACK+5,x
sta STACK+5,y
dex
dey
dec COUNTER
bne @loop
lda COMMAND
.if ::XTRACMD
cmp #$09 ; bad command number?
.else
cmp #$07
.endif
bcc docmd ; no, do command
lda #$01
sta EXITCOD
bra acceldn
docmd: asl a ; calculate jump table offset
tax
jsr dispcmd ; dispatch command
acceldn:
lda EXITCOD
pha
; restore zero page contnets
ldx #$07
@loop: lda ZPSAVE,x
sta ZPAGE,x
dex
bpl @loop ; fixed bug
pla
plx
ply
plp
clc
cmp #$00
beq doexit
sec
doexit:
.if ::TESTBLD
rts
.else
jmp SWRTS2
.endif
dispcmd:
jmp (cmdtable,x)
.endproc ; ACCEL
; Initialize Accelerator (undocumented)
.proc AINIT
; give time for user to hit key
ldx #$03
@loop: lda #$FF
.if ::TESTBLD
jsr WAIT
.else
jsr AUXWAIT
.endif
dex
bne @loop
; now read keyboard
lda KBD
sta KBDSAVE
; check powerup bytes
lda PWRUPB0
cmp #PWRUPV0
bne coldst
lda PWRUPB1
cmp #PWRUPV1
beq warmst
coldst: lda KBDSAVE
ora #$80
sta KBDSAVE
jsr MIGINIT
warmst: lda KBDSAVE
cmp #ESCKEY
bne doinit
; toggle accelerator speed
lda ACWH ; kept in ACWH
eor #$08 ; toggle bit 4
sta ACWH
doinit: jsr AUNLK ; unlock registers
jsr ASETR1 ; set registers
jsr ALOCK ; lock accelerator
; set powerup bytes
lda #PWRUPV0
sta PWRUPB0
lda #PWRUPV1
sta PWRUPB1
.if ::ACCMENU
; now handle keyboard for menu
lda KBDSAVE
cmp #TABKEY
bne initdn
sta KBDSTR
jsr AMENU
.endif
initdn: lda ACWH
and #$08
beq exinit ; 0 if accel enabled
.if ::TESTBLD
lda #$4e
sta $0500
sta KBDSTR
.else
jmp NORMAL
.endif
exinit: rts
.endproc ; AINIT
; initialize values in MIG RAM
.proc MIGINIT
ldx #$03
@loop: lda IREGV,x
sta ZIP5CSV,x
dex
bpl @loop
lda IACWL
sta ACWL
lda IACWH
sta ACWH
rts
.endproc ; MIGINIT
; conditionally enable accelerator according to bit 4 of Y register
.proc ACOND
tya
and #$08
bne ADISA
; otherwise fall through
.endproc ; ACOND
; enable accelerator
.proc AENAB
lda #$08
sta ZIP5B
trb ACWH
rts
.endproc ; AENAB
; disable accelerator
.proc ADISA
lda #$08
sta ZIP5A
tsb ACWH
rts
.endproc ; ADISA
; lock accelerator registers
.proc ALOCK
lda #$A5
sta ZIP5A
lda #$10
tsb ACWH
lda #$80
trb ACWH ; z flag is 0 if bit 7 was 0
bne :+ ; if DHiRes was off
bit ZIP5E ; otherwise make sure it is on
bra :++
: bit ZIP5F ; make sure it is off
: rts
.endproc ; ALOCK
; unlock accelerator registers
.proc AUNLK
lda $c07f ; RdDHiRes - bit 7 = 1 if off, 0 if on
and #$80
tsb ACWH ; put in ACWH
lda #$5A
sta ZIP5A
sta ZIP5A
sta ZIP5A
sta ZIP5A
lda #$10
trb ACWH
rts
.endproc ; AUNLK
; read accelerator
.proc AREAD
ldy #$00
lda ACWL
sta (UBFPTRL),y
iny
lda ACWH
sta (UBFPTRL),y
rts
.endproc ; AREAD
; write accelerator
.proc AWRIT
lda #$40
trb ACWH ; clear writable bits
ldy #$00
lda (UBFPTRL),y
tax
iny
lda (UBFPTRL),y
and #$40 ; all other bits reserved
ora ACWH ; merge in existing ACWH less the bits we cleared above
tay
;jsr AUNLK ; Apple code unlocks in write command, prob a bug.
;jsr ASETR
;jsr ALOCK ; bug cont'd.
;rts
; fall through
.endproc ; AWRIT
; set accelerator registers
; x = new ACWL
; y = new ACWH
.proc ASETR
; php
; pha
; phx
stx ACWL
stx ZIP5CSV
sty ACWH
lda #$40 ; reset paddle speed
trb ZIP5FSV
tya
and #$40 ; mask paddle speed
ora ZIP5FSV ; merge with existing $c05f values
sta ZIP5FSV ; and put back
; now set ZIP registers from MIG RAM
;jsr ASETR1
; plx
; pla
; plp
;rts
; fall through
.endproc ; ASETR1
; set accelerator registers from saved values in MIG
.proc ASETR1
ldx #$03 ; set all registers from MIG
stx ZIP5B ; turn on accelerator for writing
@loop: lda ZIP5CSV,x
sta ZIP5C,x
.if ::TESTBLD
sta MIGRAM+$0c,x ; copy to unused locs for inspection
.endif
.if ::ADEBUG
sta $300,x ; DEBUG
.endif
dex
bpl @loop
ldy ACWH ; ACWH
jmp ACOND ; leave accelerator in configured state
.endproc ; ASETR1
cmdtable:
.word AINIT
.word AENAB
.word ADISA
.word ALOCK
.word AUNLK
.word AREAD
.word AWRIT
.if ::XTRACMD
.word ARSPD
.word AWSPD
; get the accelerator speed register
.proc ARSPD
ldy #$00
lda ZIP5DSV
sta (UBFPTRL),y
rts
.endproc ; ARSPD
; write the accelerator speed register
.proc AWSPD
ldy #$00
lda (UBFPTRL),y
sta ZIP5DSV
tay
jsr AUNLK
sty ZIP5D
jsr ALOCK
rts
.endproc ; AWSPD
.endif
IACWL: .byte %01100111 ; initial ACWL - same as $C05C
IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock
; b3 = 1=accel disable, rest reserved by apple
; rom5x: b7 = state of DHiRes when accelerator was unlocked
IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay
.byte %00000000 ; Initial $C05D - $00 = 4MHz
.byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc
.byte %01000000 ; Initial $C05F - b7=0 enable L/C accel, b6=1 paddle sync (slow)
.if ::ACCMENU
; accelerator config menu
; ---------|---------|---------|---------|
; Accel: On Spk Dly: On
; Speed: 4.00 Pdl Dly: On
;
.proc AMENU
; do this in case someone else calls us outside of AINIT
bit MIGPAG0
bit MIGPAGI
bit MIGPAGI
; save ZP locs we are using
lda COUNTER
pha
lda UBFPTRH
pha
lda UBFPTRL
pha
amenu1: jsr disp ; disp menu with Accel Off
lda ACWH ; get ACWH
and #$08 ; check accelerator enabled
bne aminp ; if not, go to input
ldx #(msg2-msg1) ; rest of menu
jsr disp0 ; on screen
lda ZIP5CSV ; should be same as ACWL
and #$01 ; bit 1 = speaker delay, 1 = enable
bne dpdl ; Skip if enabled
lda #$e6 ; Change on to off in menu
sta $06c6
sta $06c7
dpdl: lda ZIP5FSV ; 5F register has paddle delay
and #$40 ; bit 6 = paddle delay (1 = slow)
bne dspd ; 1 = on, skip
lda #$e6 ; change on to off in menu
sta $0746
sta $0747
dspd: lda ZIP5DSV ; Speed in 5D register
sta COUNTER ; if it is 4 MHz, this will stay 0
tay
beq aminp ; get input since menu already says 4.00
ldx #38 ; # of speeds(20) * 2 - 1
@sloop: lda spdtab,x ; get speed table speed byte
tay
and #$fc ; mask off irrelevant bits we use for MHz
cmp ZIP5DSV ; see if matching
beq dspd1 ; if so, display it
dex ; otherwise, next entry
dex
bpl @sloop
; fall through will say 0.00 MHz or 00%
dspd1: tya
stx COUNTER ; which speed option is selected
.if ::TESTBLD
stx $0e1f ; DEBUG
.endif
.if ::spdpct
lda #$a0 ; space
.else
and #$03 ; MHz value
ora #$b0 ; to digit
.endif
sta $072b ; ones (MHz) or 100s (%)
inx
lda spdtab,x
tay
lsr
lsr
lsr
lsr
ora #$b0
.if ::spdpct
sta $072c ; 10s (%)
.else
sta $072d ; 10ths (MHz)
.endif
tya
and #$0f
ora #$b0
.if ::spdpct
sta $072d ; 1s (%)
.else
sta $072e ; 100ths (MHz)
.endif
aminp: ldy #$00
lda #$60
sta (UBFPTRL),y
@kloop: lda KBD
bpl @kloop
bit KBDSTR
ckrtn: cmp #$8d ; return
beq exit
and #$df ; upper case
ckA: cmp #$c1 ; 'A'
bne ckrest
lda ACWH
eor #$08
sta ACWH
bra tomenu
ckrest: tay
lda ACWH ; get ACWH
and #$08 ; check accelerator enabled
bne tomenu ; if not, do not allow changes
tya
ckrt: cmp #$95 ; right arrow
bne cklt
ldx COUNTER
dex
dex
bmi tomenu
setspd: lda spdtab,x
and #$fc
sta ZIP5DSV
bra tomenu
cklt: cmp #$88 ; left arrow
bne ckS
ldx COUNTER
inx
inx
cpx #35 ; should stop at 0.67
bcc setspd
bra tomenu
ckS: cmp #$d3 ; 'S'
bne ckP
lda ZIP5CSV
eor #$01
sta ZIP5CSV
sta ACWL
bra tomenu
ckP: cmp #$d0 ; 'P'
bne tomenu
lda ZIP5FSV
eor #$40
sta ZIP5FSV
lda ACWH
eor #$40
sta ACWH
tomenu: jmp amenu1
; restore saved values and set accelerator
exit: pla
sta UBFPTRL
pla
sta UBFPTRH
pla
sta COUNTER
jsr AUNLK
jsr ASETR1
jsr ALOCK
jmp dclear
disp: jsr dclear
inx
ldy #$00
disp0: lda msg1,x
bne disp1
rts
disp1: inx
cmp #$20 ; ' '
bcc disp2
eor #$80
sta (UBFPTRL),y
inc UBFPTRL
bra disp0
disp2: sta UBFPTRH
lda msg1,x
sta UBFPTRL
inx
bra disp0
dclear: lda #$a0
ldx #$27
@cloop: sta $0628,x ; line 12
sta $06a8,x ; 13
sta $0728,x ; 14
sta $07a8,x ; 15
dex
bpl @cloop
rts
.if ::TESTBLD
.include "accelmenu.h"
spdtab:
.include "spdtab.h"
.else
msg1 = ::amenu1
msg2 = ::amenu2
.endif
.endproc ; AMENU
; check for run into vector area
.assert * < $ffe0, error, "accel5x overran $ffe0"
.endif

31
rom5x/Rakefile
View File

@ -13,21 +13,28 @@ desc "Clean object files"
task :clean do
sh "rm -f #{dest_rom}"
sh "rm -f sf512_#{dest_rom}"
sh "rm -f *.o65"
sh "rm -f *.o65.lbl"
sh "rm -f *.o"
sh "rm -f *.lst"
sh "rm -f *.b"
sh "rm -f accel5x"
sh "rm -f POOF1 *.po"
end
desc "Assemble all source files"
task :assemble => source_files.ext('.o65')
task :assemble => source_files.ext('.b')
rule ".o65" => ".s" do |t|
sh "xa -c -o #{t.name} -l #{t.name}.lbl #{t.source}"
rule ".o" => ".s" do |t|
sh "ca65 -l #{t.name}.lst #{t.source}"
end
rule ".b" => ".o" do |t|
sh "ld65 -t none -o #{t.name} #{t.source}"
end
desc "Build ROM"
task :build_rom => [:assemble] do
puts "Building ROM image..."
obj_files = Rake::FileList.new('*.o65')
obj_files = Rake::FileList.new('*.b')
rom = File.read(source_rom)
obj_files.each do |t|
if t =~ /B(\h)_(\h{4})/
@ -57,3 +64,15 @@ task :sf512 => [:build_rom] do
sh "cat #{dest_rom} #{dest_rom} > sf512_#{dest_rom}"
end
desc "Build accel5x test binary"
task :accel5x do
sh "ca65 -D testaccel -o accel5x.o -l accel5x.lst B1_FD00_accel5x.s"
sh "ld65 -t none -o accel5x accel5x.o"
end
desc "Build accel5x test binary into accel5x.po disk image"
task :"accel5x.po" => [:accel5x] do
sh "to_pro -140 accel5x"
sh "mv -f POOF1 accel5x.po"
end

12
rom5x/accelmenu.h Normal file
View File

@ -0,0 +1,12 @@
; acclerator menu text
msg1: .byte $06,$a8,$81,"ccel: Off"
.byte $06,$b3,$00
msg2: .byte $06,$b0,"n "
.byte $06,$bc,$93,"pk Dly: On"
.if ::spdpct
.byte $07,$28,$bc,$ad," 100% ",$ad,$be
.else
.byte $07,$28,$bc,$ad," 4.00 MHz ",$ad,$be
.endif
.byte $07,$3c,$90,"dl Dly: On"
.byte $07,$4f,$00

10
rom5x/iic+.defs
View File

@ -1,3 +1,8 @@
; options
newbeep = 0 ; 1 = use IIc+ beep
spdpct = 0 ; 1 = use percent speeds in accel config
; hardware
;set80col = $c001
rombank = $c028
@ -53,3 +58,8 @@ conf5x = gkey5x+2
titl5x = conf5x+2
banner = $fb60
; accel5x locs
amenu1 = $d3b5
amenu2 = amenu1 + $0f
spdtab = $fcc9

4
rom5x/options/accel_reverse/B1_FDD5_accel_reverse.s
View File

@ -5,7 +5,7 @@
; This patch was inspired by Quinn Dunki's functionally equivalent
; firmware mod found here: http://quinndunki.com/blondihacks/?p=2546
.text
* = $fdd5
.code
.org $fdd5
.byte $f0

45
rom5x/spdtab.h Normal file
View File

@ -0,0 +1,45 @@
; this was confirmed by measuring a delay loop
; for each speed. The delay loop was timed
; timed to 1/100 sec accuracy using the Ram
; Express II+ dclock.
.if ::spdpct
; percent speed table for any IIc Plus/Zip Chip
.byte %00000001,$00
.byte %00100000,$83
.byte %00010000,$80
.byte %00001000,$75
.byte %00000100,$67
.byte %01000000,$50
.byte %01100000,$42
.byte %01010000,$40
.byte %01001000,$38
.byte %11000000,$33
.byte %11100000,$28
.byte %11010000,$27
.byte %11001000,$25
.byte %11000100,$22
.byte %10100000,$21
.byte %10010000,$20
.byte %10001000,$19
.byte %10000100,$17
.else
; MHz speed table for 4 MHz IIc Plus
.byte %00000000,$00 ; 4.0000
.byte %00100011,$33 ; 3.3333
.byte %00010011,$20 ; 3.2000
.byte %00001011,$00 ; 3.0000
.byte %00000110,$67 ; 2.6667
.byte %01000010,$00 ; 2.0000
.byte %01100001,$67 ; 1.6667
.byte %01010001,$60 ; 1.6000
.byte %01001001,$50 ; 1.5000
.byte %11000001,$33 ; 1.3333
.byte %11100001,$11 ; 1.1111
.byte %11010001,$07 ; 1.0667
.byte %11001001,$00 ; 1.0000
.byte %11000100,$89 ; 0.8889
.byte %10100000,$83 ; 0.8333
.byte %10010000,$80 ; 0.8000
.byte %10001000,$75 ; 0.7500
.byte %10000100,$67 ; 0.6667
.endif