From 3ac2b9d74f8395bdc2bdd561c2856e1199cc7bb0 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sat, 18 Mar 2017 20:00:43 -0700 Subject: [PATCH 1/8] conversion to cc65 --- .gitignore | 3 + README.md | 2 +- rom4x/B0_C552_patch_bootfail.s | 14 +-- rom4x/B0_C763_switcher.s | 6 +- rom4x/B0_FAB4_patch_pwrup.s | 7 +- rom4x/B0_FAC8_patch_reset.s | 7 +- rom4x/B1_C763_switcher.s | 6 +- rom4x/B1_E000_rom4x.s | 109 +++++++++--------- rom4x/B1_E300_new_bootfail.s | 10 +- rom4x/Rakefile | 24 ++-- rom5x/B0_CFF9_switch_cmd.s | 6 +- rom5x/B0_FAB4_patch_pwrup.s | 6 +- rom5x/B0_FAC8_patch_reset.s | 6 +- rom5x/B0_FB68_center_title.s | 2 +- rom5x/B0_FBDF_bell1_hijack.s | 4 +- rom5x/B1_C53D_patch_out_rom_cksum.s | 4 +- rom5x/B1_D516_boot5x.s | 49 ++++---- rom5x/B1_D6CE_rom5x_misc.s | 51 ++++---- rom5x/B1_DB63_reset5x.s | 19 +-- rom5x/B1_FB3C_rom5x_dispatch.s | 7 +- rom5x/B1_FBE2_bell1_hijack_b1.s | 6 +- rom5x/Rakefile | 17 ++- .../accel_reverse/B1_FDD5_accel_reverse.s | 4 +- 23 files changed, 195 insertions(+), 174 deletions(-) diff --git a/.gitignore b/.gitignore index 9e69fdd..de2e1f0 100644 --- a/.gitignore +++ b/.gitignore @@ -3,5 +3,8 @@ *.bin *.swp *.zip +*.o +*.lst +*.b copyrom.sh diff --git a/README.md b/README.md index 64655f3..3e3f8da 100644 --- a/README.md +++ b/README.md @@ -125,7 +125,7 @@ It may work with other ROM dumps, it will *not* work with any other ROM version, Place the ROM dump in the directory with the other files and name it `iic_rom4.bin` for ROM 4X and `iic+_rom5.bin` for ROM 5X. -Now you will need a 65C02 cross assembler. The code was developed using [xa](http://www.floodgap.com/retrotech/xa/), mainly because it was available as a prebuilt binary in my preferred Linux distro's package repositories and supported the 65C02 opcodes. +Now you will need a 65C02 cross assembler. The current codebase is developed using ca65 from the [cc65](http://www.cc65.org/) project. (Note: The code was developed originally using [xa](http://www.floodgap.com/retrotech/xa/)). Finally you will need [Ruby](https://www.ruby-lang.org/en/) and [Rake](https://github.com/ruby/rake). diff --git a/rom4x/B0_C552_patch_bootfail.s b/rom4x/B0_C552_patch_bootfail.s index 5b63898..4c9b504 100644 --- a/rom4x/B0_C552_patch_bootfail.s +++ b/rom4x/B0_C552_patch_bootfail.s @@ -1,14 +1,14 @@ -#include "iic.defs" - -.text -* = $c552 +.psc02 +.code +.include "iic.defs" + .org $c552 jsr setnorm jsr init bra cbtfail - .dsb coma-*,$ea + .res coma-*,$ea bra coma ; Make sure coma routine exists - .db 0 ; rom4x present -cbtfail jsr setvid + .byte 0 ; rom4x present +cbtfail: jsr setvid jsr setkbd lda #>(nbtfail-1) pha diff --git a/rom4x/B0_C763_switcher.s b/rom4x/B0_C763_switcher.s index fc61f20..f821047 100644 --- a/rom4x/B0_C763_switcher.s +++ b/rom4x/B0_C763_switcher.s @@ -1,6 +1,6 @@ -#include "iic.defs" -.text -* = gorst4x +.code +.include "iic.defs" + .org gorst4x sta rombank ; gorst4x jmp rst4xrtn ; in other bank jmp reset4x sta rombank ; gobt4x diff --git a/rom4x/B0_FAB4_patch_pwrup.s b/rom4x/B0_FAB4_patch_pwrup.s index 3b76299..0e7c852 100644 --- a/rom4x/B0_FAB4_patch_pwrup.s +++ b/rom4x/B0_FAB4_patch_pwrup.s @@ -1,7 +1,6 @@ ; patch PWRUP to call boot4x - -#include "iic.defs" -.text -* = $fab4 +.code +.include "iic.defs" + .org $fab4 nop jmp gobt4x diff --git a/rom4x/B0_FAC8_patch_reset.s b/rom4x/B0_FAC8_patch_reset.s index 3bfd4cf..ce27568 100644 --- a/rom4x/B0_FAC8_patch_reset.s +++ b/rom4x/B0_FAC8_patch_reset.s @@ -1,7 +1,6 @@ ; patch RESET.X to call reset4x - -#include "iic.defs" -.text -* = $fac8 +.code +.include "iic.defs" + .org $fac8 jmp gorst4x diff --git a/rom4x/B1_C763_switcher.s b/rom4x/B1_C763_switcher.s index 149ecee..93b8d43 100644 --- a/rom4x/B1_C763_switcher.s +++ b/rom4x/B1_C763_switcher.s @@ -1,6 +1,6 @@ -#include "iic.defs" -.text -* = gorst4x +.code +.include "iic.defs" + .org gorst4x sta rombank ; gorst4x jmp reset4x ; in other bank jmp rstxrtn sta rombank ; gobt4x diff --git a/rom4x/B1_E000_rom4x.s b/rom4x/B1_E000_rom4x.s index 7e4daa7..7bac439 100644 --- a/rom4x/B1_E000_rom4x.s +++ b/rom4x/B1_E000_rom4x.s @@ -1,15 +1,16 @@ -#include "iic.defs" -.text -* = reset4x +.psc02 +.code +.include "iic.defs" + .org reset4x stz power2 + rx_mslot ; action = normal boot asl butn1 ; closed apple bcs ckdiag -exitrst jmp gorst4x ; return to RESET.X +exitrst: jmp gorst4x ; return to RESET.X ; check to see if both apples are down -ckdiag bit butn0 ; open apple +ckdiag: bit butn0 ; open apple bmi exitrst ; return to RESET.X ; present menu because only closed apple is down -menu4x jsr gobanner ; "Apple //c" +menu4x: jsr gobanner ; "Apple //c" ldx #$00 ; menu start jsr disp ; show it jsr gtkey @@ -22,13 +23,13 @@ menu4x jsr gobanner ; "Apple //c" lda #<(monitor-1) pha jmp swrts2 ; rts to enter monitor -ckkey1 cmp #$b2 ; "2" +ckkey1: cmp #$b2 ; "2" beq doconf cmp #$b4 ; "4" bne ckkey2 -doconf jsr confirm +doconf: jsr confirm bne menu4x ; go back to menu4x -ckkey2 sec +ckkey2: sec sbc #$b0 ; ascii->number bmi menu4x ; < 0 not valid cmp #$08 @@ -37,35 +38,35 @@ ckkey2 sec stz softev + 1 ; deinit coldstart stz pwerdup ; ditto bra exitrst -gtkey lda #$60 +gtkey: lda #$60 sta ($0),y ; cursor sta kbdstrb ; clr keyboard -kbdin lda kbd ; get key +kbdin: lda kbd ; get key bpl kbdin sta kbdstrb ; clear keyboard sta ($0),y ; put it on screen rts ; display message, input x = message start relative to msg1 -disp stz $0 ; load some safe defaults +disp: stz $0 ; load some safe defaults lda #$04 sta $1 ldy #$0 ; needs to be zero -disp0 lda msg1,x ; get message byte +disp0: lda msg1,x ; get message byte bne disp1 ; proceed if nonzero rts ; exit if 0 -disp1 inx ; next byte either way +disp1: inx ; next byte either way cmp #$20 ; ' ' bcc disp2 ; start of ptr if < 20 eor #$80 ; invert high bit sta ($0),y ; write to mem inc $0 ; inc address low byte bra disp0 ; back to the beginning -disp2 sta $1 ; write address high +disp2: sta $1 ; write address high lda msg1,x ; get it sta $0 ; write address low inx ; set next msg byte bra disp0 ; back to the beginning -confirm pha +confirm: pha ldx #(msg3-msg1) ; ask confirm jsr disp jsr gtkey @@ -82,20 +83,20 @@ confirm pha ; else are characters to display and will have their ; upper bit inverted before being written to the screen. msg1 = * - .db $05,$06,"0 Monitor" - .db $05,$86,"1 Reboot" - .db $06,$06,"2 Zero RAM Card and Reboot" - .db $06,$86,"3 Diagnostics" - .db $07,$06,"4 RAM Card Diagnostics" - .db $07,$86,"5 Boot SmartPort" - .db $04,$2e,"6 Boot Int. 5.25" - .db $04,$ae,"7 Boot Ext. 5.25" - .db $07,$5f,"By M.G." -msg2 .db $07,$db,"ROM 4X 01/01/17" - .db $05,$ae,$00 ; cursor pos in menu -msg3 .db $05,$b0,"SURE? ",$00 - .dsb boot4x - *, 0 -* = boot4x + .byte $05,$06,"0 Monitor" + .byte $05,$86,"1 Reboot" + .byte $06,$06,"2 Zero RAM Card and Reboot" + .byte $06,$86,"3 Diagnostics" + .byte $07,$06,"4 RAM Card Diagnostics" + .byte $07,$86,"5 Boot SmartPort" + .byte $04,$2e,"6 Boot Int. 5.25" + .byte $04,$ae,"7 Boot Ext. 5.25" + .byte $07,$5f,"By M.G." +msg2: .byte $07,$db,"ROM 4X 01/01/17" + .byte $05,$ae,$00 ; cursor pos in menu +msg3: .byte $05,$b0,"SURE? ",$00 + .res boot4x - *, 0 + .org boot4x jsr gobanner ; "Apple //c" jsr rdrecov ; try to recover ramdisk lda power2 + rx_mslot ; get action saved by reset4x @@ -103,14 +104,14 @@ msg3 .db $05,$b0,"SURE? ",$00 ldx #(msg2-msg1) ; short banner offset jsr disp ; display it lda power2 + rx_mslot ; boot selection -btc2 cmp #$02 ; clear ramcard +btc2: cmp #$02 ; clear ramcard bne btc3 jsr rdclear ; do clear bra boot4 -btc3 cmp #$03 ; Diags +btc3: cmp #$03 ; Diags bne btc4 jmp $c7c4 -btc4 cmp #$04 ; RX diags +btc4: cmp #$04 ; RX diags bne btc5 ldx #$ff txs ; reset stack @@ -124,33 +125,33 @@ btc4 cmp #$04 ; RX diags lda numbanks,y ; get the card size in banks bne dordiag ; do diag if memory present jmp swrts2 ; otherwise jump to monitor -dordiag jmp $db3a ; diags +dordiag: jmp $db3a ; diags ;bra boot4 -btc5 cmp #$05 ; boot smartport +btc5: cmp #$05 ; boot smartport beq boot5 -btc6 cmp #$06 ; boot int drive +btc6: cmp #$06 ; boot int drive beq boot6 -btc7 cmp #$07 ; boot ext drive +btc7: cmp #$07 ; boot ext drive bne boot4 ; none of the above ; copy small routine to $800 to boot ; external 5.25 ldy #(bt4xend-bootext+1) -btc7lp lda bootext,y +btc7lp: lda bootext,y sta $800,y dey bpl btc7lp lda #$08 ; copy done bra bootsl -boot4 lda #rx_mslot ; boot slot 4 +boot4: lda #rx_mslot ; boot slot 4 bra bootsl -boot5 lda #$c5 ; boot slot 5 +boot5: lda #$c5 ; boot slot 5 bra bootsl -boot6 lda #$c6 ; boot slot 6 -bootsl ldx #$00 ; low byte of slot -bootadr stx $0 ; store address +boot6: lda #$c6 ; boot slot 6 +bootsl: ldx #$00 ; low byte of slot +bootadr: stx $0 ; store address sta $1 ; return to bank 0 does jmp (0) -endbt4x jmp gobt4x ; continue boot -rdrecov jsr rdinit ; init ramcard +endbt4x: jmp gobt4x ; continue boot +rdrecov: jsr rdinit ; init ramcard lda pwrup,y ; get power up flag cmp #pwrbyte ; already initialized? beq recovdn ; exit if initialized @@ -169,11 +170,11 @@ rdrecov jsr rdinit ; init ramcard beq recovdn ; not bootable lda #pwrbyte sta pwrup,y ; set power byte - lda #"R" ; tell user + lda #'R' ; tell user sta $7d0 ; on screen -recovdn rts +recovdn: rts ; zero ram card space -rdclear jsr rdinit ; init ramcard +rdclear: jsr rdinit ; init ramcard jsr testsize ; get size lda numbanks,y ; # of 64Ks to write beq clrdone ; no memory @@ -182,10 +183,10 @@ rdclear jsr rdinit ; init ramcard stz addrl,x ; slinky address 0 stz addrm,x stz addrh,x -clbnklp inc $400 ; poor mans progress meter +clbnklp: inc $400 ; poor mans progress meter ldy #$00 -cl64klp ldx #$00 ; loop for all pages in bank -cl256lp txa ; loop for all bytes in page +cl64klp: ldx #$00 ; loop for all pages in bank +cl256lp: txa ; loop for all bytes in page ldx #rx_devno stz data,x ; write a zero to card tax @@ -196,17 +197,17 @@ cl256lp txa ; loop for all bytes in page ldx #rx_mslot dec numbanks,x bne clbnklp ; if more banks -clrdone ldx #rx_mslot +clrdone: ldx #rx_mslot stz pwrup,x ; zero powerup byte lda #$a0 ; ' ' sta $400 ; clear progress rts -rdinit bit rx_mslot*$100 ; activate registers +rdinit: bit rx_mslot*$100 ; activate registers ldy #rx_mslot ; slot offset ldx #rx_devno ; register offset rts ; next is snippet of code to boot external 5.25 -bootext lda #$e0 +bootext: lda #$e0 ldy #$01 ldx #$60 jmp $c60b diff --git a/rom4x/B1_E300_new_bootfail.s b/rom4x/B1_E300_new_bootfail.s index a10bed2..34e6316 100644 --- a/rom4x/B1_E300_new_bootfail.s +++ b/rom4x/B1_E300_new_bootfail.s @@ -1,8 +1,8 @@ -#include "iic.defs" -.text -* = nbtfail +.code +.include "iic.defs" + .org nbtfail ldx #msglen -lp1 lda bootmsg,x +lp1: lda bootmsg,x ora #$80 sta $7d0+19-msglen/2,x dex @@ -14,6 +14,6 @@ lp1 lda bootmsg,x lda #<(basic-1) pha jmp swrts2 -bootmsg .db "No bootable device." +bootmsg: .byte "No bootable device." msglen = * - bootmsg - 1 diff --git a/rom4x/Rakefile b/rom4x/Rakefile index 192e076..241e416 100644 --- a/rom4x/Rakefile +++ b/rom4x/Rakefile @@ -12,33 +12,43 @@ end desc "Clean object files" task :clean do sh "rm -f #{dest_rom}" - sh "rm -f *.o65" - sh "rm -f *.o65.lbl" + sh "rm -f sf512_#{dest_rom}" + sh "rm -f *.o" + sh "rm -f *.lst" + sh "rm -f *.b" end desc "Assemble all source files" -task :assemble => source_files.ext('.o65') +task :assemble => source_files.ext('.b') -rule ".o65" => ".s" do |t| - sh "xa -c -o #{t.name} -l #{t.name}.lbl #{t.source}" +rule ".o" => ".s" do |t| + sh "ca65 -l #{t.name}.lst #{t.source}" +end + +rule ".b" => ".o" do |t| + sh "ld65 -t none -o #{t.name} #{t.source}" end desc "Build ROM" task :build_rom => [:assemble] do puts "Building ROM image..." - obj_files = Rake::FileList.new('*.o65') + obj_files = Rake::FileList.new('*.b') rom = File.read(source_rom) obj_files.each do |t| if t =~ /B(\h)_(\h{4})/ bnum = $1.to_i(16) badd = $2.to_i(16) addr = bnum * 16384 + badd - rom_base - puts "Loading #{t} into bank #{bnum} @ #{badd.to_s(16)}, file addr #{addr.to_s(16)}" fc = File.read(t) + fl = fc.bytes.count + puts "Loading #{t} into bank #{bnum} @ #{badd.to_s(16)}, file addr $#{addr.to_s(16)}, len $#{fl.to_s(16)} (#{fl})" + nzc = 0 fc.each_byte do |b| + nzc += 1 if rom.getbyte(addr) != 0 && rom.getbyte(addr) != b rom.setbyte(addr, b) addr += 1 end + puts "\tNote: patched pver #{nzc} nonzero bytes!" if nzc > 0 else puts "I dont know where to load #{t}" end diff --git a/rom5x/B0_CFF9_switch_cmd.s b/rom5x/B0_CFF9_switch_cmd.s index 62bfa5d..ad43e16 100644 --- a/rom5x/B0_CFF9_switch_cmd.s +++ b/rom5x/B0_CFF9_switch_cmd.s @@ -5,9 +5,9 @@ ; load the command $EA and proceed the same way. ; thus we get two dispatch codes in 6 bytes. -#include "iic+.defs" -.text -* = $cff9 ; 7 bytes available here, but don't count on $CFFF +.include "iic+.defs" +.code + .org $cff9 ; 7 bytes available here, but don't count on $CFFF lda #$a9 ; lda opcode nop ; jmp/jsr $cffa does lda #$ea jmp $fbdf ; jump to bell1 hijack diff --git a/rom5x/B0_FAB4_patch_pwrup.s b/rom5x/B0_FAB4_patch_pwrup.s index 428fa8f..80a8ca8 100644 --- a/rom5x/B0_FAB4_patch_pwrup.s +++ b/rom5x/B0_FAB4_patch_pwrup.s @@ -1,7 +1,7 @@ ; patch PWRUP to call boot5x -#include "iic+.defs" -.text -* = $fab4 +.include "iic+.defs" +.code + .org $fab4 nop jmp gobt5x diff --git a/rom5x/B0_FAC8_patch_reset.s b/rom5x/B0_FAC8_patch_reset.s index cbb9912..6cc7e44 100644 --- a/rom5x/B0_FAC8_patch_reset.s +++ b/rom5x/B0_FAC8_patch_reset.s @@ -1,7 +1,7 @@ ; patch RESET.X to call reset5x -#include "iic+.defs" -.text -* = $fac8 +.include "iic+.defs" +.code + .org $fac8 jmp gorst5x diff --git a/rom5x/B0_FB68_center_title.s b/rom5x/B0_FB68_center_title.s index c3f59f3..04bf8e9 100644 --- a/rom5x/B0_FB68_center_title.s +++ b/rom5x/B0_FB68_center_title.s @@ -3,6 +3,6 @@ ; then displayed it two characters to the *right* rather than one ; or to to the left. It's a major ; pet peeve of mine, more so than the beep. -.text +.code sta $040d,y diff --git a/rom5x/B0_FBDF_bell1_hijack.s b/rom5x/B0_FBDF_bell1_hijack.s index 853b4d7..2db5a33 100644 --- a/rom5x/B0_FBDF_bell1_hijack.s +++ b/rom5x/B0_FBDF_bell1_hijack.s @@ -15,7 +15,7 @@ ; Obviously, $40 should beep the speaker, anything ; else can do whatever we want. -.text -* = $fbdf +.code + .org $fbdf sta $c028 diff --git a/rom5x/B1_C53D_patch_out_rom_cksum.s b/rom5x/B1_C53D_patch_out_rom_cksum.s index ed7be8c..e2f8557 100644 --- a/rom5x/B1_C53D_patch_out_rom_cksum.s +++ b/rom5x/B1_C53D_patch_out_rom_cksum.s @@ -5,8 +5,8 @@ ; calculates the checksum. It returns with carry set = error and ; carry clear = OK. So we just patch the JSR to always clear the ; carry. For now. -* = $C53D -.text +.code + .org $C53D nop nop clc diff --git a/rom5x/B1_D516_boot5x.s b/rom5x/B1_D516_boot5x.s index 1f25091..49a1de3 100644 --- a/rom5x/B1_D516_boot5x.s +++ b/rom5x/B1_D516_boot5x.s @@ -1,20 +1,21 @@ -#include "iic+.defs" -.text -* = boot5x ; 234 bytes available, code assembles to 231 +.code +.psc02 +.include "iic+.defs" + .org boot5x ; 234 bytes available, code assembles to 231 jsr titl5x ; "Apple IIc +" jsr rdrecov ; try to recover ramdisk lda power2 + rx_mslot ; get action saved by reset5x beq boot4 ; if zero, continue boot jsr bann5x ; display ROM 5X footer lda power2 + rx_mslot ; boot selection -btc2 cmp #$02 ; clear ramcard +btc2: cmp #$02 ; clear ramcard bne btc3 jsr rdclear ; do clear bra boot4 -btc3 cmp #$03 ; Diags +btc3: cmp #$03 ; Diags bne btc4 jmp $c7c4 -btc4 cmp #$04 ; RX diags +btc4: cmp #$04 ; RX diags bne btc5 ldx #$ff txs ; reset stack @@ -28,25 +29,25 @@ btc4 cmp #$04 ; RX diags lda numbanks,y ; get the card size in banks bne dordiag ; do diag if memory present jmp swrts2 ; otherwise jump to monitor -dordiag jmp $db3a ; diags -btc5 cmp #$05 ; boot smartport +dordiag: jmp $db3a ; diags +btc5: cmp #$05 ; boot smartport beq boot5 ; fall through if none of the above -boot4 lda #rx_mslot ; boot slot 4 +boot4: lda #rx_mslot ; boot slot 4 bra bootsl -boot5 lda #$c5 ; boot slot 5 +boot5: lda #$c5 ; boot slot 5 bra bootsl -boot6 lda #$c6 ; boot slot 6 -bootsl ldx #$00 ; low byte of slot -bootadr stx $0 ; store address +boot6: lda #$c6 ; boot slot 6 +bootsl: ldx #$00 ; low byte of slot +bootadr: stx $0 ; store address sta $1 ; return to bank 0 does jmp (0) -endbt4x lda #>(bt5xrtn-1) +endbt4x: lda #>(bt5xrtn-1) pha lda #<(bt5xrtn-1) pha lda $1 jmp swrts2 -rdrecov jsr rdinit ; init ramcard +rdrecov: jsr rdinit ; init ramcard lda pwrup,y ; get power up flag cmp #pwrbyte ; already initialized? beq recovdn ; exit if initialized @@ -65,11 +66,11 @@ rdrecov jsr rdinit ; init ramcard beq recovdn ; not bootable lda #pwrbyte sta pwrup,y ; set power byte - lda #"R" ; tell user + lda #'R' ; tell user sta $7d0 ; on screen -recovdn rts +recovdn: rts ; zero ram card space -rdclear jsr rdinit ; init ramcard +rdclear: jsr rdinit ; init ramcard jsr testsize ; get size lda numbanks,y ; # of 64Ks to write beq clrdone ; no memory @@ -78,10 +79,10 @@ rdclear jsr rdinit ; init ramcard stz addrl,x ; slinky address 0 stz addrm,x stz addrh,x -clbnklp inc $400 ; poor mans progress meter +clbnklp: inc $400 ; poor mans progress meter ldy #$00 -cl64klp ldx #$00 ; loop for all pages in bank -cl256lp txa ; loop for all bytes in page +cl64klp: ldx #$00 ; loop for all pages in bank +cl256lp: txa ; loop for all bytes in page ldx #rx_devno stz data,x ; write a zero to card tax @@ -92,17 +93,17 @@ cl256lp txa ; loop for all bytes in page ldx #rx_mslot dec numbanks,x bne clbnklp ; if more banks -clrdone ldx #rx_mslot +clrdone: ldx #rx_mslot stz pwrup,x ; zero powerup byte lda #$a0 ; ' ' sta $400 ; clear progress rts -rdinit bit rx_mslot*$100 ; activate registers +rdinit: bit rx_mslot*$100 ; activate registers ldy #rx_mslot ; slot offset ldx #rx_devno ; register offset rts ; next is snippet of code to boot external 5.25 -bootext lda #$e0 +bootext: lda #$e0 ldy #$01 ldx #$60 jmp $c60b diff --git a/rom5x/B1_D6CE_rom5x_misc.s b/rom5x/B1_D6CE_rom5x_misc.s index 17f6ec1..6f24940 100644 --- a/rom5x/B1_D6CE_rom5x_misc.s +++ b/rom5x/B1_D6CE_rom5x_misc.s @@ -1,44 +1,45 @@ -#include "iic+.defs" -.text -* = misc5x ; max 306 bytes +.code +.psc02 +.include "iic+.defs" + .org misc5x ; max 306 bytes bra domenu ; Display menu bra dobann ; Display banner (title + By MG) bra gtkey ; get a key bra confirm ; ask SURE? bra ntitle ; display "Apple IIc +" -dobann jsr ntitle +dobann: jsr ntitle ldx #(msg2-msg1) ; msg display entry point jmp disp -domenu jsr ntitle ; "Apple ||c +" +domenu: jsr ntitle ; "Apple ||c +" ldx #$00 ; menu start jsr disp ; show it rts -gtkey lda #$60 +gtkey: lda #$60 sta ($0),y ; cursor sta kbdstrb ; clr keyboard -kbdin lda kbd ; get key +kbdin: lda kbd ; get key bpl kbdin sta kbdstrb ; clear keyboard sta ($0),y ; put it on screen rts ; display message, input x = message start relative to msg1 -disp ldy #$0 ; needs to be zero -disp0 lda msg1,x ; get message byte +disp: ldy #$0 ; needs to be zero +disp0: lda msg1,x ; get message byte bne disp1 ; proceed if nonzero rts ; exit if 0 -disp1 inx ; next byte either way +disp1: inx ; next byte either way cmp #$20 ; ' ' bcc disp2 ; start of ptr if < 20 eor #$80 ; invert high bit sta ($0),y ; write to mem inc $0 ; inc address low byte bra disp0 ; back to the beginning -disp2 sta $1 ; write address high +disp2: sta $1 ; write address high lda msg1,x ; get it sta $0 ; write address low inx ; set next msg byte bra disp0 ; back to the beginning -confirm pha +confirm: pha ldx #(msg3-msg1) ; ask confirm jsr disp jsr gtkey @@ -55,7 +56,7 @@ confirm pha ; we then jump to swrts2 which switches banks and RTS to ; display "Apple IIc +", which then RTS to swrts, which ; switches banks back to here and RTS to our caller. -ntitle lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack +ntitle: lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack pha lda #<(swrts2-1) pha @@ -70,16 +71,16 @@ ntitle lda #>(swrts2-1) ; put return addr of swrts/swrts2 on stack ; else are characters to display and will have their ; upper bit inverted before being written to the screen. msg1 = * - .db $05,$06,"0 Monitor" - .db $05,$86,"1 Reboot" - .db $06,$06,"2 Zero RAM Card" - .db $06,$86,"3 Sys Diags" - .db $07,$06,"4 RAM Card Diags" - .db $07,$86,"5 Boot 3.5/SmartPort" - .db $04,$2e,"6 Boot 5.25" -; .db $04,$ae,"7 Accelerator" - .db $07,$5f,"By M.G." -msg2 .db $07,$db,"ROM 5X 02/10/17" - .db $05,$ae,$00 ; cursor pos in menu -msg3 .db $05,$b0,"SURE? ",$00 + .byte $05,$06,"0 Monitor" + .byte $05,$86,"1 Reboot" + .byte $06,$06,"2 Zero RAM Card" + .byte $06,$86,"3 Sys Diags" + .byte $07,$06,"4 RAM Card Diags" + .byte $07,$86,"5 Boot 3.5/SmartPort" + .byte $04,$2e,"6 Boot 5.25" +; .byte $04,$ae,"7 Accelerator" + .byte $07,$5f,"By M.G." +msg2: .byte $07,$db,"ROM 5X 02/10/17" + .byte $05,$ae,$00 ; cursor pos in menu +msg3: .byte $05,$b0,"SURE? ",$00 diff --git a/rom5x/B1_DB63_reset5x.s b/rom5x/B1_DB63_reset5x.s index a570a7d..4e7a4dd 100644 --- a/rom5x/B1_DB63_reset5x.s +++ b/rom5x/B1_DB63_reset5x.s @@ -1,6 +1,7 @@ -#include "iic+.defs" -.text -* = reset5x ; max 157 bytes +.code +.psc02 +.include "iic+.defs" + .org reset5x ; max 157 bytes stz power2 + rx_mslot ; action = normal reset lda #>(rst5xrtn-1) ; common case pha @@ -8,12 +9,12 @@ pha ; note that this stays on stack asl butn1 ; option (closed apple) bcs ckdiag -exitrst jmp swrts2 +exitrst: jmp swrts2 ; check to see if cmd_option (both apples) are down -ckdiag bit butn0 ; command (open apple) +ckdiag: bit butn0 ; command (open apple) bmi exitrst ; return to RESET.X ; present menu because only closed apple is down -menu jsr menu5x ; display menu +menu: jsr menu5x ; display menu jsr gkey5x cmp #$b0 ; "0" bne ckkey1 @@ -24,13 +25,13 @@ menu jsr menu5x ; display menu lda #<(monitor-1) pha jmp swrts2 ; rts to enter monitor -ckkey1 cmp #$b2 ; "2" +ckkey1: cmp #$b2 ; "2" beq doconf cmp #$b4 ; "4" bne ckkey2 -doconf jsr conf5x +doconf: jsr conf5x bne menu ; go back to menu4x -ckkey2 sec +ckkey2: sec sbc #$b0 ; ascii->number bmi menu ; < 0 not valid cmp #$07 ; we will use 7 for accelerator later diff --git a/rom5x/B1_FB3C_rom5x_dispatch.s b/rom5x/B1_FB3C_rom5x_dispatch.s index c25e0a7..03bdf97 100644 --- a/rom5x/B1_FB3C_rom5x_dispatch.s +++ b/rom5x/B1_FB3C_rom5x_dispatch.s @@ -1,6 +1,7 @@ -#include "iic+.defs" -.text -* = $fb3c ; ~165 bytes free here +.code +.psc02 +.include "iic+.defs" + .org $fb3c ; ~165 bytes free here cmp #$a9 ; reset patch bne chk2 jmp reset5x diff --git a/rom5x/B1_FBE2_bell1_hijack_b1.s b/rom5x/B1_FBE2_bell1_hijack_b1.s index 8fe7472..9df31dd 100644 --- a/rom5x/B1_FBE2_bell1_hijack_b1.s +++ b/rom5x/B1_FBE2_bell1_hijack_b1.s @@ -1,5 +1,5 @@ -#include "iic+.defs" -.text -* = $fbe2 ; ~29 bytes free here +.code +.include "iic+.defs" + .org $fbe2 ; ~29 bytes free here jmp $fb3c diff --git a/rom5x/Rakefile b/rom5x/Rakefile index 00148f1..66dcccd 100644 --- a/rom5x/Rakefile +++ b/rom5x/Rakefile @@ -13,21 +13,26 @@ desc "Clean object files" task :clean do sh "rm -f #{dest_rom}" sh "rm -f sf512_#{dest_rom}" - sh "rm -f *.o65" - sh "rm -f *.o65.lbl" + sh "rm -f *.o" + sh "rm -f *.lst" + sh "rm -f *.b" end desc "Assemble all source files" -task :assemble => source_files.ext('.o65') +task :assemble => source_files.ext('.b') -rule ".o65" => ".s" do |t| - sh "xa -c -o #{t.name} -l #{t.name}.lbl #{t.source}" +rule ".o" => ".s" do |t| + sh "ca65 -l #{t.name}.lst #{t.source}" +end + +rule ".b" => ".o" do |t| + sh "ld65 -t none -o #{t.name} #{t.source}" end desc "Build ROM" task :build_rom => [:assemble] do puts "Building ROM image..." - obj_files = Rake::FileList.new('*.o65') + obj_files = Rake::FileList.new('*.b') rom = File.read(source_rom) obj_files.each do |t| if t =~ /B(\h)_(\h{4})/ diff --git a/rom5x/options/accel_reverse/B1_FDD5_accel_reverse.s b/rom5x/options/accel_reverse/B1_FDD5_accel_reverse.s index c346779..46eb0ac 100644 --- a/rom5x/options/accel_reverse/B1_FDD5_accel_reverse.s +++ b/rom5x/options/accel_reverse/B1_FDD5_accel_reverse.s @@ -5,7 +5,7 @@ ; This patch was inspired by Quinn Dunki's functionally equivalent ; firmware mod found here: http://quinndunki.com/blondihacks/?p=2546 -.text -* = $fdd5 +.code + .org $fdd5 .byte $f0 From 99d18d92c85748448756b252a33732a0af816278 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sat, 18 Mar 2017 23:34:25 -0700 Subject: [PATCH 2/8] initial integration of accelerator code --- notes/rom5_zeros.txt | 6 +- rom5x/B1_D3B5_accmenu.s | 7 + rom5x/B1_FB3C_rom5x_dispatch.s | 4 + rom5x/B1_FCC9_spdtab.s | 5 + rom5x/B1_FD00_accel5x.s | 560 +++++++++++++++++++++++++++++++++ rom5x/accelmenu.h | 8 + rom5x/iic+.defs | 8 + rom5x/spdtab.h | 21 ++ 8 files changed, 616 insertions(+), 3 deletions(-) create mode 100644 rom5x/B1_D3B5_accmenu.s create mode 100644 rom5x/B1_FCC9_spdtab.s create mode 100644 rom5x/B1_FD00_accel5x.s create mode 100644 rom5x/accelmenu.h create mode 100644 rom5x/spdtab.h diff --git a/notes/rom5_zeros.txt b/notes/rom5_zeros.txt index 6db3743..1574b1d 100644 --- a/notes/rom5_zeros.txt +++ b/notes/rom5_zeros.txt @@ -13,7 +13,7 @@ C572 - 8 bytes C7FB - 8 bytes C7FC - 7 bytes CE00 - 512 bytes not usable (MIG space) -D134 - 76 bytes +D3B5 - 75 bytes - Accelerator menu text D516 - 234 bytes - ROM 5X boot D6CE - 306 bytes - ROM 5X misc routines DB63 - 157 bytes - ROM 5X reset @@ -23,9 +23,9 @@ F7ED - 19 bytes FB3C - 196 bytes - FBE2 ROM 5X dispatch - Future: classic beep FC3C - 12 bytes -FCC9 - 55 bytes +FCC9 - 55 bytes - Accelerator speeds table FE96 - 352 bytes - but reserve 65816 vectors - - Future ROM 5X accelerator enhancements + - Accelerator enhancements Other potential usable space: Aux Bank diff --git a/rom5x/B1_D3B5_accmenu.s b/rom5x/B1_D3B5_accmenu.s new file mode 100644 index 0000000..57d9826 --- /dev/null +++ b/rom5x/B1_D3B5_accmenu.s @@ -0,0 +1,7 @@ +.code +.include "iic+.defs" +.org $d3b5 +.proc ACCMENU +.include "accelmenu.h" +.endproc + diff --git a/rom5x/B1_FB3C_rom5x_dispatch.s b/rom5x/B1_FB3C_rom5x_dispatch.s index 03bdf97..5d98c66 100644 --- a/rom5x/B1_FB3C_rom5x_dispatch.s +++ b/rom5x/B1_FB3C_rom5x_dispatch.s @@ -8,6 +8,9 @@ chk2: cmp #$ea ; boot patch bne chk3 jmp boot5x +.if newbeep +chk3: +.else chk3: cmp #$40 ; beep bne dowait ; "classic air raid beep" @@ -20,6 +23,7 @@ obell2: lda #$0c dey bne obell2 bra dexit ; back to caller +.endif dowait: jsr $fcb5 ; do delay if anything else lda #>($fbe2-1) ; return to other bank here (in BELL1) pha ; by pushing address onto diff --git a/rom5x/B1_FCC9_spdtab.s b/rom5x/B1_FCC9_spdtab.s new file mode 100644 index 0000000..900c3f9 --- /dev/null +++ b/rom5x/B1_FCC9_spdtab.s @@ -0,0 +1,5 @@ +.code +.include "iic+.defs" +.org $fcc9 +.include "spdtab.h" + diff --git a/rom5x/B1_FD00_accel5x.s b/rom5x/B1_FD00_accel5x.s new file mode 100644 index 0000000..fbd9be4 --- /dev/null +++ b/rom5x/B1_FD00_accel5x.s @@ -0,0 +1,560 @@ +; Improved Apple IIc Plus accelerator firmware +; by M.G. + +; Improvements over apple-supplied code: +; * bugs fixed +; * reset+ toggles acclerator on/off rather than setting slow +; * warm reset preserves configured settings +; * additional commands to read/write accelerator speed +; * reset+ configuration menu +; Config menu can be called independently from other alt +; bank firmware, such as ROM 5X + +; note that in the current state, the code cannot be inserted +; into the ROM without moving the menu text and the speeds +; table. + +TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II emulator at $2000 + ; this disables the bank switch and uses the main RAM at $0E00 to simulate the + ; MIG RAM. +XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands +ACCMENU = 1 ; set to 1 to enable accelerator menu + + .psc02 +.if TESTBLD + ; test build of accel code +.else + .include "iic+.defs" +.endif +; zero page +ZPAGE = $00 +COUNTER = ZPAGE+0 ; used as a generic counter for loops +CALLSP = ZPAGE+1 ; stack pointer at call time +COMMAND = ZPAGE+2 ; command to execute +UBFPTRL = ZPAGE+3 ; user buffer pointer - low byte +UBFPTRH = ZPAGE+4 ; ditto - high byte +EXITCOD = ZPAGE+5 ; exit code from command + +; stack +STACK = $0100 + +; I/O +IOPAGE = $C000 +KBD = IOPAGE+$00 +KBDSTR = IOPAGE+$10 +ZIP5A = IOPAGE+$5A +ZIP5B = IOPAGE+$5B +ZIP5C = IOPAGE+$5C +ZIP5D = IOPAGE+$5D +ZIP5E = IOPAGE+$5E +ZIP5F = IOPAGE+$5F + +; MIG +.if ::TESTBLD +MIGBASE = $0E00 +.else +MIGBASE = $CE00 +.endif +MIGRAM = MIGBASE +PWRUPB0 = MIGRAM+0 ; powerup byte +PWRUPB1 = MIGRAM+1 ; powerup byte +ACWL = MIGRAM+2 ; accelerator control word - low, also ZIP $C05C reg +ACWH = MIGRAM+3 ; accelerator control word - high +KBDSAVE = MIGRAM+4 ; saved keystroke +ZIP5CSV = MIGRAM+5 ; configured $C05C register +ZIP5DSV = MIGRAM+6 ; configured $C05D register +ZIP5ESV = MIGRAM+7 ; configured $C05E register +ZIP5FSV = MIGRAM+8 ; configured $C05F register +ZPSAVE = MIGRAM+$10 ; 8 zero page values saved here +MIGPAG0 = MIGBASE+$A0 ; MIG set page 0 +MIGPAGI = MIGBASE+$20 ; MIG increment page + +; fixed values +PWRUPV0 = $33 +PWRUPV1 = $55 +ESCKEY = $9B +TABKEY = $89 + +; routines we use +WAIT = $FCA8 +AUXWAIT = $FCB5 +NORMAL = $FC27 +SWRTS2 = $C784 + +.if ::TESTBLD + .org $2000 + lda #$00 + pha + jsr ACCEL + rts +.else + .org $FD00 +.endif +.proc ACCEL + php + sei + phy + phx + bit MIGPAG0 + bit MIGPAGI + bit MIGPAGI + ; save used ZP locations + ldx #$07 +@loop: lda ZPAGE,x + sta ZPSAVE,x + stz ZPAGE,x + dex + bpl @loop + ; get command & any parameters + tsx + txa + tay + iny + lda STACK+6,x + sta COMMAND + cmp #$05 ; read accelerator - first command with pointer parameter + stx CALLSP + bcc noparm ; no parameter command + lda STACK+7,x + sta UBFPTRL + lda STACK+8,x + sta UBFPTRH + iny + iny + inx + inx +noparm: inx + txs + ldx CALLSP + lda #$05 + sta COUNTER +@loop: lda STACK+5,x + sta STACK+5,y + dex + dey + dec COUNTER + bne @loop + lda COMMAND +.if ::XTRACMD + cmp #$09 ; bad command number? +.else + cmp #$07 +.endif + bcc docmd ; no, do command + lda #$01 + sta EXITCOD + bra acceldn +docmd: asl a ; calculate jump table offset + tax + jsr dispcmd ; dispatch command +acceldn: + lda EXITCOD + pha + ; restore zero page contnets + ldx #$07 +@loop: lda ZPSAVE,x + sta ZPAGE,x + dex + bpl @loop ; fixed bug + pla + plx + ply + plp + clc + cmp #$00 + beq doexit + sec +doexit: +.if ::TESTBLD + rts +.else + jmp SWRTS2 +.endif +dispcmd: + jmp (cmdtable,x) +.endproc ; ACCEL +; Initialize Accelerator (undocumented) +.proc AINIT + ; give time for user to hit key + ldx #$03 +@loop: lda #$FF +.if ::TESTBLD + jsr WAIT +.else + jsr AUXWAIT +.endif + dex + bne @loop + ; now read keyboard + lda KBD + sta KBDSAVE + ; check powerup bytes + lda PWRUPB0 + cmp #PWRUPV0 + bne coldst + lda PWRUPB1 + cmp #PWRUPV1 + beq warmst +coldst: lda KBDSAVE + ora #$80 + sta KBDSAVE + jsr MIGINIT +warmst: ldx ACWL + ldy ACWH + lda KBDSAVE + cmp #ESCKEY + bne doinit + ; toggle accelerator speed + tya + eor #$08 ; toggle bit 4 + tay +doinit: jsr AUNLK ; unlock registers + jsr ACOND ; set enabled according to y reg + jsr ASETR ; set registers + jsr ALOCK ; lock accelerator + ; set powerup bytes + lda #PWRUPV0 + sta PWRUPB0 + lda #PWRUPV1 + sta PWRUPB1 +.if ::ACCMENU + ; now handle keyboard for menu + lda KBDSAVE + cmp #TABKEY + bne initdn + sta KBDSTR + jsr AMENU +.endif +initdn: lda ACWH + and #$08 + beq exinit ; 0 if accel enabled +.if ::TESTBLD + lda #$4e + sta $0500 + sta KBDSTR +.else + jmp NORMAL +.endif +exinit: rts +.endproc ; AINIT +; initialize values in MIG RAM +.proc MIGINIT + ldx #$03 +@loop: lda IREGV,x + sta ZIP5CSV,x + dex + bpl @loop + lda IACWL + sta ACWL + lda IACWH + sta ACWH + rts +.endproc ; MIGINIT +; conditionally enable accelerator according to bit 4 of Y register +.proc ACOND + tya + and #$08 + bne ADISA + ; otherwise fall through +.endproc ; ACOND +; enable accelerator +.proc AENAB + lda #$08 + sta ZIP5B + trb ACWH + rts +.endproc ; AENAB +; disable accelerator +.proc ADISA + lda #$08 + sta ZIP5A + tsb ACWH + rts +.endproc ; ADISA +; lock accelerator registers +.proc ALOCK + lda #$A5 + sta ZIP5A + lda #$10 + tsb ACWH + rts +.endproc ; ALOCK +; unlock accelerator registers +.proc AUNLK + lda #$5A + sta ZIP5A + sta ZIP5A + sta ZIP5A + sta ZIP5A + lda #$10 + trb ACWH + rts +.endproc ; AUNLK +; read accelerator +.proc AREAD + ldy #$00 + lda ACWL + sta (UBFPTRL),y + iny + lda ACWH + sta (UBFPTRL),y + rts +.endproc ; AREAD +; write accelerator +.proc AWRIT + lda #$40 + trb ACWH ; clear writable bits + ldy #$00 + lda (UBFPTRL),y + tax + iny + lda (UBFPTRL),y + and #$40 ; all other bits reserved + ora ACWH ; merge in existing ACWH less the bits we cleared above + tay + ;jsr AUNLK ; Apple code unlocks in write command, prob a bug. + jsr ASETR + ;jsr ALOCK + rts +.endproc ; AWRIT +; set accelerator registers +; x = new ACWL +; y = new ACWH +.proc ASETR +; php +; pha +; phx + stx ACWL + stx ZIP5CSV + sty ACWH + lda #$40 ; reset paddle speed + trb ZIP5FSV + tya + and #$40 ; mask paddle speed + ora ZIP5FSV ; merge with existing $c05f values + sta ZIP5FSV ; and put back + ; now set ZIP registers from MIG RAM + jsr ASETR1 +; plx +; pla +; plp + rts +.endproc ; ASETR1 +.proc ASETR1 + ldy ACWH + jsr ACOND + tya + and #$08 + beq setdn + ldx #$03 +@loop: lda ZIP5CSV,x + sta ZIP5C,x + dex + bpl @loop +setdn: rts +.endproc ; ASETR1 +cmdtable: + .word AINIT + .word AENAB + .word ADISA + .word ALOCK + .word AUNLK + .word AREAD + .word AWRIT +.if ::XTRACMD + .word ARSPD + .word AWSPD +; get the accelerator speed register +.proc ARSPD + ldy #$00 + lda ZIP5DSV + sta (UBFPTRL),y + rts +.endproc ; ARSPD +; write the accelerator speed register +.proc AWSPD + ldy #$00 + lda (UBFPTRL),y + sta ZIP5DSV + tay + jsr AUNLK + sty ZIP5D + jsr ALOCK + rts +.endproc ; AWSPD +.endif +IACWL: .byte %01100111 ; initial ACWL - same as $C05C +IACWH: .byte %00010000 ; initial ACWH - b6 = 1=paddle fast, b4 = reg 1=lock/0=unlock + ; b3 = 1=accel disable, rest reserved +IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay + .byte %00000000 ; Initial $C05D - $00 = 4MHz + .byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc + .byte %00000000 ; Initial $C05F - b7=0 enable L/C accel, b6=0 paddle sync +.if ::ACCMENU +; accelerator config menu +; ---------|---------|---------|---------| +; Accel: On Spk Dly: On +; Speed: 4.00 Pdl Dly: On +; +.proc AMENU + ; do this in case someone else calls us + bit MIGPAG0 + bit MIGPAGI + bit MIGPAGI + lda COUNTER + pha + lda UBFPTRH + pha + lda UBFPTRL + pha +amenu1: jsr disp ; disp menu with Accel Off + lda ACWH ; get ACWH + and #$08 ; check accelerator enabled + bne aminp ; if not, go to input + ldx #(msg2-msg1) ; rest of menu + jsr disp0 ; on screen + lda ZIP5CSV ; should be same as ACWL + and #$01 ; bit 1 = speaker delay, 1 = enable + bne dpdl ; Skip if enabled + lda #$e6 ; Change on to off in menu + sta $06c6 + sta $06c7 +dpdl: lda ZIP5FSV ; 5F register has paddle delay + and #$40 ; bit 6 = paddle delay (1 = defeat) + beq dspd ; 0 = on, skip + lda #$e6 ; change on to off in menu + sta $0746 + sta $0747 +dspd: lda ZIP5DSV ; Speed in 5D register + sta COUNTER ; if it is 4 MHz, this will stay 0 + tay + beq aminp ; get input since menu already says 4.00 + ldx #38 ; # of speeds(20) * 2 - 1 +@sloop: lda spdtab,x ; get speed table speed byte + tay + and #$fc ; mask off irrelevant bits we use for MHz + cmp ZIP5DSV ; see if matching + beq dspd1 ; if so, display it + dex ; otherwise, next entry + dex + bpl @sloop + ; fall through will say 0.00 MHz +dspd1: tya + stx COUNTER ; which speed option is selected + stx $0e1f ; DEBUG + and #$03 ; MHz value + ora #$b0 ; to digit + sta $072b ; ones + inx + lda spdtab,x + tay + lsr + lsr + lsr + lsr + ora #$b0 + sta $072d ; 10ths + tya + and #$0f + ora #$b0 + sta $072e ; 100ths +aminp: ldy #$00 + lda #$60 + sta (UBFPTRL),y +@kloop: lda KBD + bpl @kloop + bit KBDSTR +ckrtn: cmp #$8d ; return + beq exit + and #$df ; upper case +ckA: cmp #$c1 ; 'A' + bne ckrest + lda ACWH + eor #$08 + sta ACWH + bra tomenu +ckrest: tay + lda ACWH ; get ACWH + and #$08 ; check accelerator enabled + bne tomenu ; if not, do not allow changes + tya +ckrt: cmp #$95 ; right arrow + bne cklt + ldx COUNTER + dex + dex + bmi tomenu +setspd: lda spdtab,x + and #$fc + sta ZIP5DSV + bra tomenu +cklt: cmp #$88 ; left arrow + bne ckS + ldx COUNTER + inx + inx + cpx #35 ; should stop at 0.67 + bcc setspd + bra tomenu +ckS: cmp #$d3 ; 'S' + bne ckP + lda ZIP5CSV + eor #$01 + sta ZIP5CSV + sta ACWL + bra tomenu +ckP: cmp #$d0 ; 'P' + bne tomenu + lda ZIP5FSV + eor #$40 + sta ZIP5FSV + lda ACWH + eor #$40 + sta ACWH +tomenu: jmp amenu1 +exit: pla + sta UBFPTRL + pla + sta UBFPTRH + pla + sta COUNTER + jmp dclear +disp: jsr dclear + inx + ldy #$00 +disp0: lda msg1,x + bne disp1 + rts +disp1: inx + cmp #$20 ; ' ' + bcc disp2 + eor #$80 + sta (UBFPTRL),y + inc UBFPTRL + bra disp0 +disp2: sta UBFPTRH + lda msg1,x + sta UBFPTRL + inx + bra disp0 +dclear: lda #$a0 + ldx #$27 +@cloop: sta $0628,x ; line 12 + sta $06a8,x ; 13 + sta $0728,x ; 14 + sta $07a8,x ; 15 + dex + bpl @cloop + rts +.if ::TESTBLD +.include "accelmenu.h" +spdtab: +.include "spdtab.h" +.else +msg1 = ::amenu1 +msg2 = ::amenu2 +.endif +.endproc ; AMENU +; check for run into vector area +.assert * < $ffe0, error, "accel5x overran $ffe0" +.endif diff --git a/rom5x/accelmenu.h b/rom5x/accelmenu.h new file mode 100644 index 0000000..084423d --- /dev/null +++ b/rom5x/accelmenu.h @@ -0,0 +1,8 @@ +; acclerator menu text +msg1: .byte $06,$a8,$81,"ccel: Off" + .byte $06,$b3,$00 +msg2: .byte $06,$b0,"n " + .byte $06,$bc,$93,"pk Dly: On" + .byte $07,$28,$bc,$ad," 4.00 MHz ",$ad,$be + .byte $07,$3c,$90,"dl Dly: On" + .byte $07,$4f,$00 diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs index 632a882..fd46d0e 100644 --- a/rom5x/iic+.defs +++ b/rom5x/iic+.defs @@ -1,3 +1,6 @@ +; options +newbeep = 1 ; 1 = use IIc+ beep + ; hardware ;set80col = $c001 rombank = $c028 @@ -53,3 +56,8 @@ conf5x = gkey5x+2 titl5x = conf5x+2 banner = $fb60 +; accel5x locs +amenu1 = $d3b5 +amenu2 = amenu1 + $0f +spdtab = $fcc9 + diff --git a/rom5x/spdtab.h b/rom5x/spdtab.h new file mode 100644 index 0000000..966d64d --- /dev/null +++ b/rom5x/spdtab.h @@ -0,0 +1,21 @@ +; speed table for 4 MHz IIc Plus + .byte %00000000,$00 ; 4.0000 + .byte %00100011,$33 ; 3.3333 + .byte %00010011,$20 ; 3.2000 + .byte %00001011,$00 ; 3.0000 + .byte %00000110,$67 ; 2.6667 + .byte %01000010,$00 ; 2.0000 + .byte %01100001,$67 ; 1.6667 + .byte %01010001,$60 ; 1.6000 + .byte %01001001,$50 ; 1.5000 + .byte %11000001,$33 ; 1.3333 + .byte %11100001,$11 ; 1.1111 + .byte %11010001,$07 ; 1.0667 + .byte %10000001,$00 ; 1.0000 + .byte %11000100,$89 ; 0.8889 + .byte %10100000,$83 ; 0.8333 + .byte %10010000,$80 ; 0.8000 + .byte %10001000,$75 ; 0.7500 + .byte %10000100,$67 ; 0.6667 + .byte %01000101,$33 ; 1.3333 + .byte %11001001,$00 ; 1.0000 From 19527adc3b2cc0dfed09225f56796e90b0c750ab Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 19 Mar 2017 11:05:13 -0700 Subject: [PATCH 3/8] 5X: fix accelerator menu bugs after initial HW test --- rom5x/B1_D6CE_rom5x_misc.s | 2 +- rom5x/B1_DB63_reset5x.s | 6 +++++- rom5x/B1_FB3C_rom5x_dispatch.s | 3 ++- rom5x/B1_FD00_accel5x.s | 26 ++++++++++++++++++++------ rom5x/iic+.defs | 2 +- 5 files changed, 29 insertions(+), 10 deletions(-) diff --git a/rom5x/B1_D6CE_rom5x_misc.s b/rom5x/B1_D6CE_rom5x_misc.s index 6f24940..38b8337 100644 --- a/rom5x/B1_D6CE_rom5x_misc.s +++ b/rom5x/B1_D6CE_rom5x_misc.s @@ -78,7 +78,7 @@ msg1 = * .byte $07,$06,"4 RAM Card Diags" .byte $07,$86,"5 Boot 3.5/SmartPort" .byte $04,$2e,"6 Boot 5.25" -; .byte $04,$ae,"7 Accelerator" + .byte $04,$ae,"7 Accelerator" .byte $07,$5f,"By M.G." msg2: .byte $07,$db,"ROM 5X 02/10/17" .byte $05,$ae,$00 ; cursor pos in menu diff --git a/rom5x/B1_DB63_reset5x.s b/rom5x/B1_DB63_reset5x.s index 4e7a4dd..8d519a4 100644 --- a/rom5x/B1_DB63_reset5x.s +++ b/rom5x/B1_DB63_reset5x.s @@ -31,7 +31,11 @@ ckkey1: cmp #$b2 ; "2" bne ckkey2 doconf: jsr conf5x bne menu ; go back to menu4x -ckkey2: sec +ckkey2: cmp #$b7 ; "7" + bne ckkey3 + jsr $fd02 ; accelerator menu + bra menu +ckkey3: sec sbc #$b0 ; ascii->number bmi menu ; < 0 not valid cmp #$07 ; we will use 7 for accelerator later diff --git a/rom5x/B1_FB3C_rom5x_dispatch.s b/rom5x/B1_FB3C_rom5x_dispatch.s index 5d98c66..d83125d 100644 --- a/rom5x/B1_FB3C_rom5x_dispatch.s +++ b/rom5x/B1_FB3C_rom5x_dispatch.s @@ -15,7 +15,8 @@ chk3: cmp #$40 ; beep bne dowait ; "classic air raid beep" ; inspired by http://quinndunki.com/blondihacks/?p=2471 - jsr $fcb5 ; (new) WAIT for .1 sec delay + ; jsr $fcb5 ; (new) WAIT for .1 sec delay + jsr owait ldy #$c0 obell2: lda #$0c jsr owait ; old wait for correct sound diff --git a/rom5x/B1_FD00_accel5x.s b/rom5x/B1_FD00_accel5x.s index fbd9be4..d66ef8c 100644 --- a/rom5x/B1_FD00_accel5x.s +++ b/rom5x/B1_FD00_accel5x.s @@ -19,6 +19,7 @@ TESTBLD = 0 ; set to 1 to enable test code that runs in random ; MIG RAM. XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands ACCMENU = 1 ; set to 1 to enable accelerator menu +ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set) .psc02 .if TESTBLD @@ -91,7 +92,9 @@ SWRTS2 = $C784 .org $FD00 .endif .proc ACCEL - php + bra accel1 + jmp AMENU +accel1: php sei phy phx @@ -340,15 +343,19 @@ exinit: rts ; plp rts .endproc ; ASETR1 +; set accelerator registers from saved values in MIG .proc ASETR1 ldy ACWH - jsr ACOND + jsr ACOND ; conditionally enable accelerator tya - and #$08 - beq setdn - ldx #$03 + and #$08 ; is it disabled? + bne setdn ; if so, don't change other registers + ldx #$03 ; otherwise set all registers from MIG @loop: lda ZIP5CSV,x sta ZIP5C,x +.if ::ADEBUG + sta $300,x ; DEBUG +.endif dex bpl @loop setdn: rts @@ -397,10 +404,11 @@ IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot spee ; Speed: 4.00 Pdl Dly: On ; .proc AMENU - ; do this in case someone else calls us + ; do this in case someone else calls us outside of AINIT bit MIGPAG0 bit MIGPAGI bit MIGPAGI + ; save ZP locs we are using lda COUNTER pha lda UBFPTRH @@ -441,7 +449,9 @@ dspd: lda ZIP5DSV ; Speed in 5D register ; fall through will say 0.00 MHz dspd1: tya stx COUNTER ; which speed option is selected +.if ::TESTBLD stx $0e1f ; DEBUG +.endif and #$03 ; MHz value ora #$b0 ; to digit sta $072b ; ones @@ -512,12 +522,16 @@ ckP: cmp #$d0 ; 'P' eor #$40 sta ACWH tomenu: jmp amenu1 +; restore saved values and set accelerator exit: pla sta UBFPTRL pla sta UBFPTRH pla sta COUNTER + jsr AUNLK + jsr ASETR1 + jsr ALOCK jmp dclear disp: jsr dclear inx diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs index fd46d0e..9f1d84e 100644 --- a/rom5x/iic+.defs +++ b/rom5x/iic+.defs @@ -1,5 +1,5 @@ ; options -newbeep = 1 ; 1 = use IIc+ beep +newbeep = 0 ; 1 = use IIc+ beep ; hardware ;set80col = $c001 From 6a785d55887915a4960f6a52068bc79d9c510962 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 19 Mar 2017 16:17:51 -0700 Subject: [PATCH 4/8] confirmed speed table for 4 MHz using empirical evidence --- rom5x/spdtab.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/rom5x/spdtab.h b/rom5x/spdtab.h index 966d64d..c2292c9 100644 --- a/rom5x/spdtab.h +++ b/rom5x/spdtab.h @@ -11,11 +11,10 @@ .byte %11000001,$33 ; 1.3333 .byte %11100001,$11 ; 1.1111 .byte %11010001,$07 ; 1.0667 - .byte %10000001,$00 ; 1.0000 + .byte %11001001,$00 ; 1.0000 .byte %11000100,$89 ; 0.8889 .byte %10100000,$83 ; 0.8333 .byte %10010000,$80 ; 0.8000 .byte %10001000,$75 ; 0.7500 .byte %10000100,$67 ; 0.6667 - .byte %01000101,$33 ; 1.3333 - .byte %11001001,$00 ; 1.0000 + From 7da7a32cae68928d66c22722a45fa74b3a562bcd Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 19 Mar 2017 16:19:37 -0700 Subject: [PATCH 5/8] add note about speed table testing --- rom5x/spdtab.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/rom5x/spdtab.h b/rom5x/spdtab.h index c2292c9..5755275 100644 --- a/rom5x/spdtab.h +++ b/rom5x/spdtab.h @@ -1,4 +1,8 @@ ; speed table for 4 MHz IIc Plus +; this was confirmed by measuring a delay loop +; for each speed. The delay loop was timed +; timed to 1/100 sec accuracy using the Ram +; Express II+ dclock. .byte %00000000,$00 ; 4.0000 .byte %00100011,$33 ; 3.3333 .byte %00010011,$20 ; 3.2000 From 4cee44a2a43f7bae9e5d2cae1dab0132581f1c28 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Mon, 20 Mar 2017 11:40:11 -0700 Subject: [PATCH 6/8] 5X: optional percentage-based speed display for accelerator config --- .gitignore | 2 ++ rom5x/B1_FD00_accel5x.s | 29 +++++++++++++++++++++++------ rom5x/Rakefile | 14 ++++++++++++++ rom5x/accelmenu.h | 4 ++++ rom5x/iic+.defs | 2 ++ rom5x/spdtab.h | 25 +++++++++++++++++++++++-- 6 files changed, 68 insertions(+), 8 deletions(-) diff --git a/.gitignore b/.gitignore index de2e1f0..b823cc6 100644 --- a/.gitignore +++ b/.gitignore @@ -6,5 +6,7 @@ *.o *.lst *.b +*.po copyrom.sh +rom5x/accel5x diff --git a/rom5x/B1_FD00_accel5x.s b/rom5x/B1_FD00_accel5x.s index d66ef8c..48b2b56 100644 --- a/rom5x/B1_FD00_accel5x.s +++ b/rom5x/B1_FD00_accel5x.s @@ -14,9 +14,13 @@ ; into the ROM without moving the menu text and the speeds ; table. -TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II emulator at $2000 +.ifdef testaccel +TESTBLD = 1 +.else +TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II hw/emulator at $2000 ; this disables the bank switch and uses the main RAM at $0E00 to simulate the - ; MIG RAM. + ; MIG RAM. Will configure a Zip Chip as if it were the IIc+ Accelerator. +.endif XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands ACCMENU = 1 ; set to 1 to enable accelerator menu ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set) @@ -24,6 +28,7 @@ ADEBUG = 0 ; turn on debugging (copies registers to $300 when .psc02 .if TESTBLD ; test build of accel code + spdpct = 1 .else .include "iic+.defs" .endif @@ -446,15 +451,19 @@ dspd: lda ZIP5DSV ; Speed in 5D register dex ; otherwise, next entry dex bpl @sloop - ; fall through will say 0.00 MHz + ; fall through will say 0.00 MHz or 00% dspd1: tya stx COUNTER ; which speed option is selected .if ::TESTBLD stx $0e1f ; DEBUG .endif +.if ::spdpct + lda #$a0 ; space +.else and #$03 ; MHz value ora #$b0 ; to digit - sta $072b ; ones +.endif + sta $072b ; ones (MHz) or 100s (%) inx lda spdtab,x tay @@ -463,11 +472,19 @@ dspd1: tya lsr lsr ora #$b0 - sta $072d ; 10ths +.if ::spdpct + sta $072c ; 10s (%) +.else + sta $072d ; 10ths (MHz) +.endif tya and #$0f ora #$b0 - sta $072e ; 100ths +.if ::spdpct + sta $072d ; 1s (%) +.else + sta $072e ; 100ths (MHz) +.endif aminp: ldy #$00 lda #$60 sta (UBFPTRL),y diff --git a/rom5x/Rakefile b/rom5x/Rakefile index 66dcccd..a8877e7 100644 --- a/rom5x/Rakefile +++ b/rom5x/Rakefile @@ -16,6 +16,8 @@ task :clean do sh "rm -f *.o" sh "rm -f *.lst" sh "rm -f *.b" + sh "rm -f accel5x" + sh "rm -f POOF1 *.po" end desc "Assemble all source files" @@ -62,3 +64,15 @@ task :sf512 => [:build_rom] do sh "cat #{dest_rom} #{dest_rom} > sf512_#{dest_rom}" end +desc "Build accel5x test binary" +task :accel5x do + sh "ca65 -D testaccel -o accel5x.o -l accel5x.lst B1_FD00_accel5x.s" + sh "ld65 -t none -o accel5x accel5x.o" +end + +desc "Build accel5x test binary into accel5x.po disk image" +task :"accel5x.po" => [:accel5x] do + sh "to_pro -140 accel5x" + sh "mv -f POOF1 accel5x.po" +end + diff --git a/rom5x/accelmenu.h b/rom5x/accelmenu.h index 084423d..750e958 100644 --- a/rom5x/accelmenu.h +++ b/rom5x/accelmenu.h @@ -3,6 +3,10 @@ msg1: .byte $06,$a8,$81,"ccel: Off" .byte $06,$b3,$00 msg2: .byte $06,$b0,"n " .byte $06,$bc,$93,"pk Dly: On" +.if ::spdpct + .byte $07,$28,$bc,$ad," 100% ",$ad,$be +.else .byte $07,$28,$bc,$ad," 4.00 MHz ",$ad,$be +.endif .byte $07,$3c,$90,"dl Dly: On" .byte $07,$4f,$00 diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs index 9f1d84e..fb0247a 100644 --- a/rom5x/iic+.defs +++ b/rom5x/iic+.defs @@ -1,5 +1,7 @@ ; options newbeep = 0 ; 1 = use IIc+ beep +spdpct = 1 ; 1 = use percent speeds in accel config + ; hardware ;set80col = $c001 diff --git a/rom5x/spdtab.h b/rom5x/spdtab.h index 5755275..d87a97e 100644 --- a/rom5x/spdtab.h +++ b/rom5x/spdtab.h @@ -1,8 +1,29 @@ -; speed table for 4 MHz IIc Plus ; this was confirmed by measuring a delay loop ; for each speed. The delay loop was timed ; timed to 1/100 sec accuracy using the Ram ; Express II+ dclock. +.if ::spdpct +; percent speed table for any IIc Plus/Zip Chip + .byte %00000001,$00 + .byte %00100000,$83 + .byte %00010000,$80 + .byte %00001000,$75 + .byte %00000100,$67 + .byte %01000000,$50 + .byte %01100000,$42 + .byte %01010000,$40 + .byte %01001000,$38 + .byte %11000000,$33 + .byte %11100000,$28 + .byte %11010000,$27 + .byte %11001000,$25 + .byte %11000100,$22 + .byte %10100000,$21 + .byte %10010000,$20 + .byte %10001000,$19 + .byte %10000100,$17 +.else +; MHz speed table for 4 MHz IIc Plus .byte %00000000,$00 ; 4.0000 .byte %00100011,$33 ; 3.3333 .byte %00010011,$20 ; 3.2000 @@ -21,4 +42,4 @@ .byte %10010000,$80 ; 0.8000 .byte %10001000,$75 ; 0.7500 .byte %10000100,$67 ; 0.6667 - +.endif From 93114217ee04f7616bcd38fadedcd95cfe6332b2 Mon Sep 17 00:00:00 2001 From: mgcaret Date: Mon, 20 Mar 2017 12:02:52 -0700 Subject: [PATCH 7/8] 5X: remove boot 2nd 5.25 drive code snippet, not needed --- rom5x/B1_D516_boot5x.s | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/rom5x/B1_D516_boot5x.s b/rom5x/B1_D516_boot5x.s index 49a1de3..165b939 100644 --- a/rom5x/B1_D516_boot5x.s +++ b/rom5x/B1_D516_boot5x.s @@ -1,7 +1,7 @@ .code .psc02 .include "iic+.defs" - .org boot5x ; 234 bytes available, code assembles to 231 + .org boot5x ; 234 bytes available, code assembles to 222 jsr titl5x ; "Apple IIc +" jsr rdrecov ; try to recover ramdisk lda power2 + rx_mslot ; get action saved by reset5x @@ -102,11 +102,5 @@ rdinit: bit rx_mslot*$100 ; activate registers ldy #rx_mslot ; slot offset ldx #rx_devno ; register offset rts -; next is snippet of code to boot external 5.25 -bootext: lda #$e0 - ldy #$01 - ldx #$60 - jmp $c60b -bt4xend = * From 79187ea31e6d7d7ab8d4feb47d206c8faefe553d Mon Sep 17 00:00:00 2001 From: mgcaret Date: Sun, 2 Apr 2017 11:53:48 -0700 Subject: [PATCH 8/8] optimize accel5x and fix #4 --- rom4x/Rakefile | 2 +- rom5x/B1_D6CE_rom5x_misc.s | 2 +- rom5x/B1_FD00_accel5x.s | 59 ++++++++++++++++++++++---------------- rom5x/iic+.defs | 2 +- 4 files changed, 37 insertions(+), 28 deletions(-) diff --git a/rom4x/Rakefile b/rom4x/Rakefile index 241e416..4863165 100644 --- a/rom4x/Rakefile +++ b/rom4x/Rakefile @@ -48,7 +48,7 @@ task :build_rom => [:assemble] do rom.setbyte(addr, b) addr += 1 end - puts "\tNote: patched pver #{nzc} nonzero bytes!" if nzc > 0 + puts "\tNote: patched over #{nzc} nonzero bytes!" if nzc > 0 else puts "I dont know where to load #{t}" end diff --git a/rom5x/B1_D6CE_rom5x_misc.s b/rom5x/B1_D6CE_rom5x_misc.s index 38b8337..699974d 100644 --- a/rom5x/B1_D6CE_rom5x_misc.s +++ b/rom5x/B1_D6CE_rom5x_misc.s @@ -80,7 +80,7 @@ msg1 = * .byte $04,$2e,"6 Boot 5.25" .byte $04,$ae,"7 Accelerator" .byte $07,$5f,"By M.G." -msg2: .byte $07,$db,"ROM 5X 02/10/17" +msg2: .byte $07,$db,"ROM 5X 04/02/17" .byte $05,$ae,$00 ; cursor pos in menu msg3: .byte $05,$b0,"SURE? ",$00 diff --git a/rom5x/B1_FD00_accel5x.s b/rom5x/B1_FD00_accel5x.s index 48b2b56..0790cc6 100644 --- a/rom5x/B1_FD00_accel5x.s +++ b/rom5x/B1_FD00_accel5x.s @@ -207,18 +207,15 @@ coldst: lda KBDSAVE ora #$80 sta KBDSAVE jsr MIGINIT -warmst: ldx ACWL - ldy ACWH - lda KBDSAVE +warmst: lda KBDSAVE cmp #ESCKEY bne doinit ; toggle accelerator speed - tya + lda ACWH ; kept in ACWH eor #$08 ; toggle bit 4 - tay + sta ACWH doinit: jsr AUNLK ; unlock registers - jsr ACOND ; set enabled according to y reg - jsr ASETR ; set registers + jsr ASETR1 ; set registers jsr ALOCK ; lock accelerator ; set powerup bytes lda #PWRUPV0 @@ -285,10 +282,19 @@ exinit: rts sta ZIP5A lda #$10 tsb ACWH - rts + lda #$80 + trb ACWH ; z flag is 0 if bit 7 was 0 + bne :+ ; if DHiRes was off + bit ZIP5E ; otherwise make sure it is on + bra :++ +: bit ZIP5F ; make sure it is off +: rts .endproc ; ALOCK ; unlock accelerator registers .proc AUNLK + lda $c07f ; RdDHiRes - bit 7 = 1 if off, 0 if on + and #$80 + tsb ACWH ; put in ACWH lda #$5A sta ZIP5A sta ZIP5A @@ -321,9 +327,10 @@ exinit: rts ora ACWH ; merge in existing ACWH less the bits we cleared above tay ;jsr AUNLK ; Apple code unlocks in write command, prob a bug. - jsr ASETR - ;jsr ALOCK - rts + ;jsr ASETR + ;jsr ALOCK ; bug cont'd. + ;rts + ; fall through .endproc ; AWRIT ; set accelerator registers ; x = new ACWL @@ -342,28 +349,29 @@ exinit: rts ora ZIP5FSV ; merge with existing $c05f values sta ZIP5FSV ; and put back ; now set ZIP registers from MIG RAM - jsr ASETR1 + ;jsr ASETR1 ; plx ; pla ; plp - rts + ;rts + ; fall through .endproc ; ASETR1 ; set accelerator registers from saved values in MIG .proc ASETR1 - ldy ACWH - jsr ACOND ; conditionally enable accelerator - tya - and #$08 ; is it disabled? - bne setdn ; if so, don't change other registers - ldx #$03 ; otherwise set all registers from MIG + ldx #$03 ; set all registers from MIG + stx ZIP5B ; turn on accelerator for writing @loop: lda ZIP5CSV,x sta ZIP5C,x +.if ::TESTBLD + sta MIGRAM+$0c,x ; copy to unused locs for inspection +.endif .if ::ADEBUG sta $300,x ; DEBUG .endif dex bpl @loop -setdn: rts + ldy ACWH ; ACWH + jmp ACOND ; leave accelerator in configured state .endproc ; ASETR1 cmdtable: .word AINIT @@ -396,12 +404,13 @@ cmdtable: .endproc ; AWSPD .endif IACWL: .byte %01100111 ; initial ACWL - same as $C05C -IACWH: .byte %00010000 ; initial ACWH - b6 = 1=paddle fast, b4 = reg 1=lock/0=unlock - ; b3 = 1=accel disable, rest reserved +IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock + ; b3 = 1=accel disable, rest reserved by apple + ; rom5x: b7 = state of DHiRes when accelerator was unlocked IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay .byte %00000000 ; Initial $C05D - $00 = 4MHz .byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc - .byte %00000000 ; Initial $C05F - b7=0 enable L/C accel, b6=0 paddle sync + .byte %01000000 ; Initial $C05F - b7=0 enable L/C accel, b6=1 paddle sync (slow) .if ::ACCMENU ; accelerator config menu ; ---------|---------|---------|---------| @@ -433,8 +442,8 @@ amenu1: jsr disp ; disp menu with Accel Off sta $06c6 sta $06c7 dpdl: lda ZIP5FSV ; 5F register has paddle delay - and #$40 ; bit 6 = paddle delay (1 = defeat) - beq dspd ; 0 = on, skip + and #$40 ; bit 6 = paddle delay (1 = slow) + bne dspd ; 1 = on, skip lda #$e6 ; change on to off in menu sta $0746 sta $0747 diff --git a/rom5x/iic+.defs b/rom5x/iic+.defs index fb0247a..4a91d71 100644 --- a/rom5x/iic+.defs +++ b/rom5x/iic+.defs @@ -1,6 +1,6 @@ ; options newbeep = 0 ; 1 = use IIc+ beep -spdpct = 1 ; 1 = use percent speeds in accel config +spdpct = 0 ; 1 = use percent speeds in accel config ; hardware