Apple-2-SW/rom4x
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experimental accelerator reverse for accel5x

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This commit is contained in:
mgcaret 2017-04-08 14:31:52 -07:00
parent c0b6f2b229
commit f489231464
2 changed files with 21 additions and 6 deletions
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5
rom5x/B1_FD00_accel5x.s
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@ -24,6 +24,7 @@ TESTBLD = 0 ; set to 1 to enable test code that runs in random
XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands
ACCMENU = 1 ; set to 1 to enable accelerator menu ACCMENU = 1 ; set to 1 to enable accelerator menu
ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set) ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set)
AOFFDFL = 0 ; accelerator off by default
.psc02 .psc02
.if TESTBLD .if TESTBLD
@ -404,9 +405,13 @@ cmdtable:
.endproc ; AWSPD .endproc ; AWSPD
.endif .endif
IACWL: .byte %01100111 ; initial ACWL - same as $C05C IACWL: .byte %01100111 ; initial ACWL - same as $C05C
.if ::AOFFDFL
IACWH: .byte %01011000 ; initial ACWH - accelerator OFF. See below for bits
.else
IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock
; b3 = 1=accel disable, rest reserved by apple ; b3 = 1=accel disable, rest reserved by apple
; rom5x: b7 = state of DHiRes when accelerator was unlocked ; rom5x: b7 = state of DHiRes when accelerator was unlocked
.endif
IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay
.byte %00000000 ; Initial $C05D - $00 = 4MHz .byte %00000000 ; Initial $C05D - $00 = 4MHz
.byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc .byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc

22
rom5x/README.md
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@ -1,13 +1,21 @@
# ROM 5X by MG # ROM 5X by MG
## PRELIMINARY, NEEDS MORE TESTING ## Consider it a step beyond beta :-)
*ll of the functionality, including the RAM Disk recovery and other functions, *All of the functionality, including the RAM Disk recovery and other functions,
appear to work correctly, but I would appreciate any feedback if something isn't appear to work correctly, but I would appreciate any feedback if something isn't
workign for you.* workign for you.*
This is ROM 5X, providing the ROM 4X functionality to the Apple IIc Plus ROM This is ROM 5X, providing the ROM 4X functionality to the Apple IIc Plus ROM
version 5. version 5, plus some basic control functions for the Apple IIc Plus accelerator.
There are some build options in accel5x.s - some functional, others needing more
work, the most popular of which will no doubt be the option to reset the system
with the accelerator in the disabled state. The "extra commands" option will
currently fail to build because the code gets too large, and is really only for
experimental purposes.
### Nitty Gritty
There are almost no free bytes in the main bank of the IIc Plus firmware, so There are almost no free bytes in the main bank of the IIc Plus firmware, so
I had to get creative to get into the alternate bank, where I then had to split I had to get creative to get into the alternate bank, where I then had to split
@ -36,10 +44,12 @@ that change the default behavior of the Apple IIc Plus.
Enable options by copying the files to the main directory. Disable the by removing Enable options by copying the files to the main directory. Disable the by removing
the copied files. the copied files.
### Accelerator Reverse ### (Obsolete) Accelerator Reverse
The accelerator reverse patch is a 1-byte patch that causes the IIc Plus to boot up This option was obsoleted by the inclusion of Accel5X in the project.
at the normal speed.
The accelerator reverse patch is a 1-byte patch that causes a IIc Plus with the
original Apple accelerator code to start at the "normal" 1 MHz speed.
Pressing ESC at reset time will make the machine run at 4 MHz. Pressing ESC at reset time will make the machine run at 4 MHz.