mirror of https://github.com/mgcaret/rom4x.git
613 lines
16 KiB
ArmAsm
613 lines
16 KiB
ArmAsm
; Improved Apple IIc Plus accelerator firmware
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; by M.G.
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; Improvements over apple-supplied code:
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; * bugs fixed
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; * reset+<esc> toggles acclerator on/off rather than setting slow
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; * warm reset preserves configured settings
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; * additional commands to read/write accelerator speed
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; * reset+<tab> configuration menu
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; Config menu can be called independently from other alt
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; bank firmware, such as ROM 5X
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; note that in the current state, the code cannot be inserted
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; into the ROM without moving the menu text and the speeds
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; table.
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.ifdef testaccel
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TESTBLD = 1
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.else
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TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II hw/emulator at $2000
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; this disables the bank switch and uses the main RAM at $0E00 to simulate the
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; MIG RAM. Will configure a Zip Chip as if it were the IIc+ Accelerator.
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.endif
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XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands
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ACCMENU = 1 ; set to 1 to enable accelerator menu
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ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set)
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AOFFDFL = 0 ; accelerator off by default
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.psc02
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.if TESTBLD
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; test build of accel code
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spdpct = 1
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.else
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.include "iic+.defs"
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.endif
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; zero page
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ZPAGE = $00
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COUNTER = ZPAGE+0 ; used as a generic counter for loops
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CALLSP = ZPAGE+1 ; stack pointer at call time
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COMMAND = ZPAGE+2 ; command to execute
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UBFPTRL = ZPAGE+3 ; user buffer pointer - low byte
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UBFPTRH = ZPAGE+4 ; ditto - high byte
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EXITCOD = ZPAGE+5 ; exit code from command
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; stack
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STACK = $0100
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; I/O
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IOPAGE = $C000
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KBD = IOPAGE+$00
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KBDSTR = IOPAGE+$10
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ZIP5A = IOPAGE+$5A
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ZIP5B = IOPAGE+$5B
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ZIP5C = IOPAGE+$5C
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ZIP5D = IOPAGE+$5D
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ZIP5E = IOPAGE+$5E
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ZIP5F = IOPAGE+$5F
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; MIG
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.if ::TESTBLD
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MIGBASE = $0E00
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.else
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MIGBASE = $CE00
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.endif
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MIGRAM = MIGBASE
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PWRUPB0 = MIGRAM+0 ; powerup byte
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PWRUPB1 = MIGRAM+1 ; powerup byte
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ACWL = MIGRAM+2 ; accelerator control word - low, also ZIP $C05C reg
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ACWH = MIGRAM+3 ; accelerator control word - high
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KBDSAVE = MIGRAM+4 ; saved keystroke
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ZIP5CSV = MIGRAM+5 ; configured $C05C register
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ZIP5DSV = MIGRAM+6 ; configured $C05D register
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ZIP5ESV = MIGRAM+7 ; configured $C05E register
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ZIP5FSV = MIGRAM+8 ; configured $C05F register
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ZPSAVE = MIGRAM+$10 ; 8 zero page values saved here
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MIGPAG0 = MIGBASE+$A0 ; MIG set page 0
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MIGPAGI = MIGBASE+$20 ; MIG increment page
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; fixed values
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PWRUPV0 = $33
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PWRUPV1 = $55
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ESCKEY = $9B
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TABKEY = $89
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; routines we use
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WAIT = $FCA8
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AUXWAIT = $FCB5
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NORMAL = $FC27
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SWRTS2 = $C784
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.if ::TESTBLD
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.org $2000
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lda #$00
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pha
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jsr ACCEL
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rts
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.else
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.org $FD00
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.endif
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.proc ACCEL
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bra accel1
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.if ::ACCMENU
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jmp AMENU ; entry point for menu
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.else
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rts ; otherwise return to caller if they want menu
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.endif
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accel1: php
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sei
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phy
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phx
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bit MIGPAG0
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bit MIGPAGI
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bit MIGPAGI
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; save used ZP locations
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ldx #$07
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@loop: lda ZPAGE,x
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sta ZPSAVE,x
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stz ZPAGE,x
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dex
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bpl @loop
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; get command & any parameters
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tsx
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txa
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tay
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iny
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lda STACK+6,x
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sta COMMAND
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cmp #$05 ; read accelerator - first command with pointer parameter
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stx CALLSP
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bcc noparm ; no parameter command
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lda STACK+7,x
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sta UBFPTRL
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lda STACK+8,x
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sta UBFPTRH
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iny
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iny
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inx
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inx
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noparm: inx
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txs
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ldx CALLSP
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lda #$05
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sta COUNTER
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@loop: lda STACK+5,x
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sta STACK+5,y
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dex
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dey
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dec COUNTER
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bne @loop
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lda COMMAND
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.if ::XTRACMD
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cmp #$09 ; bad command number?
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.else
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cmp #$07
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.endif
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bcc docmd ; no, do command
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lda #$01
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sta EXITCOD
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bra acceldn
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docmd: asl a ; calculate jump table offset
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tax
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jsr dispcmd ; dispatch command
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acceldn:
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lda EXITCOD
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pha
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; restore zero page contnets
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ldx #$07
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@loop: lda ZPSAVE,x
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sta ZPAGE,x
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dex
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bpl @loop ; fixed bug
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pla
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plx
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ply
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plp
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; original code:
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; clc ; ...
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; cmp #$00 ; sets carry, derp
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; beq doexit
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; sec ; carry was set anyway...
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cmp #$01 ; better, carry reflect error status
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doexit:
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.if ::TESTBLD
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rts
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.else
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jmp SWRTS2
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.endif
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dispcmd:
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jmp (cmdtable,x)
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.endproc ; ACCEL
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; Initialize Accelerator (undocumented)
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.proc AINIT
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; give time for user to hit key
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ldx #$03
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@loop: lda #$FF
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.if ::TESTBLD
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jsr WAIT
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.else
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jsr AUXWAIT
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.endif
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dex
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bne @loop
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; now read keyboard
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lda KBD
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sta KBDSAVE
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; check powerup bytes
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lda PWRUPB0
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cmp #PWRUPV0
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bne coldst
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lda PWRUPB1
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cmp #PWRUPV1
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beq warmst
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coldst: lda KBDSAVE
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ora #$80
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sta KBDSAVE
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jsr MIGINIT
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warmst: lda KBDSAVE
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cmp #ESCKEY
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bne doinit
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; toggle accelerator speed
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lda ACWH ; kept in ACWH
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eor #$08 ; toggle bit 4
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sta ACWH
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doinit: jsr AUNLK ; unlock registers
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jsr ASETR1 ; set registers
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jsr ALOCK ; lock accelerator
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; set powerup bytes
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lda #PWRUPV0
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sta PWRUPB0
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lda #PWRUPV1
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sta PWRUPB1
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.if ::ACCMENU
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; now handle keyboard for menu
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lda KBDSAVE
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cmp #TABKEY
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bne initdn
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sta KBDSTR
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jsr AMENU
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.endif
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initdn: lda ACWH
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and #$08
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beq exinit ; 0 if accel enabled
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.if ::TESTBLD
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lda #$4e
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sta $0500
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sta KBDSTR
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.else
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jmp NORMAL
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.endif
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exinit: rts
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.endproc ; AINIT
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; initialize values in MIG RAM
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.proc MIGINIT
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ldx #$03
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@loop: lda IREGV,x
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sta ZIP5CSV,x
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dex
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bpl @loop
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lda IACWL
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sta ACWL
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lda IACWH
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sta ACWH
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rts
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.endproc ; MIGINIT
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; conditionally enable accelerator according to bit 4 of Y register
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.proc ACOND
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tya
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and #$08
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bne ADISA
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; otherwise fall through
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.endproc ; ACOND
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; enable accelerator
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.proc AENAB
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lda #$08
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sta ZIP5B
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trb ACWH
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rts
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.endproc ; AENAB
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; disable accelerator
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.proc ADISA
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lda #$08
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sta ZIP5A
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tsb ACWH
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rts
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.endproc ; ADISA
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; lock accelerator registers
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.proc ALOCK
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lda #$A5
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sta ZIP5A
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lda #$10
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tsb ACWH
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lda #$80
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trb ACWH ; z flag is 0 if bit 7 was 0
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bne :+ ; if DHiRes was off
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bit ZIP5E ; otherwise make sure it is on
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bra :++
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: bit ZIP5F ; make sure it is off
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: rts
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.endproc ; ALOCK
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; unlock accelerator registers
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.proc AUNLK
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lda $c07f ; RdDHiRes - bit 7 = 1 if off, 0 if on
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and #$80
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tsb ACWH ; put in ACWH
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lda #$5A
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sta ZIP5A
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sta ZIP5A
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sta ZIP5A
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sta ZIP5A
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lda #$10
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trb ACWH
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rts
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.endproc ; AUNLK
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; read accelerator
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.proc AREAD
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ldy #$00
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lda ACWL
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sta (UBFPTRL),y
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iny
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lda ACWH
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sta (UBFPTRL),y
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rts
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.endproc ; AREAD
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; write accelerator
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.proc AWRIT
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lda #$40
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trb ACWH ; clear writable bits
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ldy #$00
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lda (UBFPTRL),y
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tax
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iny
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lda (UBFPTRL),y
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and #$40 ; all other bits reserved
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ora ACWH ; merge in existing ACWH less the bits we cleared above
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tay
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;jsr AUNLK ; Apple code unlocks in write command, prob a bug.
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;jsr ASETR
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;jsr ALOCK ; bug cont'd.
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;rts
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; fall through
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.endproc ; AWRIT
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; set accelerator registers
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; x = new ACWL
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; y = new ACWH
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.proc ASETR
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; php
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; pha
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; phx
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stx ACWL
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stx ZIP5CSV
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sty ACWH
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lda #$40 ; reset paddle speed
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trb ZIP5FSV
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tya
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and #$40 ; mask paddle speed
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ora ZIP5FSV ; merge with existing $c05f values
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sta ZIP5FSV ; and put back
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; now set ZIP registers from MIG RAM
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;jsr ASETR1
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; plx
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; pla
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; plp
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;rts
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; fall through
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.endproc ; ASETR1
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; set accelerator registers from saved values in MIG
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.proc ASETR1
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ldx #$03 ; set all registers from MIG
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stx ZIP5B ; turn on accelerator for writing
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@loop: lda ZIP5CSV,x
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sta ZIP5C,x
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.if ::TESTBLD
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sta MIGRAM+$0c,x ; copy to unused locs for inspection
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.endif
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.if ::ADEBUG
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sta $300,x ; DEBUG
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.endif
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dex
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bpl @loop
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ldy ACWH ; ACWH
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jmp ACOND ; leave accelerator in configured state
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.endproc ; ASETR1
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cmdtable:
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.word AINIT
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.word AENAB
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.word ADISA
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.word ALOCK
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.word AUNLK
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.word AREAD
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.word AWRIT
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.if ::XTRACMD
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.word ARSPD
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.word AWSPD
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; get the accelerator speed register
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.proc ARSPD
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ldy #$00
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lda ZIP5DSV
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sta (UBFPTRL),y
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rts
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.endproc ; ARSPD
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; write the accelerator speed register
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.proc AWSPD
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ldy #$00
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lda (UBFPTRL),y
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sta ZIP5DSV
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tay
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jsr AUNLK
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sty ZIP5D
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jsr ALOCK
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rts
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.endproc ; AWSPD
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.endif
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IACWL: .byte %01100111 ; initial ACWL - same as $C05C
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.if ::AOFFDFL
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IACWH: .byte %01011000 ; initial ACWH - accelerator OFF. See below for bits
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.else
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IACWH: .byte %01010000 ; initial ACWH - b6 = 1=paddle slow, b4 = reg 1=lock/0=unlock
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; b3 = 1=accel disable, rest reserved by apple
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; rom5x: b7 = state of DHiRes when accelerator was unlocked
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.endif
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IREGV: .byte %01100111 ; Initial $C05C - slots & speaker: b7-b1 = slot speed. b0 = speaker delay
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.byte %00000000 ; Initial $C05D - $00 = 4MHz
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.byte %01000000 ; Initial $C05E - b7=0 enable I/O sync, b6=undoc
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.byte %01000000 ; Initial $C05F - b7=0 enable L/C accel, b6=1 paddle sync (slow)
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.if ::ACCMENU
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; accelerator config menu
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; ---------|---------|---------|---------|
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; Accel: On Spk Dly: On
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; Speed: 4.00 Pdl Dly: On
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;
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.proc AMENU
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; do this in case someone else calls us outside of AINIT
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bit MIGPAG0
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bit MIGPAGI
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bit MIGPAGI
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; save ZP locs we are using
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lda COUNTER
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pha
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lda UBFPTRH
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pha
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lda UBFPTRL
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pha
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amenu1: jsr disp ; disp menu with Accel Off
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lda ACWH ; get ACWH
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and #$08 ; check accelerator enabled
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bne aminp ; if not, go to input
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ldx #(msg2-msg1) ; rest of menu
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jsr disp0 ; on screen
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lda ZIP5CSV ; should be same as ACWL
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and #$01 ; bit 1 = speaker delay, 1 = enable
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bne dpdl ; Skip if enabled
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lda #$e6 ; Change on to off in menu
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sta $06c6
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sta $06c7
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dpdl: lda ZIP5FSV ; 5F register has paddle delay
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and #$40 ; bit 6 = paddle delay (1 = slow)
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bne dspd ; 1 = on, skip
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lda #$e6 ; change on to off in menu
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sta $0746
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sta $0747
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dspd: lda ZIP5DSV ; Speed in 5D register
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sta COUNTER ; if it is 4 MHz, this will stay 0
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tay
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beq aminp ; get input since menu already says 4.00
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ldx #38 ; # of speeds(20) * 2 - 1
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@sloop: lda spdtab,x ; get speed table speed byte
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tay
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and #$fc ; mask off irrelevant bits we use for MHz
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cmp ZIP5DSV ; see if matching
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beq dspd1 ; if so, display it
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dex ; otherwise, next entry
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dex
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bpl @sloop
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; fall through will say 0.00 MHz or 00%
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dspd1: tya
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stx COUNTER ; which speed option is selected
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.if ::TESTBLD
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stx $0e1f ; DEBUG
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.endif
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.if ::spdpct
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lda #$a0 ; space
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.else
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and #$03 ; MHz value
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ora #$b0 ; to digit
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.endif
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sta $072b ; ones (MHz) or 100s (%)
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inx
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lda spdtab,x
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tay
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lsr
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lsr
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lsr
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lsr
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ora #$b0
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.if ::spdpct
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sta $072c ; 10s (%)
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.else
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sta $072d ; 10ths (MHz)
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.endif
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tya
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and #$0f
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ora #$b0
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.if ::spdpct
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sta $072d ; 1s (%)
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.else
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sta $072e ; 100ths (MHz)
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.endif
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aminp: ldy #$00
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lda #$60
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sta (UBFPTRL),y
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@kloop: lda KBD
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bpl @kloop
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bit KBDSTR
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ckrtn: cmp #$8d ; return
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beq exit
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and #$df ; upper case
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ckA: cmp #$c1 ; 'A'
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bne ckrest
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lda ACWH
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eor #$08
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sta ACWH
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bra tomenu
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ckrest: tay
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lda ACWH ; get ACWH
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and #$08 ; check accelerator enabled
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bne tomenu ; if not, do not allow changes
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tya
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ckrt: cmp #$95 ; right arrow
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bne cklt
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ldx COUNTER
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dex
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dex
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bmi tomenu
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setspd: lda spdtab,x
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and #$fc
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sta ZIP5DSV
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bra tomenu
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cklt: cmp #$88 ; left arrow
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bne ckS
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ldx COUNTER
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inx
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inx
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cpx #35 ; should stop at 0.67
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bcc setspd
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bra tomenu
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ckS: cmp #$d3 ; 'S'
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bne ckP
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lda ZIP5CSV
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eor #$01
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sta ZIP5CSV
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sta ACWL
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bra tomenu
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ckP: cmp #$d0 ; 'P'
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bne tomenu
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lda ZIP5FSV
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eor #$40
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sta ZIP5FSV
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lda ACWH
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eor #$40
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sta ACWH
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tomenu: jmp amenu1
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; restore saved values and set accelerator
|
|
exit: pla
|
|
sta UBFPTRL
|
|
pla
|
|
sta UBFPTRH
|
|
pla
|
|
sta COUNTER
|
|
jsr AUNLK
|
|
jsr ASETR1
|
|
jsr ALOCK
|
|
jmp dclear
|
|
disp: jsr dclear
|
|
inx
|
|
ldy #$00
|
|
disp0: lda msg1,x
|
|
bne disp1
|
|
rts
|
|
disp1: inx
|
|
cmp #$20 ; ' '
|
|
bcc disp2
|
|
eor #$80
|
|
sta (UBFPTRL),y
|
|
inc UBFPTRL
|
|
bra disp0
|
|
disp2: sta UBFPTRH
|
|
lda msg1,x
|
|
sta UBFPTRL
|
|
inx
|
|
bra disp0
|
|
dclear: lda #$a0
|
|
ldx #$27
|
|
@cloop: sta $0628,x ; line 12
|
|
sta $06a8,x ; 13
|
|
sta $0728,x ; 14
|
|
sta $07a8,x ; 15
|
|
dex
|
|
bpl @cloop
|
|
rts
|
|
.if ::TESTBLD
|
|
.include "accelmenu.h"
|
|
spdtab:
|
|
.include "spdtab.h"
|
|
.else
|
|
msg1 = ::amenu1
|
|
msg2 = ::amenu2
|
|
.endif
|
|
.endproc ; AMENU
|
|
; check for run into vector and ROM checksum area
|
|
.assert * < $ffe0, error, "accel5x overran $ffe0"
|
|
.endif
|