mirror of
https://github.com/deater/tb1.git
synced 2025-01-04 20:31:37 +00:00
220 lines
7.6 KiB
ArmAsm
220 lines
7.6 KiB
ArmAsm
init_snes:
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; Setup All the Registers
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sei ; disable interrupts
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clc ; clear carry
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xce ; and exchange with X to enable native mode
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phk ; make data bank match program bank
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plb ;
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rep #$38 ; clear status bits, binary mode, A and IX/IY = 16
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.i16 ; tell assembler IX/IY=16bits
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.a16
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ldx #$1fff ; set the stack pointer to be 0x1fff
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txs ; move X to stack
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sep #$20 ; mem/A = 8 bit
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.a8
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lda #$8f ; put 0x8f in accumulator
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; (screen off, full brightness)
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sta $2100 ; store to brightness/screen reg
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stz $2101 ; sprite register (size+address, VRAM)
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stz $2102 ; sprite register (address in mem, OAM)
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stz $2103 ; "
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stz $2105 ; graphic mode register (mode 0)
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stz $2106 ; mosaic register (noplanes, nomosaic)
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stz $2107 ; plane 0 map VRAM location
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stz $2108 ; plane 1 map VRAM location
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stz $2109 ; plane 2 map VRAM location
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stz $210a ; plane 3 map VRAM location
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stz $210b ; plane 0+1 tile location
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stz $210c ; plane 2+3 tile location
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stz $210d ; Plane 0 scroll x (first 8 bits)
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stz $210d ; Plane 0 scroll x (last 3 bits) #$0 - #$07ff
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stz $210e ; Plane 0 scroll y (first 8 bits)
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stz $210e ; Plane 0 scroll y (last 3 bits) #$0 - #$07ff
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stz $210f ; Plane 1 scroll x (first 8 bits)
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stz $210f ; Plane 1 scroll x (last 3 bits) #$0 - #$07ff
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stz $2110 ; Plane 1 scroll y (first 8 bits)
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stz $2110 ; Plane 1 scroll y (last 3 bits) #$0 - #$07ff
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stz $2111 ; Plane 2 scroll x (first 8 bits)
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stz $2111 ; Plane 2 scroll x (last 3 bits) #$0 - #$07ff
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stz $2112 ; Plane 2 scroll y (first 8 bits)
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stz $2112 ; Plane 2 scroll y (last 3 bits) #$0 - #$07ff
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stz $2113 ; Plane 3 scroll x (first 8 bits)
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stz $2113 ; Plane 3 scroll x (last 3 bits) #$0 - #$07ff
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stz $2114 ; Plane 3 scroll y (first 8 bits)
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stz $2114 ; Plane 3 scroll y (last 3 bits) #$0 - #$07ff
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lda #$80 ; increase VRAM address after writing to $2119
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sta $2115 ; VRAM address increment register
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stz $2116 ; VRAM address low
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stz $2117 ; VRAM address high
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stz $211a ; Initial Mode 7 setting register
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stz $211b ; Mode 7 matrix parameter A register (low)
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lda #$01
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sta $211b ; Mode 7 matrix parameter A register (high)
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stz $211c ; Mode 7 matrix parameter B register (low)
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stz $211c ; Mode 7 matrix parameter B register (high)
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stz $211d ; Mode 7 matrix parameter C register (low)
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stz $211d ; Mode 7 matrix parameter C register (high)
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stz $211e ; Mode 7 matrix parameter D register (low)
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stz $211e ; Mode 7 matrix parameter D register (high)
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stz $211f ; Mode 7 center position X register (low)
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stz $211f ; Mode 7 center position X register (high)
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stz $2120 ; Mode 7 center position Y register (low)
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stz $2120 ; Mode 7 center position Y register (high)
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stz $2121 ; color # register
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stz $2123 ; bg1 & bg2 window mask reg
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stz $2124 ; bg3 & bg4 window mask reg
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stz $2125 ; obj & color mask reg
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stz $2126 ; window 1 left pos
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stz $2127 ; window 2 left pos
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stz $2128 ; window 3 left pos
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stz $2129 ; window 4 left pos
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stz $212a ; bg1,2,3,4 window logic reg
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stz $212b ; obj color win logic reg (or, and, xor, nor)
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lda #$01 ;
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sta $212c ; main screen desig (plane, sprite enable)
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stz $212d ; sub screen desig
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stz $212e ; window mask main screen
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stz $212f ; window mask sub screen
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lda #$30 ;
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sta $2130 ; color addition and screen addition
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stz $2131 ; add/sub desig for screen/sprite/color
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lda #$e0 ;
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sta $2132 ; color data for add/sub
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stz $2133 ; screen setting (interlace, x,y enable, SFX data)
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; $2134-$2136 - multiplication result, no initialization needed
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; $2137 - software H/V latch, no initialization needed
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; $2138 - Sprite data read, no initialization needed
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; $2139-$213A - VRAM data read, no initialization needed
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; $213B - Color RAM data read, no initialization needed
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; $213C-$213D - H/V latched data read, no initialization needed
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stz $213E ; $213E - might not be necesary, but selects PPU master/slave mode
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; $213F - PPU status flag, no initialization needed
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; $2140-$2143 - APU communication regs, no initialization required
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; $2180 - read/write WRAM register, no initialization required
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; $2181-$2183 - WRAM address, no initialization required
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; $4016-$4017 - serial JoyPad read registers, no need to initialize
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stz $4200 ; disable timers, v-blank interrupt, joypad register
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lda #$ff ;
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sta $4201 ; programmable i/o port
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; stz $4202 ; multiplicand A
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; stz $4203 ; multiplier B
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; stz $4204 ; multiplier C
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; stz $4205 ; multiplicand C
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; stz $4206 ; Divisor B
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stz $4207 ; Horizontal Count Timer
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stz $4208 ; Horizontal Count MSB
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stz $4209 ; Vertical Count Timer
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stz $420a ; Vertical Count MSB
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stz $420b ; General DMA enable
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stz $420c ; Horizontal DMA enable
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stz $420d ; Access cycle designation (slow/fast ROM)
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lda $4210 ; $4210 - NMI status, reading resets
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; $4211 - IRQ status, no need to initialize
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; $4212 - H/V blank and JoyRead status, no need to initialize
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; $4213 - programmable I/O inport, no need to initialize
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; $4214-$4215 - divide results, no need to initialize
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; $4216-$4217 - multiplication or remainder results, no need to initialize
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; $4218-$421f - JoyPad read registers, no need to initialize
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; $4300-$437F
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; no need to intialize because DMA was disabled above
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; also, we're not sure what all of the registers do, so it is better to leave them at
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; their reset state value
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ClearVRAM:
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pha
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phx
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php
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rep #$30 ; mem/A = 8 bit, X/Y = 16 bit
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sep #$20
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.a8
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lda #$80
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sta $2115 ; Set VRAM port to word access
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ldx #$1809
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stx $4300 ; Set DMA mode to fixed source, WORD to $2118/9
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ldx #$0000
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stx $2116 ; Set VRAM port address to $0000
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stx $0000 ; Set $00:0000 to $0000 (assumes scratchpad ram)
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stx $4302 ; Set source address to $xx:0000
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lda #$00
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sta $4304 ; Set source bank to $00
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ldx #$FFFF
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stx $4305 ; Set transfer size to 64k-1 bytes
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lda #$01
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sta $420B ; Initiate transfer
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stz $2119 ; clear the last byte of the VRAM
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plp
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plx
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pla
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ClearPalette:
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phx
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php
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rep #$30 ; mem/A = 8 bit, X/Y = 16 bit
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sep #$20
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.a8
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stz $2121
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ldx #$0100
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ClearPaletteLoop:
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stz $2122
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stz $2122
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dex
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bne ClearPaletteLoop
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plp
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plx
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;=================================
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; Clear Sprite Table
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;=================================
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jsr svmw_move_sprites_offscreen
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;=====================
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;**** clear WRAM *****
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;=====================
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stz $2181 ;set WRAM address to $000000
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stz $2182
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stz $2183
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ldx #$8008
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stx $4300 ;Set DMA mode to fixed source, BYTE to $2180
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ldx #.LOWORD(wram_fill_byte)
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stx $4302 ;Set source offset
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lda #^wram_fill_byte
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sta $4304 ;Set source bank
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ldx #$0000
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stx $4305 ;Set transfer size to 64k bytes
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lda #$01
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sta $420B ;Initiate transfer
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lda #$01 ;now set the next 64k bytes
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sta $420B ;Initiate transfer
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