mirror of
https://github.com/a2-4am/4cade.git
synced 2024-06-17 23:29:31 +00:00
some reset work
This commit is contained in:
parent
ac90b57991
commit
0b588f7170
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11434637
|
!be24 11435149
|
||||||
!le16 4545
|
!le16 4545
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11385850
|
!be24 11386362
|
||||||
!le16 5294
|
!le16 5294
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11326212
|
!be24 11326724
|
||||||
!le16 3654
|
!le16 3654
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11338993
|
!be24 11339505
|
||||||
!le16 4064
|
!le16 4064
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11355033
|
!be24 11355545
|
||||||
!le16 5245
|
!le16 5245
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11373547
|
!be24 11374059
|
||||||
!le16 5870
|
!le16 5870
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11439182
|
!be24 11439694
|
||||||
!le16 410
|
!le16 410
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11439936
|
!be24 11440448
|
||||||
!le16 448
|
!le16 448
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11440384
|
!be24 11440896
|
||||||
!le16 303
|
!le16 303
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11393290
|
!be24 11393802
|
||||||
!le16 1242
|
!le16 1242
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11439668
|
!be24 11440180
|
||||||
!le16 67
|
!le16 67
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11434578
|
!be24 11435090
|
||||||
!le16 59
|
!le16 59
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11433093
|
!be24 11433605
|
||||||
!le16 1404
|
!le16 1404
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11418710
|
!be24 11419222
|
||||||
!le16 521
|
!le16 521
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11391144
|
!be24 11391656
|
||||||
!le16 2146
|
!le16 2146
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11394890
|
!be24 11395402
|
||||||
!le16 6433
|
!le16 6433
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11439592
|
!be24 11440104
|
||||||
!le16 76
|
!le16 76
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11434497
|
!be24 11435009
|
||||||
!le16 81
|
!le16 81
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11439735
|
!be24 11440247
|
||||||
!le16 201
|
!le16 201
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11419231
|
!be24 11419743
|
||||||
!le16 4511
|
!le16 4511
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11423742
|
!be24 11424254
|
||||||
!le16 1591
|
!le16 1591
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11425333
|
!be24 11425845
|
||||||
!le16 1053
|
!le16 1053
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11426386
|
!be24 11426898
|
||||||
!le16 3237
|
!le16 3237
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11429623
|
!be24 11430135
|
||||||
!le16 2877
|
!le16 2877
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11432500
|
!be24 11433012
|
||||||
!le16 479
|
!le16 479
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11432979
|
!be24 11433491
|
||||||
!le16 114
|
!le16 114
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11440687
|
!be24 11441199
|
||||||
!le16 2370
|
!le16 2370
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11406279
|
!be24 11406791
|
||||||
!le16 3642
|
!le16 3642
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11409921
|
!be24 11410433
|
||||||
!le16 2795
|
!le16 2795
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11379417
|
!be24 11379929
|
||||||
!le16 6433
|
!le16 6433
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 3698688
|
!be24 3699200
|
||||||
!le16 8192
|
!le16 8192
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 3715072
|
!be24 3715584
|
||||||
!le16 8192
|
!le16 8192
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 3706880
|
!be24 3707392
|
||||||
!le16 8192
|
!le16 8192
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11317929
|
!be24 11318441
|
||||||
!le16 8283
|
!le16 8283
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11329866
|
!be24 11330378
|
||||||
!le16 9127
|
!le16 9127
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11343057
|
!be24 11343569
|
||||||
!le16 11976
|
!le16 11976
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11360278
|
!be24 11360790
|
||||||
!le16 13269
|
!le16 13269
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11394532
|
!be24 11395044
|
||||||
!le16 358
|
!le16 358
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11401323
|
!be24 11401835
|
||||||
!le16 4956
|
!le16 4956
|
||||||
|
|
|
@ -4,5 +4,5 @@
|
||||||
; This file is automatically generated
|
; This file is automatically generated
|
||||||
;
|
;
|
||||||
!byte 0
|
!byte 0
|
||||||
!be24 11412716
|
!be24 11413228
|
||||||
!le16 5994
|
!le16 5994
|
||||||
|
|
11
src/macros.a
11
src/macros.a
|
@ -375,7 +375,7 @@
|
||||||
eor #$A5
|
eor #$A5
|
||||||
sta $3F4
|
sta $3F4
|
||||||
} else {
|
} else {
|
||||||
!if >.addr != 1 {
|
!if (>.addr != 1) or (.addr = $100) {
|
||||||
lda #>.addr
|
lda #>.addr
|
||||||
sta $3F3
|
sta $3F3
|
||||||
eor #$A5
|
eor #$A5
|
||||||
|
@ -385,17 +385,22 @@
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
!macro RESET_VECTOR_HALF .addr {
|
||||||
|
lda #>.addr
|
||||||
|
sta $3F3
|
||||||
|
eor #$A5
|
||||||
|
sta $3F4
|
||||||
|
}
|
||||||
|
|
||||||
!macro RESET_AND_IRQ_VECTOR .addr {
|
!macro RESET_AND_IRQ_VECTOR .addr {
|
||||||
lda #<.addr
|
lda #<.addr
|
||||||
sta $3F2
|
sta $3F2
|
||||||
sta $3FE
|
sta $3FE
|
||||||
!if >.addr != 1 {
|
|
||||||
lda #>.addr
|
lda #>.addr
|
||||||
sta $3F3
|
sta $3F3
|
||||||
sta $3FF
|
sta $3FF
|
||||||
eor #$A5
|
eor #$A5
|
||||||
sta $3F4
|
sta $3F4
|
||||||
}
|
|
||||||
}
|
}
|
||||||
; for games that clobber $100-$105, the prelaunch code constructs a new reset vector
|
; for games that clobber $100-$105, the prelaunch code constructs a new reset vector
|
||||||
; somewhere else and sets its
|
; somewhere else and sets its
|
||||||
|
|
|
@ -18,7 +18,7 @@
|
||||||
sta $7dbf ; patch - don't increase lives
|
sta $7dbf ; patch - don't increase lives
|
||||||
sta $9c01 ; patch - don't decrease lives
|
sta $9c01 ; patch - don't decrease lives
|
||||||
+
|
+
|
||||||
+RESET_VECTOR $100
|
+RESET_VECTOR_HALF $100
|
||||||
lda #$2C
|
lda #$2C
|
||||||
sta $A0D2
|
sta $A0D2
|
||||||
sta $A0D5
|
sta $A0D5
|
||||||
|
|
|
@ -13,13 +13,6 @@
|
||||||
; clobbers $100, sets LC & page 3 reset vectors
|
; clobbers $100, sets LC & page 3 reset vectors
|
||||||
+NEW_RESET_VECTOR $7000
|
+NEW_RESET_VECTOR $7000
|
||||||
|
|
||||||
lda #$4C
|
|
||||||
sta $7003 ; JMP not (JMP)
|
|
||||||
lda $104
|
|
||||||
sta $7004
|
|
||||||
lda $105 ; clone actual TR reentry point to $7000
|
|
||||||
sta $7005 ; loops between LC and $7000 otherwise
|
|
||||||
|
|
||||||
lda #0
|
lda #0
|
||||||
sta $FFFC
|
sta $FFFC
|
||||||
lda #$70
|
lda #$70
|
||||||
|
|
|
@ -9,21 +9,25 @@
|
||||||
|
|
||||||
+ENABLE_ACCEL
|
+ENABLE_ACCEL
|
||||||
|
|
||||||
lda #<reset
|
ldx #<reset_e
|
||||||
sta $2049+1
|
- lda+2 $ff,x
|
||||||
lda #>reset
|
|
||||||
sta $2049+2
|
|
||||||
|
|
||||||
ldx #(reset_e-reset)-1
|
|
||||||
- lda callback,x
|
|
||||||
sta $50,x
|
sta $50,x
|
||||||
dex
|
dex
|
||||||
bpl -
|
bne -
|
||||||
|
|
||||||
|
lda #<reset
|
||||||
|
sta $2049+1
|
||||||
|
stx $2049+2
|
||||||
|
|
||||||
jmp $2000
|
jmp $2000
|
||||||
|
|
||||||
callback !pseudopc $50 {
|
!pseudopc $51+<* {
|
||||||
reset +NEW_RESET_VECTOR $2F0
|
reset ldx #5
|
||||||
|
- lda $51, x
|
||||||
|
sta $2F0, x
|
||||||
|
dex
|
||||||
|
bpl -
|
||||||
|
+RESET_VECTOR $2f0
|
||||||
+READ_RAM2_NO_WRITE
|
+READ_RAM2_NO_WRITE
|
||||||
lda MachineStatus
|
lda MachineStatus
|
||||||
and #CHEATS_ENABLED
|
and #CHEATS_ENABLED
|
||||||
|
@ -34,8 +38,8 @@ reset +NEW_RESET_VECTOR $2F0
|
||||||
jsr DisableAccelerator
|
jsr DisableAccelerator
|
||||||
+READ_ROM_NO_WRITE
|
+READ_ROM_NO_WRITE
|
||||||
jmp $B800
|
jmp $B800
|
||||||
reset_e
|
|
||||||
}
|
}
|
||||||
|
reset_e
|
||||||
|
|
||||||
!if * > $1C0 {
|
!if * > $1C0 {
|
||||||
!error "code is too large, ends at ", *
|
!error "code is too large, ends at ", *
|
||||||
|
|
|
@ -24,10 +24,13 @@ hook2 lda #<hook3
|
||||||
sta $9E4D+1
|
sta $9E4D+1
|
||||||
lda #>hook3
|
lda #>hook3
|
||||||
sta $9E4D+2
|
sta $9E4D+2
|
||||||
|
ldx #0
|
||||||
|
stx $9E52
|
||||||
|
inx
|
||||||
|
stx $9E53 ; reset vector fix
|
||||||
jmp $9D84 ; decompress3
|
jmp $9D84 ; decompress3
|
||||||
|
|
||||||
hook3 +RESET_VECTOR $100
|
hook3 +READ_RAM2_NO_WRITE
|
||||||
+READ_RAM2_NO_WRITE
|
|
||||||
lda MachineStatus
|
lda MachineStatus
|
||||||
and #CHEATS_ENABLED
|
and #CHEATS_ENABLED
|
||||||
beq +
|
beq +
|
||||||
|
|
|
@ -19,7 +19,7 @@
|
||||||
sta $144B ; patch - don't decrease lives
|
sta $144B ; patch - don't decrease lives
|
||||||
sta $E96 ; patch - don't increase lives
|
sta $E96 ; patch - don't increase lives
|
||||||
+
|
+
|
||||||
+RESET_VECTOR $100
|
+RESET_VECTOR_HALF $100
|
||||||
+DISABLE_ACCEL
|
+DISABLE_ACCEL
|
||||||
jmp $305
|
jmp $305
|
||||||
|
|
||||||
|
|
|
@ -7,12 +7,12 @@
|
||||||
|
|
||||||
!source "src/prelaunch/common.a"
|
!source "src/prelaunch/common.a"
|
||||||
|
|
||||||
|
+NEW_RESET_VECTOR $160
|
||||||
|
|
||||||
lda #$60
|
lda #$60
|
||||||
sta $872
|
sta $872
|
||||||
jsr $800 ; title
|
jsr $800 ; title
|
||||||
|
|
||||||
+NEW_RESET_VECTOR $100
|
|
||||||
|
|
||||||
jmp $2007
|
jmp $2007
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -25,7 +25,7 @@ callback
|
||||||
dec $8A5 ; patch - don't decrease lives
|
dec $8A5 ; patch - don't decrease lives
|
||||||
dec $8DE ; patch - don't decrease lives
|
dec $8DE ; patch - don't decrease lives
|
||||||
+
|
+
|
||||||
+RESET_VECTOR $100
|
+RESET_VECTOR_HALF $100
|
||||||
lda $7fe ; Saracen code
|
lda $7fe ; Saracen code
|
||||||
pha
|
pha
|
||||||
+DISABLE_ACCEL
|
+DISABLE_ACCEL
|
||||||
|
|
|
@ -8,11 +8,11 @@
|
||||||
!source "src/prelaunch/common.a"
|
!source "src/prelaunch/common.a"
|
||||||
|
|
||||||
+ENABLE_ACCEL
|
+ENABLE_ACCEL
|
||||||
|
+NEW_RESET_VECTOR $BFF0
|
||||||
lda #$60
|
lda #$60
|
||||||
sta $1867
|
sta $1867
|
||||||
jsr $180F ; decompress
|
jsr $180F ; decompress
|
||||||
|
|
||||||
+NEW_RESET_VECTOR $BFF0
|
|
||||||
lda #$F0
|
lda #$F0
|
||||||
sta $4001
|
sta $4001
|
||||||
lda #$BF
|
lda #$BF
|
||||||
|
|
|
@ -11,7 +11,7 @@
|
||||||
lda #$60
|
lda #$60
|
||||||
sta $60A4
|
sta $60A4
|
||||||
jsr $6000 ; decompress
|
jsr $6000 ; decompress
|
||||||
+RESET_VECTOR $100
|
+RESET_VECTOR_HALF $100
|
||||||
lda #$60
|
lda #$60
|
||||||
sta $89F
|
sta $89F
|
||||||
jsr $800 ; decompress more
|
jsr $800 ; decompress more
|
||||||
|
|
Loading…
Reference in New Issue
Block a user