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add DHGR 48boxes effects

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4am 2020-11-29 23:10:44 -05:00
parent 3311e3c785
commit 3004ecf6ee
12 changed files with 1297 additions and 0 deletions
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9
res/DFX.CONF
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@ -1,51 +1,60 @@
DHGR.FIZZLE2BIT
DHGR.RIPPLE
DHGR.SOFT.DIAG
DHGR.48BOXES
DHGR.BUBBLES
DHGR.RADIAL
DHGR.SOFT.IRIS
DHGR.WAVY.RIP
DHGR.SNOWFL.IN
DHGR.MAPLE
DHGR.48.SNAKE
DHGR.SLOW.STAR
DHGR.HEART.RIP
DHGR.CORNER4
DHGR.STAR.IN
DHGR.REDLINES
DHGR.BUTTERFLY
DHGR.48.ARROW
DHGR.BLOOM.IN
DHGR.RADIAL4
DHGR.TWOPASS.LR
DHGR.WAVY.IN
DHGR.CORNER4RIP
DHGR.48.LDIAGON
DHGR.STAR
DHGR.MAPLE.IN
DHGR.BAR.DISSLV
DHGR.BLOOM
DHGR.SLOW.STARI
DHGR.HEART
DHGR.48.2SNAKES
DHGR.RADIAL3
DHGR.STAR.RIP
DHGR.BFLY.IN
DHGR.DIAGONAL
DHGR.SNOWFLAKE
DHGR.48.DOWN
DHGR.SOFTIRISIN
DHGR.RADIAL2
DHGR.IRIS
DHGR.BUBBLES.IN
DHGR.SLOWST.RIP
DHGR.RADIAL5
DHGR.48.SPIRAL
DHGR.FIZZLE
DHGR.BFLY.RIP
DHGR.IRIS.IN
DHGR.SWIRL
DHGR.MAPLE.RIP
DHGR.R.BY.PIXEL
DHGR.48.SIDES
DHGR.HEART.IN
DHGR.SNOWFL.RIP
DHGR.CORNER4.IN
DHGR.WAVY.IRIS
DHGR.BLOOM.RIP
DHGR.48.SYNC
DHGR.FLICK
[eof]

36
src/fx/fx.dhgr.48boxes.2snakes.a Normal file
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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.2SNAKES",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FE,$FC,$FA,$D8,$D6,$D4,$D2
!byte $F2,$F4,$F6,$F8,$DA,$DC,$DE,$E0
!byte $F0,$EE,$EC,$EA,$E8,$E6,$E4,$E2
!byte $E2,$E4,$E6,$E8,$EA,$EC,$EE,$F0
!byte $E0,$DE,$DC,$DA,$F8,$F6,$F4,$F2
!byte $D2,$D4,$D6,$D8,$FA,$FC,$FE,$00
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi

52
src/fx/fx.dhgr.48boxes.a Normal file
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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48BOXES",plain
*=$6000
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $EC,$E8,$E4,$E0,$DC,$D8,$D4,$D0
!byte $F0,$EC,$E8,$E4,$E0,$DC,$D8,$D4
!byte $F4,$F0,$EC,$E8,$E4,$E0,$DC,$D8
!byte $F8,$F4,$F0,$EC,$E8,$E4,$E0,$DC
!byte $FC,$F8,$F4,$F0,$EC,$E8,$E4,$E0
!byte $00,$FC,$F8,$F4,$F0,$EC,$E8,$E4
StagesHi ; high bytes of address of drawing routine for each stage
!byte clear00
!byte clear01
!byte clear02
!byte clear03
!byte clear04
!byte clear05
!byte clear06
!byte clear07
!byte clear08
!byte clear09
!byte clear0A
!byte clear0B
!byte clear0C
!byte clear0D
!byte clear0E
!byte clear0F
!byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
!byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi

36
src/fx/fx.dhgr.48boxes.arrow.a Normal file
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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.ARROW",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $FA,$F6,$F4,$F0,$EE,$EA,$E8,$E4
!byte $FC,$FA,$F6,$F4,$F0,$EE,$EA,$E8
!byte $00,$FC,$FA,$F6,$F4,$F0,$EE,$EA
!byte $FF,$FD,$F9,$F7,$F3,$F1,$ED,$EB
!byte $FD,$F9,$F7,$F3,$F1,$ED,$EB,$E7
!byte $F9,$F7,$F3,$F1,$ED,$EB,$E7,$E5
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy00
!byte copy01
!byte copy02
!byte copy03
!byte copy04
!byte copy05
!byte copy06
!byte copy07
!byte copy08
!byte copy09
!byte copy0A
!byte copy0B
!byte copy0C
!byte copy0D
!byte copy0E
!byte copy0F
EndStagesHi

694
src/fx/fx.dhgr.48boxes.common.a Normal file
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;license:MIT
;(c) 2020 by 4am & qkumba
;
!ifndef USES_CLEAR {
; if an effect doesn't use any clear stages, you can reduce code size
; by setting USES_CLEAR=0 before including this file
USES_CLEAR = 1
}
src = $00 ; [word][must be at $00] used by drawing routines
dst = $02 ; [word] used by drawing routines
rowcount = $04 ; [byte] used by drawing routines
tmpy = $05 ; [byte] used by drawing routines
box = $0E ; [byte] counter in main loop
any = $0F ; [byte][must be at $0F] counter in main loop
BoxStages = $10 ; [$30 bytes] current stage for each box
auxsrc_hgrhi = $BC00 ; [$C0 bytes] HGR base addresses (hi) starting at $8000
hgrhi = $BD00 ; [$C0 bytes] HGR base addresses (hi) starting at $2000
hgrlo = $BE00 ; [$C0 bytes] HGR base addresses (lo) starting at $2000
BoxesX = $BDC0 ; [$30 bytes] starting row for each box
BoxesY = $BEC0 ; [$30 bytes] starting byte offset for each box
; High bytes of drawing routines for each stage (actual routines will be page-aligned).
; To minimize code size, we build drawing routines in this order:
; - copy01 (STAGE1 template)
; - copy00 (STAGE0 template)
; - copy0F..copy09 (OUTER_STAGE template)
; - copy08..copy02 (MIDDLE_STAGE template)
; - change some opcodes to turn the 'copy' routines into 'clear' routines
; - clear0F..clear08 (OUTER_STAGE)
; - clear07..clear02 (MIDDLE_STAGE)
; - clear01 (STAGE1)
; - clear00 (STAGE0)
clear00 = $70
clear01 = $71
clear02 = $72
clear03 = $73
clear04 = $74
clear05 = $75
clear06 = $76
clear07 = $77
clear08 = $78
clear09 = $79
clear0A = $7A
clear0B = $7B
clear0C = $7C
clear0D = $7D
clear0E = $7E
clear0F = $7F
copy02 = $80
copy03 = $81
copy04 = $82
copy05 = $83
copy06 = $84
copy07 = $85
copy08 = $86
copy09 = $87
copy0A = $88
copy0B = $89
copy0C = $8A
copy0D = $8B
copy0E = $8C
copy0F = $8D
copy00 = $8E
copy01 = $8F
; tokens for code generation
; used as indexes into |codegen_pieces| and |codegen_piece_lengths|,
; so keep all three in sync
k_rts = 0 ; must be 0
k_edge_left_mask_main = 1 ; must be 1
k_edge_right_mask_main = 2 ; must be 2
k_left_mask_main = 3 ; must be 3
k_right_mask_main = 4 ; must be 4
k_edge_left_mask_aux = 5 ; must be 5
k_edge_right_mask_aux = 6 ; must be 6
k_left_mask_aux = 7 ; must be 7
k_right_mask_aux = 8 ; must be 8
k_current_page = 9
k_switch_to_main = 10
k_switch_to_aux = 11
k_inx_and_recalc = 12
k_set_row_count = 13
k_set_first_row = 14
k_iny = 15
k_dey = 16
k_save_y = 17
k_restore_y = 18
k_middle_jsr = 19
k_outer_jsr = 20
k_middle_branch = 21
k_outer_branch = 22
k_bitcopy = 23
k_mask_copy_pre = 24
k_mask_copy_post = 25
k_byte_copy = 26
!source "src/fx/macros.a"
; generate |BoxesX| and |BoxesY| arrays
ldx #48
ldy #$A0
lda #$23
pha
- tya
sta BoxesX-1, x
pla
sta BoxesY-1, x
sec
sbc #5
bcs +
lda #$23
+ pha
dex
txa
and #7
bne -
tya
sec
sbc #$20
tay
txa
bne -
pla
; construct drawing routines for each stage
jsr BuildDrawingRoutines
; A=0 here
; set up zero page for drawing phase
tax
- ldy BoxInitialStages-BoxStages, x
sty $00, x
sta EndStagesHi, x
inx
bne -
; X=0 here
+BUILD_HGR_LOOKUP_TABLES_X_IS_ALREADY_0 hgrlo, hgrhi
; X=$C0 here
- lda hgrhi-1, x
clc
adc #$70
sta auxsrc_hgrhi-1, x
dex
bne -
sta $C001 ; 80STORE mode so we can bank $2000/aux in & out with STA $C055 & $C054
MainLoop ldx #48
BoxLoop stx box
ldy BoxStages-1, x ; for each box, get its current stage
inc BoxStages-1, x ; increment every box's stage every time through the loop
lda StagesHi, y
beq NextBox ; if stage's drawing routine is 0, nothing to do
sta j+2
lda BoxesX-1, x
ldy BoxesY-1, x ; Y = starting byte offset for this box
tax ; X = starting HGR row for this box
inc any ; was initialized by the BoxStages copy loop
clc
j jsr $FD00 ; [SMC] call drawing routine for this stage
ldx box
NextBox dex
bne BoxLoop
lda any
beq + ; if we didn't draw anything in any box, we're done
stx any ; X=0 here
bit $C000 ; check for key
bpl MainLoop
+ sta $C000 ; 80STORE off
; execution falls through here
; These are all the pieces of code we need to construct the drawing routines.
; There are 32 drawing routines (16 if USES_CLEAR=0), which we construct from
; four templates (below). Templates use tokens to refer to these code pieces.
; Note that several pieces overlap in order to minimize code size.
; Everything from CODEGEN_COPY_START and onward is copied to zero page for
; the code generation phase on program startup.
CODEGEN_COPY_START
!pseudopc 0 {
RTS0
rts ; also terminates MainLoop
RTS0_E
;
EDGE_LEFT_MASK_MAIN ; must be at address $01 to match token
!byte $FD
EDGE_RIGHT_MASK_MAIN ; must be at address $02 to match token
!byte $FD
LEFT_MASK_MAIN ; must be at address $03 to match token
!byte $FD
RIGHT_MASK_MAIN ; must be at address $04 to match token
!byte $FD
EDGE_LEFT_MASK_AUX ; must be at address $05 to match token
!byte $FD
EDGE_RIGHT_MASK_AUX ; must be at address $06 to match token
!byte $FD
LEFT_MASK_AUX ; must be at address $07 to match token
!byte $FD
RIGHT_MASK_AUX ; must be at address $08 to match token
!byte $FD
SWITCH_TO_MAIN
sta $C054
SWITCH_TO_MAIN_E
;
SWITCH_TO_AUX
sta $C055
lda auxsrc_hgrhi, x
sta src+1
SWITCH_TO_AUX_E
;
INX_AND_RECALC
inx
lda hgrlo, x
sta src
sta dst
lda hgrhi, x
sta dst+1
eor #$60
sta src+1
INX_AND_RECALC_E
;
SET_ROW_COUNT
ROW_COUNT=*+1
lda #$1D ; SMC
sta rowcount
SET_ROW_COUNT_E
;
SET_FIRST_ROW
txa
FIRST_ROW=*+1
adc #$0D ; SMC
tax
SET_FIRST_ROW_E
;
MASKCOPY_PRE
lda (dst), y
BIT_FOR_CLEAR
eor (src), y
!byte $29 ; (AND #$44 opcode)
MASKCOPY_PRE_E
;
MASKCOPY_POST
eor (dst), y
sta (dst), y
MASKCOPY_POST_E
;
BYTECOPY
lda (src), y
sta (dst), y
BYTECOPY_E
;
DEY1
dey
DEY1_E
;
INY1
iny
INY1_E
;
SAVE_Y
sty tmpy
SAVE_Y_E
;
RESTORE_Y
ldy tmpy
RESTORE_Y_E
;
MIDDLE_JSR
!byte $20,$46
MIDDLE_JSR_E
OUTER_JSR
!byte $20,$47
OUTER_JSR_E
MIDDLE_BRANCH
dec rowcount
!byte $10,$C8
MIDDLE_BRANCH_E
;
OUTER_BRANCH
dec rowcount
!byte $10,$C6
OUTER_BRANCH_E
codegen_piece_lengths ; length of each of the pieces
!byte RTS0_E-RTS0
!byte 1 ; edge left mask main
!byte 1 ; edge right mask main
!byte 1 ; left mask main
!byte 1 ; right mask main
!byte 1 ; edge left mask aux
!byte 1 ; edge right mask aux
!byte 1 ; left mask aux
!byte 1 ; right mask aux
!byte 1 ; current page
!byte SWITCH_TO_MAIN_E-SWITCH_TO_MAIN
!byte SWITCH_TO_AUX_E-SWITCH_TO_AUX
!byte INX_AND_RECALC_E-INX_AND_RECALC
!byte SET_ROW_COUNT_E-SET_ROW_COUNT
!byte SET_FIRST_ROW_E-SET_FIRST_ROW
!byte INY1_E-INY1
!byte DEY1_E-DEY1
!byte SAVE_Y_E-SAVE_Y
!byte RESTORE_Y_E-RESTORE_Y
!byte MIDDLE_JSR_E-MIDDLE_JSR
!byte OUTER_JSR_E-OUTER_JSR
!byte MIDDLE_BRANCH_E-MIDDLE_BRANCH
!byte OUTER_BRANCH_E-OUTER_BRANCH
!byte $FF ; negative length -> do special bitcopy logic during codegen
!byte MASKCOPY_PRE_E-MASKCOPY_PRE
!byte MASKCOPY_POST_E-MASKCOPY_POST
!byte BYTECOPY_E-BYTECOPY
codegen_pieces ; address of each of the pieces (on zero page, so 1 byte)
!byte <RTS0
!byte <EDGE_LEFT_MASK_MAIN
!byte <EDGE_RIGHT_MASK_MAIN
!byte <LEFT_MASK_MAIN
!byte <RIGHT_MASK_MAIN
!byte <EDGE_LEFT_MASK_AUX
!byte <EDGE_RIGHT_MASK_AUX
!byte <LEFT_MASK_AUX
!byte <RIGHT_MASK_AUX
!byte <codegen_dst ; current page
!byte <SWITCH_TO_MAIN
!byte <SWITCH_TO_AUX
!byte <INX_AND_RECALC
!byte <SET_ROW_COUNT
!byte <SET_FIRST_ROW
!byte <INY1
!byte <DEY1
!byte <SAVE_Y
!byte <RESTORE_Y
!byte <MIDDLE_JSR
!byte <OUTER_JSR
!byte <MIDDLE_BRANCH
!byte <OUTER_BRANCH
!byte 0 ; bitcopy pseudo-opcode has no piece of its own
!byte <MASKCOPY_PRE
!byte <MASKCOPY_POST
!byte <BYTECOPY
codegen_stage
!byte 27
codegen_maskindex
!byte 0
BuildDrawingRoutineFrom
sta <codegen_token_src
BuildDrawingRoutine
ldy #0
sty <codegen_token_x
- jsr GetNextToken
pha
jsr ProcessToken
pla
bne -
dec <codegen_dst
inc <FIRST_ROW
rts
GetNextToken
codegen_token_x=*+1
ldx #$00
codegen_token_src=*+1
lda OUTER_STAGE, x
inc <codegen_token_x
rts
ProcessBitcopyToken
jsr GetNextToken
sta <bitcopy_mask
bitcopy_mask=*+1
lda $FD ; SMC
beq ExitProcessToken ; copymask=0 -> nothing to generate
bmi + ; copymask>$80 -> assume full byte
lda #k_mask_copy_pre
jsr ProcessToken
lda <bitcopy_mask
jsr ProcessToken
lda #k_mask_copy_post
+HIDE_NEXT_BYTE
+ lda #k_byte_copy
; execution falls through here
ProcessToken
tax
lda <codegen_piece_lengths, x
bmi ProcessBitcopyToken ; only bitcopy has length>$80
sta <piece_length
lda <codegen_pieces, x
sta <piece_src
ldx #0
-
piece_src=*+1
lda $FD, x ; SMC
!byte $99,$00 ; STA $4400, Y
codegen_dst
!byte copy01 ; SMC
iny
inx
piece_length=*+1
cpx #$FD ; SMC
bcc -
ExitProcessToken
rts
CopyAuxDHGRToMain
; X=0
sta $C003 ; copy $4000-5FFF/aux to $9000-AFFF/main
ldy #$20
@a lda $4000, x
@b sta $9000, x
inx
bne @a
inc <@a+2
inc <@b+2
dey
bne @a
sta $C002
; X=0,Y=0
rts
}
EdgeLeftMasks
!byte %01100000
!byte %01111000
!byte %11111111
!byte %11111111
!byte %11111111
!byte %11111111
!byte %11111111
EdgeRightMasks
!byte %00000000
!byte %00000000
!byte %00000000
!byte %00000001
!byte %00000111
!byte %00011111
!byte %11111111
LeftMasks
!byte %01100000
!byte %00011000
!byte %00000111
!byte %00000000
RightMasks
!byte %00000000
!byte %00000000
!byte %00000000 ; also terminates LeftMasks
!byte %00000001
!byte %00000110
!byte %00011000
!byte %01100000
EdgeLeftMasksAux
!byte %00000000
!byte %00000000
!byte %00000000
!byte %01000000
!byte %01110000
!byte %01111100
!byte %11111111
RightMasksAux
!byte %00000011
!byte %00001100
!byte %01110000
!byte %00000000
LeftMasksAux
!byte %00000000
!byte %00000000
!byte %00000000 ; also terminates RightMasksAux
!byte %01000000
!byte %00110000
!byte %00001100
EdgeRightMasksAux
!byte %00000011 ; also terminates LeftMasksAux
!byte %00001111
!byte %11111111
!byte %11111111
!byte %11111111
!byte %11111111
!byte %11111111
BuildDrawingRoutines
; copy codegen data to zero page
ldx #0
- lda CODEGEN_COPY_START, x
sta $00, x
inx
bne -
;X=0 here
; copy the half of the source image from $4000/aux to main memory
jsr CopyAuxDHGRToMain
;X,Y=0 here
; generate drawing routines for copy01, then copy00
jsr BuildStage1And0
; A=0 here
lda #$FF
sta <FIRST_ROW
; generate drawing routines for copy0F..copy02, then clear0F..clear02
lda #<MIDDLE_STAGE
--- eor #(<OUTER_STAGE XOR <MIDDLE_STAGE)
sta <codegen_token_src
ldx #6
-- stx <codegen_maskindex
lda EdgeLeftMasks, x
sta <EDGE_LEFT_MASK_MAIN
lda EdgeRightMasks, x
sta <EDGE_RIGHT_MASK_MAIN
lda LeftMasks, x
sta <LEFT_MASK_MAIN
lda RightMasks, x
sta <RIGHT_MASK_MAIN
lda EdgeLeftMasksAux, x
sta <EDGE_LEFT_MASK_AUX
lda EdgeRightMasksAux, x
sta <EDGE_RIGHT_MASK_AUX
lda LeftMasksAux, x
sta <LEFT_MASK_AUX
lda RightMasksAux, x
sta <RIGHT_MASK_AUX
jsr BuildDrawingRoutine
dec <ROW_COUNT
dec <ROW_COUNT
dec <codegen_stage
bmi BuildStage1And0
lda <codegen_stage
eor #13
bne +
!if USES_CLEAR {
; reset counts and switch from copy to clear
lda #$FF
sta <FIRST_ROW
lda #$1D
sta <ROW_COUNT
lda #$A9
sta <BYTECOPY
lda #$24
sta <BIT_FOR_CLEAR
} else {
rts
}
+ lda <codegen_token_src
ldx <codegen_maskindex
dex
bmi ---
bpl -- ; always branches
; generate drawing routines for copy01, copy00 (or clear01, clear00)
BuildStage1And0
lda #%00011111
sta <LEFT_MASK_MAIN
lda #%01111100
sta <LEFT_MASK_AUX
lda #<STAGE1
jsr BuildDrawingRoutineFrom
lda #<STAGE0
jmp BuildDrawingRoutineFrom
; All template p-code must be on the same page
;!align 255,0
; Template for 'stage 0' routine (copy00), which copies the innermost
; part of the box (labeled '0' in diagram above).
STAGE0
!byte k_set_first_row
!byte k_iny
!byte k_iny
!byte k_inx_and_recalc
!byte k_bitcopy, k_left_mask_main
!byte k_switch_to_aux
!byte k_bitcopy, k_left_mask_main
!byte k_switch_to_main
!byte k_inx_and_recalc
!byte k_bitcopy, k_left_mask_aux
!byte k_switch_to_aux
!byte k_bitcopy, k_left_mask_aux
!byte k_switch_to_main
!byte k_rts ; also serves as an end-of-template marker
; Template for 'stage 1' routine (copy01), which copies the pixels
; around the innermost box (labeled '1' in diagram above).
STAGE1
!byte k_set_first_row
!byte k_iny
!byte k_iny
!byte k_inx_and_recalc
!byte k_byte_copy
!byte k_switch_to_aux
!byte k_byte_copy
!byte k_switch_to_main
!byte k_inx_and_recalc
!byte k_byte_copy
!byte k_switch_to_aux
!byte k_byte_copy
!byte k_switch_to_main
!byte k_inx_and_recalc
!byte k_byte_copy
!byte k_switch_to_aux
!byte k_byte_copy
!byte k_switch_to_main
!byte k_inx_and_recalc
!byte k_byte_copy
!byte k_switch_to_aux
!byte k_byte_copy
!byte k_switch_to_main
!byte k_rts ; also serves as an end-of-template marker
; Template for stages 2-8 (copy02..copy08)
MIDDLE_STAGE
!byte k_set_row_count
!byte k_set_first_row
!byte k_iny
!byte k_save_y
!byte k_middle_jsr, k_current_page
;-
!byte k_inx_and_recalc
!byte k_bitcopy, k_left_mask_main
!byte k_iny
!byte k_iny
!byte k_bitcopy, k_right_mask_main
!byte k_switch_to_aux
!byte k_bitcopy, k_right_mask_aux
!byte k_restore_y
!byte k_bitcopy, k_left_mask_aux
!byte k_switch_to_main
!byte k_middle_branch
;+
!byte k_inx_and_recalc
!byte k_bitcopy, k_edge_left_mask_main
!byte k_iny
!byte k_byte_copy
!byte k_iny
!byte k_bitcopy, k_edge_right_mask_main
!byte k_switch_to_aux
!byte k_bitcopy, k_edge_right_mask_aux
!byte k_dey
!byte k_byte_copy
!byte k_dey
!byte k_bitcopy, k_edge_left_mask_aux
!byte k_switch_to_main
!byte k_rts ; also serves as an end-of-template marker
; Template for stages 9-15 (copy09..copy0F)
OUTER_STAGE
!byte k_set_row_count
!byte k_set_first_row
!byte k_save_y
!byte k_outer_jsr, k_current_page
;-
!byte k_inx_and_recalc
!byte k_bitcopy, k_left_mask_main
!byte k_iny
!byte k_iny
!byte k_iny
!byte k_iny
!byte k_bitcopy, k_right_mask_main
!byte k_switch_to_aux
!byte k_bitcopy, k_right_mask_aux
!byte k_restore_y
!byte k_bitcopy, k_left_mask_aux
!byte k_switch_to_main
!byte k_outer_branch
;+
!byte k_inx_and_recalc
!byte k_bitcopy, k_edge_left_mask_main
!byte k_iny
!byte k_byte_copy
!byte k_iny
!byte k_byte_copy
!byte k_iny
!byte k_byte_copy
!byte k_iny
!byte k_bitcopy, k_edge_right_mask_main
!byte k_switch_to_aux
!byte k_bitcopy, k_edge_right_mask_aux
!byte k_dey
!byte k_byte_copy
!byte k_dey
!byte k_byte_copy
!byte k_dey
!byte k_byte_copy
!byte k_dey
!byte k_bitcopy, k_edge_left_mask_aux
!byte k_switch_to_main
!byte k_rts ; also serves as an end-of-template marker
!if >* != >STAGE0 {
!error "Templates are not all on same page"
}
; Note: the final k_rts is later copied to zero page $0F and used in MainLoop,
; so don't put any more code before BoxInitialStages.
BoxInitialStages

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!macro AUXMEM {
sta $C055
lda auxsrc_hgrhi, x
sta src+1
}
!macro MAINMEM {
sta $C054
}
!macro INX_AND_RECALC {
inx
lda hgrlo, x
sta src
sta dst
lda hgrhi, x
sta dst+1
eor #$60
sta src+1
}
!macro BITCOPY .copy, .mask {
!if .mask != %00000000 {
!if .mask = %11111111 {
!if .copy != 0 {
lda (src), y
} else {
lda #$00
}
sta (dst), y
} else {
lda (dst), y
!if .copy != 0 {
eor (src), y
} else {
bit src
}
and #.mask
eor (dst), y
sta (dst), y
}
}
}
!macro MIDDLE_STAGE_DHGR .copy, .rowcount, .firstrow, .edge_left_mask_main, .edge_right_mask_main, .left_mask_main, .right_mask_main, .edge_left_mask_aux, .edge_right_mask_aux, .left_mask_aux, .right_mask_aux {
lda #(.rowcount-2) ;k_set_row_count
sta rowcount
txa ;k_set_first_row
adc #(.firstrow-1)
tax
iny ;k_iny
sty tmpy ;k_save_y
jsr + ;k_middle_jsr, k_current_page
-
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, .left_mask_main ;k_bitcopy, k_left_mask_main
iny ;k_iny
iny ;k_iny
+BITCOPY .copy, .right_mask_main ;k_bitcopy, k_right_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, .right_mask_aux ;k_bitcopy, k_right_mask_aux
ldy tmpy ;k_restore_y
+BITCOPY .copy, .left_mask_aux ;k_bitcopy, k_left_mask_aux
+MAINMEM ;k_switch_to_main
dec rowcount ;k_middle_branch
bpl -
+
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, .edge_left_mask_main ;k_bitcopy, k_edge_left_mask_main
iny ;k_iny
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
iny ;k_iny
+BITCOPY .copy, .edge_right_mask_main ;k_bitcopy, k_edge_right_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, .edge_right_mask_aux ;k_bitcopy, k_edge_right_mask_aux
dey ;k_dey
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
dey ;k_dey
+BITCOPY .copy, .edge_left_mask_aux ;k_bitcopy, k_edge_left_mask_aux
+MAINMEM ;k_switch_to_main
rts
}
!macro OUTER_STAGE_DHGR .copy, .rowcount, .firstrow, .edge_left_mask_main, .edge_right_mask_main, .left_mask_main, .right_mask_main, .edge_left_mask_aux, .edge_right_mask_aux, .left_mask_aux, .right_mask_aux {
lda #(.rowcount-2) ;k_set_row_count
sta rowcount
txa ;k_set_first_row
adc #(.firstrow-1)
tax
sty tmpy ;k_save_y
jsr + ;k_outer_jsr
-
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, .left_mask_main ;k_bitcopy, k_left_mask_main
iny ;k_iny
iny ;k_iny
iny ;k_iny
iny ;k_iny
+BITCOPY .copy, .right_mask_main ;k_bitcopy, k_right_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, .right_mask_aux ;k_bitcopy, k_right_mask_aux
ldy tmpy ;k_restore_y
+BITCOPY .copy, .left_mask_aux ;k_bitcopy, k_left_mask_aux
+MAINMEM ;k_switch_to_main
dec rowcount ;k_outer_branch
bpl -
+
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, .edge_left_mask_main ;k_bitcopy, k_edge_left_mask_main
iny ;k_iny
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
iny ;k_iny
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
iny ;k_iny
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
iny ;k_iny
+BITCOPY .copy, .edge_right_mask_main ;k_bitcopy, k_edge_right_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, .edge_right_mask_aux ;k_bitcopy, k_edge_right_mask_aux
dey ;k_dey
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
dey ;k_dey
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
dey ;k_dey
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
dey ;k_dey
+BITCOPY .copy, .edge_left_mask_aux ;k_bitcopy, k_edge_left_mask_aux
+MAINMEM ;k_switch_to_main
rts
}
!macro STAGE0 .copy {
txa ;k_set_first_row
adc #($0F-1)
tax
iny ;k_iny
iny ;k_iny
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %00011111 ;k_bitcopy, k_left_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %01111100 ;k_bitcopy, k_left_mask_aux
+MAINMEM ;k_switch_to_main
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %00011111 ;k_bitcopy, k_left_mask_main
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %01111100 ;k_bitcopy, k_left_mask_aux
+MAINMEM ;k_switch_to_main
rts
}
!macro STAGE1 .copy {
txa ;k_set_first_row
adc #($0E-1)
tax
iny ;k_iny
iny ;k_iny
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+MAINMEM ;k_switch_to_main
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+MAINMEM ;k_switch_to_main
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+MAINMEM ;k_switch_to_main
+INX_AND_RECALC ;k_inx_and_recalc
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+AUXMEM ;k_switch_to_aux
+BITCOPY .copy, %11111111 ;k_bitcopy, k_full_mask
+MAINMEM ;k_switch_to_main
rts
}
;clear00
*=$7000
+STAGE0 0
;clear01
*=$7100
+STAGE1 0
;clear02-0F
*=$7200
+MIDDLE_STAGE_DHGR 0, $05, $0D, %01100000, %00000000, %01100000, %00000000, %00000000, %00000011, %00000000, %00000011
*=$7300
+MIDDLE_STAGE_DHGR 0, $07, $0C, %01111000, %00000000, %00011000, %00000000, %00000000, %00001111, %00000000, %00001100
*=$7400
+MIDDLE_STAGE_DHGR 0, $09, $0B, %11111111, %00000000, %00000111, %00000000, %00000000, %11111111, %00000000, %01110000
*=$7500
+MIDDLE_STAGE_DHGR 0, $0B, $0A, %11111111, %00000001, %00000000, %00000001, %01000000, %11111111, %01000000, %00000000
*=$7600
+MIDDLE_STAGE_DHGR 0, $0D, $09, %11111111, %00000111, %00000000, %00000110, %01110000, %11111111, %00110000, %00000000
*=$7700
+MIDDLE_STAGE_DHGR 0, $0F, $08, %11111111, %00011111, %00000000, %00011000, %01111100, %11111111, %00001100, %00000000
*=$7800
+MIDDLE_STAGE_DHGR 0, $11, $07, %11111111, %11111111, %00000000, %01100000, %11111111, %11111111, %00000011, %00000000
*=$7900
+OUTER_STAGE_DHGR 0, $13, $06, %01100000, %00000000, %01100000, %00000000, %00000000, %00000011, %00000000, %00000011
*=$7A00
+OUTER_STAGE_DHGR 0, $15, $05, %01111000, %00000000, %00011000, %00000000, %00000000, %00001111, %00000000, %00001100
*=$7B00
+OUTER_STAGE_DHGR 0, $17, $04, %11111111, %00000000, %00000111, %00000000, %00000000, %11111111, %00000000, %01110000
*=$7C00
+OUTER_STAGE_DHGR 0, $19, $03, %11111111, %00000001, %00000000, %00000001, %01000000, %11111111, %01000000, %00000000
*=$7D00
+OUTER_STAGE_DHGR 0, $1B, $02, %11111111, %00000111, %00000000, %00000110, %01110000, %11111111, %00110000, %00000000
*=$7E00
+OUTER_STAGE_DHGR 0, $1D, $01, %11111111, %00011111, %00000000, %00011000, %01111100, %11111111, %00001100, %00000000
*=$7F00
+OUTER_STAGE_DHGR 0, $1F, $00, %11111111, %11111111, %00000000, %01100000, %11111111, %11111111, %00000011, %00000000
;copy02-08
; cp rowc frow edgeleft edgeright left right edgeltaux edgertaux leftaux rightaux
*=$A000
+MIDDLE_STAGE_DHGR 1, $05, $0D, %01100000, %00000000, %01100000, %00000000, %00000000, %00000011, %00000000, %00000011
*=$A100
+MIDDLE_STAGE_DHGR 1, $07, $0C, %01111000, %00000000, %00011000, %00000000, %00000000, %00001111, %00000000, %00001100
*=$A200
+MIDDLE_STAGE_DHGR 1, $09, $0B, %11111111, %00000000, %00000111, %00000000, %00000000, %11111111, %00000000, %01110000
*=$A300
+MIDDLE_STAGE_DHGR 1, $0B, $0A, %11111111, %00000001, %00000000, %00000001, %01000000, %11111111, %01000000, %00000000
*=$A400
+MIDDLE_STAGE_DHGR 1, $0D, $09, %11111111, %00000111, %00000000, %00000110, %01110000, %11111111, %00110000, %00000000
*=$A500
+MIDDLE_STAGE_DHGR 1, $0F, $08, %11111111, %00011111, %00000000, %00011000, %01111100, %11111111, %00001100, %00000000
*=$A600
+MIDDLE_STAGE_DHGR 1, $11, $07, %11111111, %11111111, %00000000, %01100000, %11111111, %11111111, %00000011, %00000000
;copy09-0F
*=$A700
+OUTER_STAGE_DHGR 1, $13, $06, %01100000, %00000000, %01100000, %00000000, %00000000, %00000011, %00000000, %00000011
*=$A800
+OUTER_STAGE_DHGR 1, $15, $05, %01111000, %00000000, %00011000, %00000000, %00000000, %00001111, %00000000, %00001100
*=$A900
+OUTER_STAGE_DHGR 1, $17, $04, %11111111, %00000000, %00000111, %00000000, %00000000, %11111111, %00000000, %01110000
*=$AA00
+OUTER_STAGE_DHGR 1, $19, $03, %11111111, %00000001, %00000000, %00000001, %01000000, %11111111, %01000000, %00000000
*=$AB00
+OUTER_STAGE_DHGR 1, $1B, $02, %11111111, %00000111, %00000000, %00000110, %01110000, %11111111, %00110000, %00000000
*=$AC00
+OUTER_STAGE_DHGR 1, $1D, $01, %11111111, %00011111, %00000000, %00011000, %01111100, %11111111, %00001100, %00000000
*=$AD00
+OUTER_STAGE_DHGR 1, $1F, $00, %11111111, %11111111, %00000000, %01100000, %11111111, %11111111, %00000011, %00000000
;copy00
*=$AE00
+STAGE0 1
;copy01
*=$AF00
+STAGE1 1

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.DOWN",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FF,$00,$FF,$00,$FF,$00,$FF
!byte $FE,$FD,$FE,$FD,$FE,$FD,$FE,$FD
!byte $FC,$FB,$FC,$FB,$FC,$FB,$FC,$FB
!byte $FA,$F9,$FA,$F9,$FA,$F9,$FA,$F9
!byte $F8,$F7,$F8,$F7,$F8,$F7,$F8,$F7
!byte $F6,$F5,$F6,$F5,$F6,$F5,$F6,$F5
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.LDIAGON",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FE,$FC,$FA,$F8,$F6,$F4,$F2
!byte $FE,$FC,$FA,$F8,$F6,$F4,$F2,$F0
!byte $FC,$FA,$F8,$F6,$F4,$F2,$F0,$EE
!byte $FA,$F8,$F6,$F4,$F2,$F0,$EE,$EC
!byte $F8,$F6,$F4,$F2,$F0,$EE,$EC,$EA
!byte $F6,$F4,$F2,$F0,$EE,$EC,$EA,$E8
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy00
!byte copy01
!byte copy02
!byte copy03
!byte copy04
!byte copy05
!byte copy06
!byte copy07
!byte copy08
!byte copy09
!byte copy0A
!byte copy0B
!byte copy0C
!byte copy0D
!byte copy0E
!byte copy0F
EndStagesHi

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.SIDES",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FC,$F8,$F4,$F0,$EC,$E8,$E4
!byte $E4,$E8,$EC,$F0,$F4,$F8,$FC,$00
!byte $00,$FC,$F8,$F4,$F0,$EC,$E8,$E4
!byte $E4,$E8,$EC,$F0,$F4,$F8,$FC,$00
!byte $00,$FC,$F8,$F4,$F0,$EC,$E8,$E4
!byte $E4,$E8,$EC,$F0,$F4,$F8,$FC,$00
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy00
!byte copy01
!byte copy02
!byte copy03
!byte copy04
!byte copy05
!byte copy06
!byte copy07
!byte copy08
!byte copy09
!byte copy0A
!byte copy0B
!byte copy0C
!byte copy0D
!byte copy0E
!byte copy0F
EndStagesHi

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.SNAKE",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FF,$FE,$FD,$FC,$FB,$FA,$F9
!byte $F1,$F2,$F3,$F4,$F5,$F6,$F7,$F8
!byte $F0,$EF,$EE,$ED,$EC,$EB,$EA,$E9
!byte $E1,$E2,$E3,$E4,$E5,$E6,$E7,$E8
!byte $E0,$DF,$DE,$DD,$DC,$DB,$DA,$D9
!Byte $D1,$D2,$D3,$D4,$D5,$D6,$D7,$D8
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.SPIRAL",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$E9,$EA,$EB,$EC,$ED,$EE,$EF
!byte $FF,$E8,$D9,$DA,$DB,$DC,$DD,$F0
!byte $FE,$E7,$D8,$D1,$D2,$D3,$DE,$F1
!byte $FD,$E6,$D7,$D6,$D5,$D4,$DF,$F2
!byte $FC,$E5,$E4,$E3,$E2,$E1,$E0,$F3
!byte $FB,$FA,$F9,$F8,$F7,$F6,$F5,$F4
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi

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;license:MIT
;(c) 2020 by 4am & qkumba
;
!cpu 6502
!to "build/FX/DHGR.48.SYNC",plain
*=$6000
USES_CLEAR = 0
!source "src/fx/fx.dhgr.48boxes.common.a"
!byte $00,$FF,$00,$FF,$00,$FF,$00,$FF
!byte $FF,$00,$FF,$00,$FF,$00,$FF,$00
!byte $00,$FF,$00,$FF,$00,$FF,$00,$FF
!byte $FF,$00,$FF,$00,$FF,$00,$FF,$00
!byte $00,$FF,$00,$FF,$00,$FF,$00,$FF
!byte $FF,$00,$FF,$00,$FF,$00,$FF,$00
StagesHi ; high bytes of address of drawing routine for each stage
!byte copy0F
!byte copy0E
!byte copy0D
!byte copy0C
!byte copy0B
!byte copy0A
!byte copy09
!byte copy08
!byte copy07
!byte copy06
!byte copy05
!byte copy04
!byte copy03
!byte copy02
!byte copy01
!byte copy00
EndStagesHi