mirror of https://github.com/a2-4am/4cade.git
shave some bytes
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parent
3e27200935
commit
93e0b82214
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@ -5,24 +5,22 @@
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!to "build/DGR.FIZZLE",plain
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!to "build/DGR.FIZZLE",plain
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*=$6000
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*=$6000
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ldx #(end-start) ; copy LFSR code to zero page
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ldx #(end-start+1) ; copy LFSR code to zero page
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- ldy start-1, x
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- ldy start-2, x
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sty $FF, x
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sty $81, x
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dex
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dex
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bne -
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bne -
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jmp loop
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jmp loop
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start
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start
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!pseudopc 0 {
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!pseudopc $83 {
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!byte 0
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;X=0
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;X=0
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;Y=0
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;Y=0
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loop txa
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loop txa
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loop1 eor #$05 ; LFSR form 0x0500 with period 2047
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loop1 eor #$05 ; LFSR form 0x0500 with period 2047
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ldx #$80
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wait inx
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wait dex
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bpl wait
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bne wait
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tax
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tax
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loop2 tya
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loop2 tya
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and #$78
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and #$78
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@ -31,13 +29,14 @@ loop2 tya
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txa
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txa
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ora #$04
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ora #$04
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sta <dst+2
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sta <dst+2
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lda <addrs, x
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txa
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bmi aux
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;C=0
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adc #$7C
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bpl aux
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sta $C004
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sta $C004
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bpl + ; always branches
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!byte $24
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aux and #$7F
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aux sta $C005
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sta $C005
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setsrc sta <src+2
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+ sta <src+2
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src lda $FD00, y ; SMC high byte
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src lda $FD00, y ; SMC high byte
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dst sta $FD00, y ; SMC high byte
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dst sta $FD00, y ; SMC high byte
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next txa
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next txa
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@ -52,14 +51,12 @@ next txa
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bmi exit
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bmi exit
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txa
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txa
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bne loop1
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bne loop1
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exit lda $4400 ; last lousy byte (because LFSR never hits 0)
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exit lda $7C00 ; last lousy byte (because LFSR never hits 0)
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!if *+1 != $C0 {
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!error *
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}
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sta $0400
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sta $0400
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sta $C004
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sta $C004
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rts
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rts
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; source data is at $4000-$47FF/main
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; $4000-$43FF/main -> $0400-$07FF/aux
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; $4400-$47FF/main -> $0400-$07FF/main
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addrs
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!byte $44,$45,$46,$47,$C0,$C1,$C2,$C3
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}
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}
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end
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end
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@ -4,5 +4,5 @@
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; This file is automatically generated
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; This file is automatically generated
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;
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;
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!byte 0
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!byte 0
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!be24 10956340
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!be24 10956327
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!le16 448
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!le16 448
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@ -4,5 +4,5 @@
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; This file is automatically generated
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; This file is automatically generated
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;
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;
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!byte 0
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!byte 0
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!be24 10956788
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!be24 10956775
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!le16 303
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!le16 303
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@ -5,4 +5,4 @@
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;
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;
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!byte 0
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!byte 0
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!be24 10956046
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!be24 10956046
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!le16 93
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!le16 80
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@ -4,5 +4,5 @@
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; This file is automatically generated
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; This file is automatically generated
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;
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;
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!byte 0
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!byte 0
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!be24 10956139
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!be24 10956126
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!le16 201
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!le16 201
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@ -4,5 +4,5 @@
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; This file is automatically generated
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; This file is automatically generated
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;
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;
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!byte 0
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!byte 0
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!be24 10957091
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!be24 10957078
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!le16 2370
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!le16 2370
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@ -106,8 +106,8 @@ BlankDGR
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LoadIndexedDGRFile
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LoadIndexedDGRFile
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; in: caller has set IndexedDGRFilename
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; in: caller has set IndexedDGRFilename
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; out: all flags & registers clobbered
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; out: all flags & registers clobbered
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jsr LoadIndexedFile ; load index file into $4A00
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jsr LoadIndexedFile ; load index file into $4000
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- !word $4A00
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- !word $4000
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!word kDGRActionIndexRecord
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!word kDGRActionIndexRecord
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jsr okvs_find
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jsr okvs_find
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@ -116,10 +116,9 @@ IndexedDGRFilename
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!word $FDFD ; SMC
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!word $FDFD ; SMC
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+ST16 @indexRecordPtr
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+ST16 @indexRecordPtr
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jsr LoadIndexedFile ; load entire DGR screenshot at $4000..$47FF
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jsr LoadIndexedFile ; load entire DGR screenshot at $7C00
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!word $4000 ; because that's where the transition code expects to find it
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!word $7C00 ; because that's where the transition code expects to find it
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; auxmem half is first ($4000..$43FF)
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; auxmem half is first, mainmem second
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; mainmem half is second ($4400..$47FF)
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@indexRecordPtr
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@indexRecordPtr
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!word $FDFD ; SMC
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!word $FDFD ; SMC
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rts
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rts
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