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make IIc VBL consistent with IIe
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parent
2272f77789
commit
ba033a5ea8
@ -13,21 +13,22 @@ WaitForVBL_iie ; IIe/IIgs have a relatively sane VBL
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; but it's reversed between the two
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; but it's reversed between the two
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; so we default to IIe, and patch in
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; so we default to IIe, and patch in
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; the reverse case if it's a IIGS.
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; the reverse case if it's a IIGS.
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- bit $C019
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patch_VBL_iigs1
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bpl -
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patch_VBL_iic1
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patch_VBL_iic1
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- lda $C019 ; $c019 bit 7 is sticky, reset it (SMC->#$70 for IIc)
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- lda $C019 ; $c019 bit 7 is sticky, reset it (SMC->#$70 for IIc)
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patch_VBL_iigs1
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patch_VBL_iic2
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patch_VBL_iic2
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bpl -
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- bit $C019
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patch_VBL_iic3
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patch_VBL_iigs2
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patch_VBL_iigs2
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bmi -
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bmi -
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WaitForVBL_nop ; II/II+ have no easy VBL
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WaitForVBL_nop ; II/II+ have no easy VBL
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rts
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rts
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iUnwaitForVBL
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iUnwaitForVBL
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lda $C070 ; $c019 bit 7 is sticky, reset it
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- bit $C019
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- bit $C019
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bpl -
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bpl -
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lda $C070 ; $c019 bit 7 is sticky, reset it
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sta $C07F ; enable access to VBL register
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sta $C07F ; enable access to VBL register
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sta $C05A ; disable VBL polling
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sta $C05A ; disable VBL polling
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sta $C07E ; disable access to VBL register
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sta $C07E ; disable access to VBL register
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@ -28,10 +28,11 @@ BuildVBLFunction
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@NotGS
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@NotGS
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rts
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rts
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@build_iic
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@build_iic
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sta patch_VBL_iic2+1
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lda #$70
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lda #$70
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sta patch_VBL_iic1+1
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sta patch_VBL_iic1+1
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lda #$60
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lda #$10
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sta patch_VBL_iic2
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sta patch_VBL_iic3
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lda #<iWaitForVBL
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lda #<iWaitForVBL
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sta WaitForVBL+1
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sta WaitForVBL+1
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lda #>iWaitForVBL
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lda #>iWaitForVBL
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