mirror of
https://github.com/a2-4am/4cade.git
synced 2024-11-19 02:10:39 +00:00
factor out more FX routines, and fix some RAM bank confusion now that launcher code extends below E000
This commit is contained in:
parent
90a6f55ddf
commit
d75c1cc039
@ -39,10 +39,15 @@ FirstMover
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;
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; If there is no stack to restore, this exits via SearchMode.
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;
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; in: none
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; in: LC RAM bank 1 or 2 must be banked in for reading because that's where
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; this code lives
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; out: see above
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;------------------------------------------------------------------------------
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Reenter
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; ensure that this code is high enough that it can function with
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; either LC RAM bank 1 or 2 banked in, because we might switch banks
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; during the routine
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!if (RELBASE != $2000) and (* < $E000) { !serious "Reenter is too low" }
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cld
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sta $C000 ; Turn 80STORE switch off
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ldx #$ff
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@ -157,6 +162,7 @@ gGlobalPrefsStore
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+DEFINE_INDIRECT_VECTOR iRippleCoordinates3Bit, RippleCoordinates3Bit
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+DEFINE_INDIRECT_VECTOR iReverseCoordinates3Bit, ReverseCoordinates3Bit
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+DEFINE_INDIRECT_VECTOR iSetupPrecomputed3Bit, SetupPrecomputed3Bit
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+DEFINE_INDIRECT_VECTOR iHGRPrecomputed2Bit, HGRPrecomputed2Bit
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+DEFINE_INDIRECT_VECTOR iRippleCoordinates2Bit, RippleCoordinates2Bit
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+DEFINE_INDIRECT_VECTOR iReverseCoordinates2Bit, ReverseCoordinates2Bit
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+DEFINE_INDIRECT_VECTOR iBuildDHGRSparseBitmasks2Bit, BuildDHGRSparseBitmasks2Bit
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181
src/4cade.init.a
181
src/4cade.init.a
@ -7,7 +7,7 @@
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; .SYSTEM file is loaded
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;
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!src "src/4cade.init.machine.a"
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!src "src/4cade.init.machine.a" ; exits with ROM read, no write
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!src "src/4cade.init.screen.a"
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; print text title in same place as graphical title will appear
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@ -21,7 +21,8 @@
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}
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jsr Has64K ; check for 64K (required)
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bcc +
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; exits with ROM read, no write
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bcc @enough_mem
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ldy #@no64Klen
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- lda @s_no64K,y
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@ -32,26 +33,30 @@
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@s_no64K !scrxor $80,"REQUIRES 64K"
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@no64Klen=(*-@s_no64K)-1
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+
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@enough_mem
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lda #0
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sta zpMachineStatus
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sta SETC3ROM
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jsr HasVidHDCard ; check for VidHD card (allows super hi-res artwork even on non-IIgs machines)
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; does not rely on ROM
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sta CLRC3ROM
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ror zpMachineStatus
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lda ROM_MACHINEID
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lda ROM_MACHINEID ; requires ROM read
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cmp #$06
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bne @NotGS
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sec
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jsr $FE1F ; check for IIgs (allows super hi-res artwork)
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; requires ROM read
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bcs @NotGS
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sec
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+HIDE_NEXT_BYTE
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@NotGS clc
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ror zpMachineStatus
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jsr Has128K ; check for 128K (allows DHGR slideshows and 128K games)
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; exits with ROM read, no write
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ror zpMachineStatus
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jsr HasJoystick ; check for joystick (absence is OK but we filter out some games that require a joystick)
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; requires ROM read
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ror zpMachineStatus
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; now bit 4 = 1 if VidHD
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; bit 5 = 1 if IIgs
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@ -83,7 +88,7 @@
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+
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; accommodate uppercase-only machines (64K ][ and ][+ are supported)
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lda ROM_MACHINEID
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lda ROM_MACHINEID ; requires ROM read
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cmp #$A0
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beq + ; Spectrum ED
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cmp #$06
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@ -98,14 +103,14 @@
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; print version or build number in lower right corner
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ldx #28
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ldy #23
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jsr SetCursorPosition
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jsr SetCursorPosition ; requires ROM read
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+LDADDR LoadingVersion
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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!ifndef RELEASE {
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lda LoadingBuild
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ldx LoadingBuild+1
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ldy #0
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jsr PrintAsDecimal
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jsr PrintAsDecimal ; requires ROM read
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}
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; set up text window so it only covers lower left corner
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@ -117,7 +122,7 @@
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; print machine configuration in lower left corner
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ldx #0
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ldy #23
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jsr SetCursorPosition
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jsr SetCursorPosition ; requires ROM read
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; if zpMachineStatus AND IS_IIGS then print 'IIgs'
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; else if zpMachineStatus AND HAS_128K then print '128K'
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@ -135,21 +140,21 @@
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+
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+LDADDR Loading64K
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@printMem
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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; if zpMachineStatus AND HAS_JOYSTICK then CR & print 'joystick'
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lda zpMachineStatus
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and #HAS_JOYSTICK
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beq +
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+LDADDR LoadingJoystick
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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+
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; if zpMachineStatus AND HAS_VIDHD then CR & print 'VidHD'
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lda zpMachineStatus
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and #HAS_VIDHD
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beq +
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+LDADDR LoadingVidHD
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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+
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@Relocate
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@ -159,30 +164,24 @@
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and #IS_IIGS
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beq +
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jsr HackThaCFFA
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+
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; initialize and relocate ProRWTS2 to $D400 in LC RAM bank 2
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+READ_ROM_WRITE_RAM2
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jsr init ; initialize and relocate ProRWTS2 to $D400 in RAM bank 2
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; ProRWTS2 disk-data live at $D000-D3FF
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sei ; we're about to overwrite ProDOS's IRQ handler
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jsr init ; requires RAM2 write
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; overwrite ProDOS IRQ handler
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sei
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lda #<NOIRQ
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sta $3FE
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lda #>NOIRQ ; in case another routine re-enables them
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lda #>NOIRQ
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sta $3FF
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cli
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ldx #$00 ; relocate program code to top of language card
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; since we end at $0000 now, adjust low offset to avoid destroying zpage
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@FM lda FirstMover - (RELBASE & $FF),x
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sta RELBASE & $FF00,x
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inx
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bne @FM
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inc @FM+2
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inc @FM+5
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bne @FM
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; relocate pseudo-ProDOS to LC RAM bank 2
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ldx #$00
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ldy #>(255 + EvenLasterMover - LastMover)
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@LM lda COPYSRC,x ; relocate pseudo-ProDOS to RAM bank 2
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sta COPYDST,x
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@LM lda COPYSRC, x
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sta COPYDST, x ; requires RAM2 write
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inx
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bne @LM
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inc @LM+2
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@ -190,10 +189,35 @@
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dey
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bne @LM
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+READ_RAM1_WRITE_RAM1
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jsr BuildAcceleratorFunction ; requires ROM read
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+ST16 @accelSrc
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dex
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-
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@accelSrc=*+1
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lda $FDFD,x ; copy (de)acceleration functions to LC RAM bank 2
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sta DisableAccelerator,x ; requires RAM2 write
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dex
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bpl -
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; X=FF
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; relocate program code to LC RAM bank 1
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; since we end at $0000 now, we adjust low offset to avoid destroying zpage
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+READ_ROM_WRITE_RAM1
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inx
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;X=0
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@FM lda FirstMover - (RELBASE & $FF), x
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sta RELBASE & $FF00, x ; requires RAM1 write
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inx
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bne @FM
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inc @FM+2
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inc @FM+5
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bne @FM
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;X=0
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; relocate font data to LC RAM bank 1
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ldy #4
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@ELM lda FONTSRC,x ; relocate font data to $D100/LC1
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sta FONTDST,x
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@ELM lda FONTSRC, x
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sta FONTDST, x ; requires RAM1 write
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inx
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bne @ELM
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inc @ELM+2
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@ -201,30 +225,19 @@
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dey
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bne @ELM
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+READ_ROM_NO_WRITE
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jsr BuildAcceleratorFunction
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+READ_RAM2_WRITE_RAM2
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+ST16 @accelSrc
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dex
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-
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@accelSrc=*+1
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lda $FDFD,x ; copy (de)acceleration functions to RAM bank 2
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sta DisableAccelerator,x
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dex
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bpl -
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+READ_ROM_WRITE_RAM2
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jsr BuildVBLFunction
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+DISABLE_ACCEL ; cycle counting in Mockingboard detection requires 1MHz
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; /!\ macro exits with ROM read, no write
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+LDADDR FoundMockingboardCallback
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jsr GetMockingboardStuff
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+READ_RAM2_WRITE_RAM2
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stx MockingboardStuff ; save mockingboard slot and type in LC RAM
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+READ_ROM_NO_WRITE
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jsr GetMockingboardStuff ; requires ROM read
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; /!\ exits with ROM read, no write
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+READ_ROM_WRITE_RAM1
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stx MockingboardStuff ; save mockingboard slot and type
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; requires RAM1 write
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jsr BuildVBLFunction ; requires ROM read, RAM1 write
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txa
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beq +
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beq @done_with_mb
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and #HAS_STEREO
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beq @mb_mono
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+LDADDR LoadingMockingboardStereo
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@ -232,18 +245,18 @@
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@mb_mono
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+LDADDR LoadingMockingboardStereo
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@mb_print
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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; if Mockingboard AND HAS_SPEECH then print CR & '...and it talks!'
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txa
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and #HAS_SPEECH
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beq +
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beq @done_with_mb
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+LDADDR LoadingMockingboardSpeech
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jsr LoadingPrint
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jsr LoadingPrint ; requires ROM read
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+
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+READ_RAM2_WRITE_RAM2
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jsr EnableAccelerator
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@done_with_mb
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+READ_RAM2_NO_WRITE
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jsr EnableAccelerator ; requires RAM2 read
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jmp OneTimeSetup
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; ProRWTS2 has its own function to relocate itself
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@ -347,8 +360,10 @@ PrintAsDecimal
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!source "src/parse.common.a"
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OneTimeSetup
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+READ_ROM_WRITE_RAM1
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lda zpMachineStatus
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sta MachineStatus ; save machine status in LC RAM
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sta MachineStatus ; save machine status
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; requires RAM1 write
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and #IS_IIGS
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beq @NotGSOS
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!cpu 65816
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@ -358,33 +373,39 @@ OneTimeSetup
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jsr PrepareGSOS
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@NotGSOS
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; initialize ProDOS shim
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+READ_RAM2_WRITE_RAM2
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ldy #$0b
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CopyDevs
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lda $BF13,y
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sta promote + $13,y
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- lda $BF13, y
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sta promote + $13, y ; requires RAM2 write
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dey
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bpl CopyDevs
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bpl -
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; save unit in LC bank 2 while overriding !pseudopc
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lda $BF30
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sta promote + ProDOS_unit - $bf00
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; save unit in LC bank 2 while overriding !pseudopc
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sta promote + ProDOS_unit - $bf00 ; requires RAM2 write
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lda hddopendir+1 ; save current directory as 'root'
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ldy hddopendir+3
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sta gRootDirectory+1
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sty gRootDirectory+3
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jsr SwitchToBank1
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; save current directory as 'root'
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lda hddopendir+1 ; requires RAM2 read
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ldy hddopendir+3 ; requires RAM2 read
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sta gRootDirectory+1 ; requires RAM2 write
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sty gRootDirectory+3 ; requires RAM2 write
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jsr LoadFile ; load preferences file into $8000
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; load raw preferences file into $8000
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+READ_RAM1_WRITE_RAM1
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jsr LoadFile ; requires RAM1 read
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; exits with RAM1 read/write
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!word kRootDirectory
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!word kGlobalPrefsFilename
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- !word $8000
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jsr ParseKeyValueList ; parse contents into OKVS data structure into LC RAM bank
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; parse raw preferences file into OKVS data structure
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jsr ParseKeyValueList ; requires RAM1 write because that's where gGlobalPrefsStore is
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!word gGlobalPrefsStore
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!word -
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!byte 16
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jsr pref_get ; see if cheats are enabled by default
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; see if cheats are enabled by default
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jsr pref_get ; requires RAM1 read
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; sets PTR -> cheat pref value as length-prefixed string '1' or '0'
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!word kCheat
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!word 0
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@ -394,8 +415,9 @@ CopyDevs
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asl
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asl
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asl ; A = #$08 or #$00
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ora MachineStatus
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ora MachineStatus ; requires RAM1 read
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sta MachineStatus ; set bit 3 of MachineStatus
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; requires RAM1 write
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rol
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rol
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@ -405,9 +427,10 @@ CopyDevs
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tax ; X in (0,2,4,6)
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ldy kGameCounts, x
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sty GameCount ; store total game count based on based on (has-joystick) X (has-128K)
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; requires RAM1 write
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sty SAVE
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ldy kGameCounts+1, x
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sty GameCount+1
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sty GameCount+1 ; requires RAM1 write
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sty SAVE+1
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lsr
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tax ; X in (0,1,2,3)
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@ -422,10 +445,10 @@ CopyDevs
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ldy #5
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@searchIndexSrc
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lda $FDFD, y ; SMC
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sta kSearchIndexRecord, y
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sta kSearchIndexRecord, y ; requires RAM1 write
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@searchCacheSrc
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lda $FDFD, y
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sta kSearchCacheRecord, y
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sta kSearchCacheRecord, y ; requires RAM1 write
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dey
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bpl @searchIndexSrc
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@ -453,13 +476,13 @@ CopyDevs
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sta SAVE
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pla
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ora #$30
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sta VisibleGameCount,y
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sta VisibleGameCount,y ; requires RAM1 write
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iny
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cpy #$03
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bcc @outer
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bit CLEARKBD
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jmp Reenter
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jmp Reenter ; requires RAM1 or RAM2 read
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@kPowersOfTen
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!byte 100
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@ -197,7 +197,8 @@ iBuildHGRSparseBitmasks2Bit = iHGRPrecomputed1Bit-3
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iBuildDHGRSparseBitmasks2Bit = iBuildHGRSparseBitmasks2Bit-3
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iReverseCoordinates2Bit = iBuildDHGRSparseBitmasks2Bit-3
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iRippleCoordinates2Bit = iReverseCoordinates2Bit-3
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iSetupPrecomputed3Bit = iRippleCoordinates2Bit-3
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iHGRPrecomputed2Bit = iRippleCoordinates2Bit-3
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iSetupPrecomputed3Bit = iHGRPrecomputed2Bit-3
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iReverseCoordinates3Bit = iSetupPrecomputed3Bit-3
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iRippleCoordinates3Bit = iReverseCoordinates3Bit-3
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122
src/fx.lib.a
122
src/fx.lib.a
@ -30,6 +30,7 @@
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; - BuildDHGRSparseBitmasks2Bit
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; - ReverseCoordinates2Bit
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; - RippleCoordinates2Bit
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; - HGRPrecomputed2Bit
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; - SetupPrecomputed3Bit
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; - ReverseCoordinates3Bit
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@ -428,70 +429,70 @@ HGRPrecomputed1Bit
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jsr BuildHGRMirrorTables
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jsr BuildHGRMirrorCols
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jsr BuildHGRSparseBitmasks1Bit
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+COPY_TO_0 start, end
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jmp InputLoop
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start
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+COPY_TO_0 .start, .end
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jmp .InputLoop
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.start
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!pseudopc 0 {
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Exit1Bit rts
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InputLoop
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.Exit1Bit rts
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.InputLoop
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ldy #0
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input=*+1
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.input=*+1
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ldx Coordinates1Bit ; first value: HGR row (only 0..95 will be in input array)
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bmi Exit1Bit ; if > 127 then we're done
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+ROW_X_TO_BASE_ADDRESSES
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+ROW_X_TO_MIRROR_ADDRESSES
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bmi .Exit1Bit ; if > 127 then we're done
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+ROW_X_TO_BASE_ADDRESSES .src1, .src2, .dest1, .dest2
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+ROW_X_TO_MIRROR_ADDRESSES .mirror_src1, .mirror_src2, .mirror_dest1, .mirror_dest2
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inc input
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lda (input), y
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+HIGH_3_LOW_5 input
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inc .input
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lda (.input), y
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+HIGH_3_LOW_5 .input
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; main 1x2 block in top-left quadrant
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src1=*+1
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.src1=*+1
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lda $FDFD, y
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eor (<dest1), y
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eor (<.dest1), y
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and copymasks1bit, x
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eor (<dest1), y
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dest1=*+1
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eor (<.dest1), y
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.dest1=*+1
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sta $FDFD, y
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src2=*+1
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.src2=*+1
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lda $FDFD, y
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eor (<dest2), y
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eor (<.dest2), y
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and copymasks1bit, x
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eor (<dest2), y
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dest2=*+1
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eor (<.dest2), y
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.dest2=*+1
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sta $FDFD, y
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; corresponding 1x2 block in top-right quadrant (same row, opposite column)
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lda mirror_cols, y
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tay
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+COPY_BIT src1, dest1, mirror_copymasks1bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks1bit
|
||||
+COPY_BIT .src1, .dest1, mirror_copymasks1bit
|
||||
+COPY_BIT .src2, .dest2, mirror_copymasks1bit
|
||||
|
||||
; corresponding 1x2 block in bottom-right quadrant (opposite row, opposite column)
|
||||
mirror_src1=*+1
|
||||
.mirror_src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<mirror_dest1), y
|
||||
eor (<.mirror_dest1), y
|
||||
and mirror_copymasks1bit, x
|
||||
eor (<mirror_dest1), y
|
||||
mirror_dest1=*+1
|
||||
eor (<.mirror_dest1), y
|
||||
.mirror_dest1=*+1
|
||||
sta $FDFD, y
|
||||
mirror_src2=*+1
|
||||
.mirror_src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<mirror_dest2), y
|
||||
eor (<.mirror_dest2), y
|
||||
and mirror_copymasks1bit, x
|
||||
eor (<mirror_dest2), y
|
||||
mirror_dest2=*+1
|
||||
eor (<.mirror_dest2), y
|
||||
.mirror_dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 1x2 block in bottom-left quadrant (opposite row, original column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT mirror_src1, mirror_dest1, copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, copymasks1bit
|
||||
+COPY_BIT .mirror_src1, .mirror_dest1, copymasks1bit
|
||||
+COPY_BIT .mirror_src2, .mirror_dest2, copymasks1bit
|
||||
|
||||
+INC_INPUT_AND_LOOP InputLoop
|
||||
+INC_INPUT_AND_LOOP .input, .InputLoop
|
||||
}
|
||||
end
|
||||
.end
|
||||
}
|
||||
|
||||
BuildHGRSparseBitmasks2Bit
|
||||
@ -737,6 +738,59 @@ RippleCoordinates2Bit
|
||||
!word 2194, 6582
|
||||
@zerotbl !byte $f0, $f2, $ca, $d2, $d8, $e0, $e2, $e6, $ea, $ee
|
||||
|
||||
!zone {
|
||||
HGRPrecomputed2Bit
|
||||
jsr BuildHGRTables
|
||||
jsr BuildHGRMirrorCols
|
||||
jsr BuildHGRSparseBitmasks2Bit
|
||||
+COPY_TO_0 .start, .end
|
||||
jmp .InputLoop
|
||||
.start
|
||||
!pseudopc 0 {
|
||||
.Exit2Bit rts
|
||||
.InputLoop
|
||||
ldy #0
|
||||
.input=*+1
|
||||
ldx Coordinates2Bit ; first value: HGR row + 1
|
||||
beq .Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES .src1, .src2, .dest1, .dest2
|
||||
|
||||
inc <.input
|
||||
lda (<.input), y
|
||||
+HIGH_3_LOW_5 .input
|
||||
|
||||
; main 2x2 block in left half
|
||||
.src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<.dest1), y
|
||||
and copymasks2bit, x
|
||||
eor (<.dest1), y
|
||||
.dest1=*+1
|
||||
sta $FDFD, y
|
||||
.src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<.dest2), y
|
||||
and copymasks2bit, x
|
||||
eor (<.dest2), y
|
||||
.dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 2x2 block in right half (same row, opposite column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT .src1, .dest1, mirror_copymasks2bit
|
||||
+COPY_BIT .src2, .dest2, mirror_copymasks2bit
|
||||
|
||||
inc <.input
|
||||
bne .InputLoop
|
||||
bit KBD
|
||||
bmi .Exit2Bit
|
||||
inc <.input+1
|
||||
bne .InputLoop ; always branches
|
||||
}
|
||||
.end
|
||||
}
|
||||
|
||||
SetupPrecomputed3Bit
|
||||
; build regular HGR lookup tables, then split them
|
||||
jsr BuildHGRTables
|
||||
|
@ -51,7 +51,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -67,7 +67,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -77,7 +77,7 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -93,7 +93,7 @@ LoopTL ; top-left quadrant
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -103,7 +103,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -121,7 +121,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -131,7 +131,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -149,7 +149,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -44,8 +44,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -83,8 +83,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -19,8 +19,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
inc input
|
||||
lda (input), y
|
||||
@ -90,7 +90,7 @@ y=*+1
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
|
||||
+INC_INPUT_AND_LOOP InputLoop
|
||||
+INC_INPUT_AND_LOOP input, InputLoop
|
||||
}
|
||||
end
|
||||
}
|
||||
@ -147,8 +147,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
iny
|
||||
lda (input), y
|
||||
|
@ -18,7 +18,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
inc <input
|
||||
lda (<input), y
|
||||
@ -131,7 +131,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -34,7 +34,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -50,7 +50,7 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -60,7 +60,7 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -76,7 +76,7 @@ LoopTL ; top-left quadrant
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -86,7 +86,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -104,7 +104,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -114,7 +114,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -132,7 +132,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
bcs -
|
||||
+ sta $C002
|
||||
sta $C004
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -29,8 +29,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -68,8 +68,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -37,8 +37,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -76,8 +76,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUBBLES.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "BUTTERFLY.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "CORNER4.DATA"
|
||||
|
@ -50,13 +50,13 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT_DITHER mirror_src1, mirror_dest1, copymasks1bit, oddrow_ptr
|
||||
+COPY_BIT_DITHER mirror_src2, mirror_dest2, copymasks1bit, evenrow_ptr
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -66,13 +66,13 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT_DITHER src1, dest1, copymasks1bit, evenrow_ptr
|
||||
+COPY_BIT_DITHER src2, dest2, copymasks1bit, oddrow_ptr
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -82,7 +82,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -90,7 +90,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
tay
|
||||
+COPY_BIT_DITHER src1, dest1, mirror_copymasks1bit, evenrow_ptr
|
||||
+COPY_BIT_DITHER src2, dest2, mirror_copymasks1bit, oddrow_ptr
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -100,7 +100,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -108,7 +108,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
tay
|
||||
+COPY_BIT_DITHER mirror_src1, mirror_dest1, mirror_copymasks1bit, oddrow_ptr
|
||||
+COPY_BIT_DITHER mirror_src2, mirror_dest2, mirror_copymasks1bit, evenrow_ptr
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -43,8 +43,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -62,8 +62,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "HEART.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "MAPLE.DATA"
|
||||
|
@ -90,8 +90,8 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row (only 0..95 will be in input array)
|
||||
bmi Exit1Bit ; if > 127 then we're done
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -20,24 +20,6 @@
|
||||
|
||||
!source "src/fx/macros.a"
|
||||
|
||||
!macro ROW_X_TO_2BIT_BASE_ADDRESSES {
|
||||
; X = $01..$C0, mapping to row 0..191
|
||||
lda hgrlo-1, x
|
||||
sta <dest1
|
||||
sta <src1
|
||||
lda hgr1hi-1, x
|
||||
sta <dest1+1
|
||||
eor #$60
|
||||
sta <src1+1
|
||||
lda hgrlo, x
|
||||
sta <dest2
|
||||
sta <src2
|
||||
lda hgr1hi, x
|
||||
sta <dest2+1
|
||||
eor #$60
|
||||
sta <src2+1
|
||||
}
|
||||
|
||||
!macro FX_INITONCE_2BIT .CoordinatesFile, .Start {
|
||||
InitOnce
|
||||
bit .Start
|
||||
@ -52,58 +34,6 @@ InitOnce
|
||||
sta EndCoordinates2Bit
|
||||
}
|
||||
|
||||
!macro FX_PRECOMPUTED_2BIT .coords {
|
||||
jsr iBuildHGRTables
|
||||
jsr iBuildHGRMirrorCols
|
||||
jsr iBuildHGRSparseBitmasks2Bit
|
||||
+COPY_TO_0 start, end
|
||||
jmp InputLoop
|
||||
start
|
||||
!pseudopc 0 {
|
||||
Exit2Bit rts
|
||||
InputLoop
|
||||
ldy #0
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
|
||||
inc <input
|
||||
lda (<input), y
|
||||
+HIGH_3_LOW_5 input
|
||||
|
||||
; main 2x2 block in left half
|
||||
src1=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest1), y
|
||||
and copymasks2bit, x
|
||||
eor (<dest1), y
|
||||
dest1=*+1
|
||||
sta $FDFD, y
|
||||
src2=*+1
|
||||
lda $FDFD, y
|
||||
eor (<dest2), y
|
||||
and copymasks2bit, x
|
||||
eor (<dest2), y
|
||||
dest2=*+1
|
||||
sta $FDFD, y
|
||||
|
||||
; corresponding 2x2 block in right half (same row, opposite column)
|
||||
lda mirror_cols, y
|
||||
tay
|
||||
+COPY_BIT src1, dest1, mirror_copymasks2bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks2bit
|
||||
|
||||
inc <input
|
||||
bne InputLoop
|
||||
bit KBD
|
||||
bmi Exit2Bit
|
||||
inc <input+1
|
||||
bne InputLoop ; always branches
|
||||
}
|
||||
end
|
||||
}
|
||||
|
||||
!macro FX_PRECOMPUTED_2BIT_DITHER .coords, .endcoords {
|
||||
jsr iBuildHGRDitherMasks
|
||||
jsr iBuildHGRTables
|
||||
@ -158,7 +88,7 @@ InputLoop
|
||||
input=*+1
|
||||
ldx .coords ; first value: HGR row + 1
|
||||
beq Exit2Bit ; if 0 then we're done
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES
|
||||
+ROW_X_TO_2BIT_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
|
||||
iny
|
||||
lda (<input), y
|
||||
|
@ -34,13 +34,13 @@ LoopBL ; bottom-left quadrant (opposite row, origi
|
||||
lda (input),y
|
||||
bmi DoneBL
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT mirror_src1, mirror_dest1, copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, copymasks1bit
|
||||
+DEC_INPUT_AND_LOOP LoopBL
|
||||
+DEC_INPUT_AND_LOOP input, LoopBL
|
||||
DoneBL
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -50,13 +50,13 @@ LoopTL ; top-left quadrant
|
||||
lda (input),y
|
||||
bmi DoneTL
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
+COPY_BIT src1, dest1, copymasks1bit
|
||||
+COPY_BIT src2, dest2, copymasks1bit
|
||||
+INC_INPUT_AND_LOOP LoopTL
|
||||
+INC_INPUT_AND_LOOP input, LoopTL
|
||||
DoneTL
|
||||
|
||||
+LDADDR EndCoordinates1Bit-2
|
||||
@ -66,7 +66,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
lda (input),y
|
||||
bmi DoneTR
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
iny
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -74,7 +74,7 @@ LoopTR ; top-right quadrant (same row, opposite co
|
||||
tay
|
||||
+COPY_BIT src1, dest1, mirror_copymasks1bit
|
||||
+COPY_BIT src2, dest2, mirror_copymasks1bit
|
||||
+DEC_INPUT_AND_LOOP LoopTR
|
||||
+DEC_INPUT_AND_LOOP input, LoopTR
|
||||
DoneTR
|
||||
|
||||
+LDADDR Coordinates1Bit
|
||||
@ -84,7 +84,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
lda (input),y
|
||||
bmi DoneBR
|
||||
tax
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -92,7 +92,7 @@ LoopBR ; bottom-right quadrant (opposite row, oppo
|
||||
tay
|
||||
+COPY_BIT mirror_src1, mirror_dest1, mirror_copymasks1bit
|
||||
+COPY_BIT mirror_src2, mirror_dest2, mirror_copymasks1bit
|
||||
+INC_INPUT_AND_LOOP LoopBR
|
||||
+INC_INPUT_AND_LOOP input, LoopBR
|
||||
DoneBR
|
||||
rts
|
||||
|
||||
|
@ -28,8 +28,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -47,8 +47,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -35,8 +35,8 @@ Loop ldy #0
|
||||
lda (input),y
|
||||
bmi Exit
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
inc input
|
||||
lda (input),y
|
||||
+HIGH_3_LOW_5 input
|
||||
@ -54,8 +54,8 @@ Loop ldy #0
|
||||
ldy #0
|
||||
lda (reverse_input),y
|
||||
tax
|
||||
+ROW_X_TO_BASE_ADDRESSES
|
||||
+ROW_X_TO_MIRROR_ADDRESSES
|
||||
+ROW_X_TO_BASE_ADDRESSES src1, src2, dest1, dest2
|
||||
+ROW_X_TO_MIRROR_ADDRESSES mirror_src1, mirror_src2, mirror_dest1, mirror_dest2
|
||||
iny
|
||||
lda (reverse_input),y
|
||||
+HIGH_3_LOW_5 reverse_input
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SLOW.STAR.DATA"
|
||||
|
@ -7,7 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.1bit.a"
|
||||
|
||||
+FX_INITONCE_1BIT CoordinatesFile, iHGRPrecomputed1Bit
|
||||
+FX_INITONCE_1BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed1Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SNOWFLAKE.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SOFT.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "SOFT.IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -1,5 +1,5 @@
|
||||
;license:MIT
|
||||
;(c) 2019 by 4am
|
||||
;(c) 2019-2024 by 4am/qkumba
|
||||
;
|
||||
!cpu 6502
|
||||
!to "build/FX.INDEXED/STAR.BLOOM",plain
|
||||
@ -7,11 +7,9 @@
|
||||
|
||||
!source "src/fx/fx.hgr.precomputed.2bit.a"
|
||||
|
||||
+FX_PRECOMPUTED_2BIT Coordinates
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
!if * and 1 {
|
||||
!byte 0
|
||||
}
|
||||
Coordinates
|
||||
!source "src/fx/fx.hgr.star.bloom.data.a"
|
||||
!byte $00
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.BLOOM.DATA"
|
||||
|
@ -1,3 +1,6 @@
|
||||
!cpu 6502
|
||||
!to "build/FX/STAR.BLOOM.DATA",plain
|
||||
*=$8100
|
||||
!byte $A5,%01000000
|
||||
!byte $01,%00100010
|
||||
!byte $B3,%00100010
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "STAR7.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -9,7 +9,7 @@
|
||||
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iReverseCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "WAVY.IRIS.DATA"
|
||||
|
@ -10,7 +10,7 @@
|
||||
+FX_INITONCE_2BIT CoordinatesFile, Start
|
||||
jsr iRippleCoordinates2Bit
|
||||
Start
|
||||
+FX_PRECOMPUTED_2BIT Coordinates2Bit
|
||||
jmp iHGRPrecomputed2Bit
|
||||
|
||||
CoordinatesFile
|
||||
+PSTRING "W.IR.BLOOM.DATA"
|
||||
|
@ -67,38 +67,56 @@
|
||||
sta CopyMaskAddr+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_BASE_ADDRESSES {
|
||||
!macro ROW_X_TO_BASE_ADDRESSES .src1, .src2, .dest1, .dest2 {
|
||||
lda hgrlo, x
|
||||
sta <dest1
|
||||
sta <src1
|
||||
sta <.dest1
|
||||
sta <.src1
|
||||
lda hgr1hi, x
|
||||
sta <dest1+1
|
||||
sta <.dest1+1
|
||||
eor #$60
|
||||
sta <src1+1
|
||||
sta <.src1+1
|
||||
lda hgrlo+1, x
|
||||
sta <dest2
|
||||
sta <src2
|
||||
sta <.dest2
|
||||
sta <.src2
|
||||
lda hgr1hi+1, x
|
||||
sta <dest2+1
|
||||
sta <.dest2+1
|
||||
eor #$60
|
||||
sta <src2+1
|
||||
sta <.src2+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_MIRROR_ADDRESSES {
|
||||
!macro ROW_X_TO_MIRROR_ADDRESSES .mirror_src1, .mirror_src2, .mirror_dest1, .mirror_dest2 {
|
||||
lda hgrlomirror, x
|
||||
sta <mirror_dest1
|
||||
sta <mirror_src1
|
||||
sta <.mirror_dest1
|
||||
sta <.mirror_src1
|
||||
lda hgr1himirror, x
|
||||
sta <mirror_dest1+1
|
||||
sta <.mirror_dest1+1
|
||||
eor #$60
|
||||
sta <mirror_src1+1
|
||||
sta <.mirror_src1+1
|
||||
lda hgrlomirror+1, x
|
||||
sta <mirror_dest2
|
||||
sta <mirror_src2
|
||||
sta <.mirror_dest2
|
||||
sta <.mirror_src2
|
||||
lda hgr1himirror+1, x
|
||||
sta <mirror_dest2+1
|
||||
sta <.mirror_dest2+1
|
||||
eor #$60
|
||||
sta <mirror_src2+1
|
||||
sta <.mirror_src2+1
|
||||
}
|
||||
|
||||
!macro ROW_X_TO_2BIT_BASE_ADDRESSES .src1, .src2, .dest1, .dest2 {
|
||||
; X = $01..$C0, mapping to row 0..191
|
||||
lda hgrlo-1, x
|
||||
sta <.dest1
|
||||
sta <.src1
|
||||
lda hgr1hi-1, x
|
||||
sta <.dest1+1
|
||||
eor #$60
|
||||
sta <.src1+1
|
||||
lda hgrlo, x
|
||||
sta <.dest2
|
||||
sta <.src2
|
||||
lda hgr1hi, x
|
||||
sta <.dest2+1
|
||||
eor #$60
|
||||
sta <.src2+1
|
||||
}
|
||||
|
||||
!macro HGR_CALC_ROUTINES {
|
||||
|
@ -53,25 +53,25 @@
|
||||
bne -
|
||||
}
|
||||
|
||||
!macro INC_INPUT_AND_LOOP .loop {
|
||||
inc <input
|
||||
!macro INC_INPUT_AND_LOOP .input, .loop {
|
||||
inc <.input
|
||||
beq +
|
||||
jmp .loop
|
||||
+ bit KBD
|
||||
bmi +
|
||||
inc <input+1
|
||||
inc <.input+1
|
||||
jmp .loop
|
||||
+ rts
|
||||
}
|
||||
|
||||
!macro DEC_INPUT_AND_LOOP .loop {
|
||||
lda input
|
||||
!macro DEC_INPUT_AND_LOOP .input, .loop {
|
||||
lda .input
|
||||
php
|
||||
dec input
|
||||
dec input
|
||||
dec .input
|
||||
dec .input
|
||||
plp
|
||||
bne +
|
||||
dec input+1
|
||||
dec .input+1
|
||||
bit KBD
|
||||
bpl .loop
|
||||
bmi ++
|
||||
|
@ -142,7 +142,7 @@ zc_enable = $C05B
|
||||
iobase = $C000 ; easily confused with kbd
|
||||
|
||||
BuildAcceleratorFunction
|
||||
; in: none
|
||||
; in: ROM banked in for reading
|
||||
; out: A/Y points to lo/hi address of code block
|
||||
; X contains length of code block
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
; HasJoystick
|
||||
; Checks whether computer has joystick connected
|
||||
;
|
||||
; in: none
|
||||
; in: ROM banked in for reading
|
||||
; out: C set if joystick found
|
||||
; C clear if no joystick found
|
||||
; other flags clobbered
|
||||
@ -16,14 +16,14 @@
|
||||
; Fastchip firmware 0.4b-compatibility fix by Frank M. (0.5b seems unaffected)
|
||||
;------------------------------------------------------------------------------
|
||||
HasJoystick
|
||||
lda $FBB3
|
||||
lda ROM_MACHINEID ; requires ROM read
|
||||
cmp #$06
|
||||
bne ++
|
||||
lda $FBC0
|
||||
cmp #$E0
|
||||
beq + ; test for Fastchip on enhanced //e
|
||||
beq + ; test for Fastchip on enhanced //e
|
||||
cmp #$EA
|
||||
beq + ; test for Fastchip on non-enhanced //e
|
||||
beq + ; test for Fastchip on non-enhanced //e
|
||||
jmp ++
|
||||
|
||||
+ ; FASTChip
|
||||
@ -31,12 +31,12 @@ fc_lock = $C06A
|
||||
fc_enable = $C06B
|
||||
fc_config = $C06E
|
||||
fc_data = $C06F
|
||||
FC_UNLOCK = $6A ; write 4 times
|
||||
FC_UNLOCK = $6A ; write 4 times
|
||||
FC_LOCK = $A6
|
||||
FC_SPKR = 2 ; speaker delay register
|
||||
FC_HIFI = 4 ; set to 'HIFI'
|
||||
FC_JOY = 3 ; joystick delay register
|
||||
FC_LONG = 2 ; set to 'LONG'
|
||||
FC_SPKR = 2 ; speaker delay register
|
||||
FC_HIFI = 4 ; set to 'HIFI'
|
||||
FC_JOY = 3 ; joystick delay register
|
||||
FC_LONG = 2 ; set to 'LONG'
|
||||
|
||||
lda #FC_UNLOCK
|
||||
sta fc_lock
|
||||
|
@ -17,6 +17,7 @@
|
||||
; (this will be called before the speech detection routine, and
|
||||
; (zp$81 will contain the slot in form $Cx)
|
||||
; /!\ ALL ACCELERATORS MUST BE OFF OR SET TO 1 MHZ
|
||||
; ROM must be banked in for reading
|
||||
; out: if card was found, X = #$?n where n is the slot number of the card, otherwise #$00
|
||||
; and bit 5 = 0 if Mockingboard Sound I found
|
||||
; or bit 5 = 1 if Mockingboard Sound II or "A"-"D" found
|
||||
@ -25,6 +26,7 @@
|
||||
; flags clobbered
|
||||
; zp $80-$82 clobbered
|
||||
; A/Y clobbered
|
||||
; ROM banked in, no write
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
MAGIC_Z80_LOCATION=$FFD
|
||||
|
@ -15,6 +15,7 @@ ROMID_IIECARD = 2
|
||||
idroutine = $FE1F ; SEC, JSR $FE1F, BCS notgs
|
||||
|
||||
BuildVBLFunction
|
||||
; in: ROM must be banked in for reading
|
||||
ldx romid
|
||||
cpx #ROMID_IIECOMPAT
|
||||
bne @build_none ; not a //e
|
||||
@ -22,7 +23,7 @@ BuildVBLFunction
|
||||
beq @build_iic ; //c family
|
||||
lda romid_mac
|
||||
cmp #ROMID_IIECARD
|
||||
beq @build_iiecard ; Mac Apple IIe card
|
||||
beq @build_iiecard ; Mac Apple IIe card
|
||||
sec
|
||||
jsr idroutine ; check for IIgs
|
||||
bcs @NotGS
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906588
|
||||
!be24 15903445
|
||||
!le16 5130
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15851268
|
||||
!be24 15848103
|
||||
!le16 5732
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15783035
|
||||
!be24 15779870
|
||||
!le16 4194
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15797749
|
||||
!be24 15794584
|
||||
!le16 4652
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15816464
|
||||
!be24 15813299
|
||||
!le16 5621
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15837505
|
||||
!be24 15834340
|
||||
!le16 6199
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15911718
|
||||
!be24 15908575
|
||||
!le16 410
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912472
|
||||
!be24 15909329
|
||||
!le16 449
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912921
|
||||
!be24 15909778
|
||||
!le16 303
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 12679253
|
||||
!be24 12676088
|
||||
!le16 1652
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15859640
|
||||
!be24 15856475
|
||||
!le16 1640
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912204
|
||||
!be24 15909061
|
||||
!le16 67
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906529
|
||||
!be24 15903386
|
||||
!le16 59
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904949
|
||||
!be24 15901806
|
||||
!le16 1426
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15889715
|
||||
!be24 15886572
|
||||
!le16 557
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15857000
|
||||
!be24 15853835
|
||||
!le16 2640
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15861638
|
||||
!le16 451
|
||||
!be24 15858473
|
||||
!le16 473
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15862089
|
||||
!be24 15858946
|
||||
!le16 7564
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912128
|
||||
!be24 15908985
|
||||
!le16 76
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15906375
|
||||
!be24 15903232
|
||||
!le16 154
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15912271
|
||||
!be24 15909128
|
||||
!le16 201
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15890272
|
||||
!be24 15887129
|
||||
!le16 4334
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15894606
|
||||
!be24 15891463
|
||||
!le16 1733
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15896339
|
||||
!be24 15893196
|
||||
!le16 1181
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15897520
|
||||
!be24 15894377
|
||||
!le16 3394
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15900914
|
||||
!be24 15897771
|
||||
!le16 3429
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904343
|
||||
!be24 15901200
|
||||
!le16 479
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15904822
|
||||
!be24 15901679
|
||||
!le16 127
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15913224
|
||||
!be24 15910081
|
||||
!le16 2370
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15875058
|
||||
!be24 15871915
|
||||
!le16 5083
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15880141
|
||||
!be24 15876998
|
||||
!le16 2485
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15843704
|
||||
!be24 15840539
|
||||
!le16 7564
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15773452
|
||||
!be24 15770287
|
||||
!le16 9583
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15787229
|
||||
!be24 15784064
|
||||
!le16 10520
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15802401
|
||||
!be24 15799236
|
||||
!le16 14063
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15822085
|
||||
!be24 15818920
|
||||
!le16 15420
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15861280
|
||||
!be24 15858115
|
||||
!le16 358
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15869653
|
||||
!be24 15866510
|
||||
!le16 5405
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15882626
|
||||
!be24 15879483
|
||||
!le16 7089
|
||||
|
@ -4,5 +4,5 @@
|
||||
; This file is automatically generated
|
||||
;
|
||||
!byte 0
|
||||
!be24 15769104
|
||||
!be24 15765939
|
||||
!le16 4348
|
||||
|
Loading…
Reference in New Issue
Block a user