mirror of https://github.com/a2-4am/4cade.git
285 lines
8.8 KiB
Plaintext
285 lines
8.8 KiB
Plaintext
;license:MIT
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;(c) 2019-2022 by Andrew Roughan, qkumba, 4am, Tom Charlesworth, Rob Justice
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;
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; Mockingboard support functions
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;
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;------------------------------------------------------------------------------
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; GetMockingboardStuff
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; detect Mockingboard card by searching for 6522 timers across all slots 7->1
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; access 6522 timers with deterministic cycle counts
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;
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; based on prior art in Mockingboard Developers Toolkit
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; with optimisation from deater/french touch
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; also takes into account FastChip //e clock difference
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;
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; in: A/Y contains address of callback to call if card was found
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; (this will be called before the speech detection routine, and
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; (zp$81 will contain the slot in form $Cx)
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; /!\ ALL ACCELERATORS MUST BE OFF OR SET TO 1 MHZ
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; out: if card was found, X = #$?n where n is the slot number of the card, otherwise #$00
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; and bit 5 = 0 if Mockingboard Sound I found
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; or bit 5 = 1 if Mockingboard Sound II or "A"-"D" found
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; and bit 6 = 1 if SSI-263 speech chip found
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; or bit 7 = 1 if SC-01 speech chip found
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; flags clobbered
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; zp $80-$82 clobbered
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; A/Y clobbered
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;------------------------------------------------------------------------------
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MAGIC_Z80_LOCATION=$FFD
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GetMockingboardStuff
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+ST16 @callback+1
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lda ROM_MACHINEID
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cmp #$06
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bne @not_iic
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ldx ROM_MACHINE2C
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bne @not_iic
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; from mgcaret
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; https://github.com/a2-4am/4cade/issues/483
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; the Mockingboard init can accidentally enable the Softcard Z80
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; and can crash the machine
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; solved by loading a small Z80 routine at $0FFD (FFFDh in the Z80 space):
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; $32 $00 $E4 $C3 FD FF which is
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; NOP
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; LD (E400h),A ; card is at $E400 due to memory translation
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; JP FFFDh
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; returns the system to 6502 mode and leaves it in the same state as the Z80 after RESET:
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; ready to execute the instruction at 0000h (from the Z80 perspective)
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ldx #5
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- lda magic_z80_bytes, x
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sta MAGIC_Z80_LOCATION, x
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dex
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bpl -
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stx $C403 ; enable Mockingboard 4C support
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stx $C404
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@not_iic
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lda #$00
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sta $80
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sta $82 ; type
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ldx #$C1
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@slotLoop
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stx $81
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ldy #$04 ; 6522 #1 $Cx04
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jsr @timercheck
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bcc @foundI
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@nextSlot
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inx
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cpx #$C8
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bne @slotLoop
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ldx #$00 ; not found
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rts
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@foundI ; sound I or better
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jsr @callback
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ldy #$84 ; 6522 #2 $Cx84
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jsr @timercheck
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bcc @foundII
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ldy #$0c
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sty @mb_smc1 + 1
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iny
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sty @mb_smc10 + 1
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iny
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sty @mb_smc5 + 1
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sty @mb_smc14 + 1
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clc
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+HIDE_NEXT_BYTE
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@foundII ;stereo
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sec
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ror $82
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lda $81
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sta @mb_smc1 + 2
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sta @mb_smc2 + 2
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sta @mb_smc3 + 2
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sta @mb_smc4 + 2
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sta @mb_smc5 + 2
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sta @mb_smc6 + 2
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sta @mb_smc7 + 2
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sta @mb_smc8 + 2
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sta @mb_smc9 + 2
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sta @mb_smc10 + 2
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sta @mb_smc11 + 2
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sta @mb_smc12 + 2
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sta @mb_smc13 + 2
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sta @mb_smc14 + 2
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sta @mb_smc15 + 2
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sta @mb_smc17 + 2
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sta @mb_smc18 + 2
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sta @mb_smc19 + 2
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sta @mb_smc20 + 2
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sta @mb_smc21 + 2
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sta @mb_smc22 + 2
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; detect speech - SSI263
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sei
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+READ_RAM2_WRITE_RAM2
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lda #$40 ; setup NMI vector (rti)
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sta $3fb
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lda #$fb
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sta $fffa
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lda #3
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sta $fffb
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lda #<@mb_irq ; setup IRQ vector
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sta $3fe
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sta $fffe
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lda #>@mb_irq
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sta $3ff
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sta $ffff
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lda #$0c ; CB2 - input neg edge, CB1 neg edge, CA2 low output, CA1 neg edge
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@mb_smc1
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sta $c48c ; peripheral control register 6522#2
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lda #$80 ; ctl=1
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@mb_smc2
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sta $c443 ; C = SSI reg 3, S/S I or A = 6522#1 ddr a
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lda #$c0 ; duration=11 phoneme=000000 (pause)
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@mb_smc3
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sta $c440 ; C = SSI reg 0, S/S I or A = 6522#1 port b data
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lda #$70 ; ctl=0 (A/R active - phoneme timing response)
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@mb_smc4
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sta $c443 ; C = SSI reg 3, S/S I or A = 6522#1 ddr a
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lda #$82 ; enable CA1 interrupt
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@mb_smc5
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sta $c48e ; interrupt enable register 6522#2
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ldx #$80 ; 0= ~650ms, 80 = ~325ms
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ldy #0
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sec
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cli
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@wait_irq
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lda $80
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bne +
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iny
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bne @wait_irq
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inx
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bne @wait_irq
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clc
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+ ror $82
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; detect speech - SC-01
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;based on S/S I demo dsk
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;init sc-01 interface
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lda #$ff
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@mb_smc15
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sta $c402 ; ddr portb - all outputs
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lda #$b0 ; cb2 pulse output,cb1 pos edge
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@mb_smc17
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sta $c40c ; pcr
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lda #$10 ; clear all interrupt flags
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@mb_smc18
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sta $c40d ; ifr
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;output stop phoneme
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lda #$3f ; stop
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@mb_smc19
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sta $c400 ; orb, write phoneme & pitch
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ldx #$D0 ; wait ~120ms, stop takes 47ms
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- lda #$10
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@mb_smc20
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bit $c40d ; ifr, check for cb1 interrupt flag
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bne + ; flag set, we found one
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iny
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bne -
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inx
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bne -
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beq @got_irq
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@mb_smc21
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+ sta $c40d ; ifr, clear flag
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lda #$00 ; turn off cb2 pulse mode to disable false writes to sc01
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@mb_smc22
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sta $c40c ; pcr
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sec ; found, we have an SC-01
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ror $82
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bne @ssI
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@got_irq
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sei
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clc ; not found
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ror $82
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ldy #$ff
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@mb_smc6
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sty $c403 ; 6522#1 ddra
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lda #7
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@mb_smc7
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sta $c402 ; 6522#1 ddrb
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iny
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sty $80
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tya
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sta ($80),y ; 6522#1 orb
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lda #4
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sta ($80),y ; 6522#1 orb
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@ssI
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ldy #$ff
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@mb_smc8
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sty $c483 ; 6522#2 ddra
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lda #7
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@mb_smc9
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sta $c482 ; 6522#2 ddrb
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lda #0
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ldy #$80
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sta ($80),y ; 6522#2 orb
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lda #4
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sta ($80),y ; 6522#2 orb
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lda #7
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and $81
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ora $82
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tax
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lda #<Ignore
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sta $fffe
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lda #>Ignore
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sta $ffff
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+READ_ROM_NO_WRITE
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rts ; found
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@timercheck
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sec
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lda ($80),y ; read 6522 timer low byte
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sbc ($80),y ; second time
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sec
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sbc #5 ; looking for 5 cycles between reads
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cmp #2 ; or 6 cycles with the FastChip //e
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rts
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@mb_irq
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lda #2 ; clear CA1 interrupt flag
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@mb_smc10
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sta $c48d ; interrupt flag register 6522#2
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lda #$80 ; ctl=1
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@mb_smc11
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sta $c443 ; C = SSI reg 3, S/S I or A = 6522#1 ddr a
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lda #0 ; duration=00 phoneme=000000 (pause)
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@mb_smc12
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sta $c440 ; C = SSI reg 0, S/S I or A = 6522#1 port b data
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lda #$70 ; ctl=0 (A/R active - phoneme timing response)
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@mb_smc13
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sta $c443 ; C = SSI reg 3, S/S I or A = 6522#1 ddr a
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sta $80 ; found
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lda #2 ; disable CA1 interrupt
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@mb_smc14
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sta $c48e ; interrupt enable register 6522#2
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lda $45
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rti
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@callback
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jmp $FDFD ; SMC
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magic_z80_bytes
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!byte $32, $00, $E4, $C3, $FD, $FF
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