2009-01-09 23:27:29 +00:00
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/*
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* z80mem.c
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*
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* Written by
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* Andreas Boose <viceteam@t-online.de>
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*
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* This file is part of VICE, the Versatile Commodore Emulator.
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* See README for copyright notice.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA.
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*
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*/
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//#include "vice.h"
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#include <stdio.h>
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#include <string.h>
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//#include "c128mem.h" // [AppleWin-TC]
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//#include "c128mmu.h"
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//#include "c64cia.h"
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//#include "c64io.h"
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//#include "cmdline.h"
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//#include "log.h"
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//#include "mem.h"
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//#include "resources.h"
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//#include "sid.h"
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//#include "sysfile.h"
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//#include "types.h"
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//#include "vdc-mem.h"
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//#include "vdc.h"
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//#include "vicii-mem.h"
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//#include "vicii.h"
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2018-02-24 15:12:40 +00:00
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#include "../CommonVICE/types.h" // [AppleWin-TC]
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2009-01-09 23:27:29 +00:00
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#include "z80mem.h"
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#include "z80.h" // [AppleWin-TC] Added for z80_RDMEM() & z80_WRMEM
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/* Z80 boot BIOS. */
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BYTE z80bios_rom[0x1000];
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/* Logging. */
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//static log_t z80mem_log = LOG_ERR; // [AppleWin-TC]
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/* Adjust this pointer when the MMU changes banks. */
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static BYTE **bank_base;
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static int *bank_limit = NULL;
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unsigned int z80_old_reg_pc;
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/* Pointers to the currently used memory read and write tables. */
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read_func_ptr_t *_z80mem_read_tab_ptr;
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store_func_ptr_t *_z80mem_write_tab_ptr;
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BYTE **_z80mem_read_base_tab_ptr;
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int *z80mem_read_limit_tab_ptr;
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#define NUM_CONFIGS 8
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/* Memory read and write tables. */
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static store_func_ptr_t mem_write_tab[NUM_CONFIGS][0x101];
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static read_func_ptr_t mem_read_tab[NUM_CONFIGS][0x101];
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static BYTE *mem_read_base_tab[NUM_CONFIGS][0x101];
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static int mem_read_limit_tab[NUM_CONFIGS][0x101];
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store_func_ptr_t io_write_tab[0x101];
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read_func_ptr_t io_read_tab[0x101];
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//static const resource_int_t resources_int[] = { // [AppleWin-TC]
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// { NULL }
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//};
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//
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//int z80mem_resources_init(void)
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//{
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// return resources_register_int(resources_int);
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//}
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//
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//static const cmdline_option_t cmdline_options[] =
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//{
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// { NULL }
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//};
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//
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//int z80mem_cmdline_options_init(void)
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//{
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// return cmdline_register_options(cmdline_options);
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//}
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/* ------------------------------------------------------------------------- */
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/* Generic memory access. */
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#if 0
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static void REGPARM2 z80mem_store(WORD addr, BYTE value)
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{
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_z80mem_write_tab_ptr[addr >> 8](addr, value);
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}
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static BYTE REGPARM1 z80mem_read(WORD addr)
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{
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return _z80mem_read_tab_ptr[addr >> 8](addr);
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}
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#endif
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BYTE REGPARM1 bios_read(WORD addr)
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{
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return z80bios_rom[addr & 0x0fff];
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}
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void REGPARM2 bios_store(WORD addr, BYTE value)
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{
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z80bios_rom[addr] = value;
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}
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//static BYTE REGPARM1 z80_read_zero(WORD addr) // [AppleWin-TC]
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//{
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// return mem_page_zero[addr];
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//}
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//
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//static void REGPARM2 z80_store_zero(WORD addr, BYTE value)
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//{
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// mem_page_zero[addr] = value;
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//}
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static BYTE REGPARM1 read_unconnected_io(WORD addr)
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{
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// log_message(z80mem_log, "Read from unconnected IO %04x", addr); // [AppleWin-TC]
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return 0;
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}
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static void REGPARM2 store_unconnected_io(WORD addr, BYTE value)
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{
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// log_message(z80mem_log, "Store to unconnected IO %04x %02x", addr, value); // [AppleWin-TC]
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}
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#ifdef _MSC_VER
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#pragma optimize("",off)
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#endif
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void z80mem_initialize(void)
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{
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int i, j;
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/* Memory addess space. */
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for (j = 0; j < NUM_CONFIGS; j++) {
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for (i = 0; i <= 0x100; i++) {
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mem_read_base_tab[j][i] = NULL;
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mem_read_limit_tab[j][i] = -1;
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mem_read_tab[j][i] = z80_RDMEM; // [AppleWin-TC]
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mem_write_tab[j][i] = z80_WRMEM; // [AppleWin-TC]
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}
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}
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_z80mem_read_tab_ptr = mem_read_tab[0];
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_z80mem_write_tab_ptr = mem_write_tab[0];
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_z80mem_read_base_tab_ptr = mem_read_base_tab[0];
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z80mem_read_limit_tab_ptr = mem_read_limit_tab[0];
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/* IO address space. */
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/* At least we know what happens. */
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for (i = 0; i <= 0x100; i++) {
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io_read_tab[i] = read_unconnected_io;
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io_write_tab[i] = store_unconnected_io;
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}
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#if 0 // [AppleWin-TC]
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int i, j;
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/* Memory addess space. */
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for (j = 0; j < NUM_CONFIGS; j++) {
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for (i = 0; i <= 0x100; i++) {
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mem_read_base_tab[j][i] = NULL;
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mem_read_limit_tab[j][i] = -1;
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}
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}
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mem_read_tab[0][0] = bios_read;
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mem_write_tab[0][0] = z80_store_zero;
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mem_read_tab[1][0] = bios_read;
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mem_write_tab[1][0] = z80_store_zero;
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mem_read_tab[2][0] = z80_read_zero;
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mem_write_tab[2][0] = z80_store_zero;
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mem_read_tab[3][0] = z80_read_zero;
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mem_write_tab[3][0] = z80_store_zero;
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mem_read_tab[4][0] = z80_read_zero;
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mem_write_tab[4][0] = z80_store_zero;
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mem_read_tab[5][0] = z80_read_zero;
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mem_write_tab[5][0] = z80_store_zero;
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mem_read_tab[6][0] = z80_read_zero;
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mem_write_tab[6][0] = z80_store_zero;
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mem_read_tab[7][0] = z80_read_zero;
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mem_write_tab[7][0] = z80_store_zero;
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mem_read_tab[0][1] = bios_read;
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mem_write_tab[0][1] = one_store;
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mem_read_tab[1][1] = bios_read;
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mem_write_tab[1][1] = one_store;
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mem_read_tab[2][1] = one_read;
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mem_write_tab[2][1] = one_store;
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mem_read_tab[3][1] = one_read;
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mem_write_tab[3][1] = one_store;
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mem_read_tab[4][1] = one_read;
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mem_write_tab[4][1] = one_store;
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mem_read_tab[5][1] = one_read;
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mem_write_tab[5][1] = one_store;
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mem_read_tab[6][1] = one_read;
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mem_write_tab[6][1] = one_store;
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mem_read_tab[7][1] = one_read;
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mem_write_tab[7][1] = one_store;
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for (i = 2; i < 0x10; i++) {
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mem_read_tab[0][i] = bios_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = bios_read;
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mem_write_tab[1][i] = ram_store;
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mem_read_tab[2][i] = lo_read;
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mem_write_tab[2][i] = lo_store;
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mem_read_tab[3][i] = lo_read;
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mem_write_tab[3][i] = lo_store;
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mem_read_tab[4][i] = ram_read;
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mem_write_tab[4][i] = ram_store;
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mem_read_tab[5][i] = ram_read;
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mem_write_tab[5][i] = ram_store;
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mem_read_tab[6][i] = lo_read;
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mem_write_tab[6][i] = lo_store;
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mem_read_tab[7][i] = lo_read;
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mem_write_tab[7][i] = lo_store;
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}
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for (i = 0x10; i <= 0x13; i++) {
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mem_read_tab[0][i] = ram_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = colorram_read;
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mem_write_tab[1][i] = colorram_store;
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mem_read_tab[2][i] = lo_read;
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mem_write_tab[2][i] = lo_store;
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mem_read_tab[3][i] = colorram_read;
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mem_write_tab[3][i] = colorram_store;
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mem_read_tab[4][i] = ram_read;
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mem_write_tab[4][i] = ram_store;
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mem_read_tab[5][i] = colorram_read;
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mem_write_tab[5][i] = colorram_store;
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mem_read_tab[6][i] = lo_read;
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mem_write_tab[6][i] = lo_store;
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mem_read_tab[7][i] = colorram_read;
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mem_write_tab[7][i] = colorram_store;
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}
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for (i = 0x14; i <= 0x3f; i++) {
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mem_read_tab[0][i] = ram_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = ram_read;
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mem_write_tab[1][i] = ram_store;
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mem_read_tab[2][i] = lo_read;
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mem_write_tab[2][i] = lo_store;
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mem_read_tab[3][i] = lo_read;
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mem_write_tab[3][i] = lo_store;
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mem_read_tab[4][i] = ram_read;
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mem_write_tab[4][i] = ram_store;
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mem_read_tab[5][i] = ram_read;
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mem_write_tab[5][i] = ram_store;
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mem_read_tab[6][i] = lo_read;
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mem_write_tab[6][i] = lo_store;
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mem_read_tab[7][i] = lo_read;
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mem_write_tab[7][i] = lo_store;
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}
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for (j = 0; j < NUM_CONFIGS; j++) {
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for (i = 0x40; i <= 0xbf; i++) {
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mem_read_tab[j][i] = ram_read;
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mem_write_tab[j][i] = ram_store;
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}
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}
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for (i = 0xc0; i <= 0xcf; i++) {
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mem_read_tab[0][i] = ram_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = ram_read;
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mem_write_tab[1][i] = ram_store;
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mem_read_tab[2][i] = top_shared_read;
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mem_write_tab[2][i] = top_shared_store;
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mem_read_tab[3][i] = top_shared_read;
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mem_write_tab[3][i] = top_shared_store;
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mem_read_tab[4][i] = ram_read;
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mem_write_tab[4][i] = ram_store;
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mem_read_tab[5][i] = ram_read;
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mem_write_tab[5][i] = ram_store;
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mem_read_tab[6][i] = top_shared_read;
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mem_write_tab[6][i] = top_shared_store;
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mem_read_tab[7][i] = top_shared_read;
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mem_write_tab[7][i] = top_shared_store;
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}
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for (i = 0xd0; i <= 0xdf; i++) {
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mem_read_tab[0][i] = ram_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = ram_read;
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mem_write_tab[1][i] = ram_store;
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mem_read_tab[2][i] = top_shared_read;
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mem_write_tab[2][i] = top_shared_store;
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mem_read_tab[3][i] = top_shared_read;
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mem_write_tab[3][i] = top_shared_store;
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mem_read_tab[4][i] = ram_read;
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mem_write_tab[4][i] = ram_store;
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mem_read_tab[5][i] = ram_read;
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mem_write_tab[5][i] = ram_store;
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mem_read_tab[6][i] = top_shared_read;
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mem_write_tab[6][i] = top_shared_store;
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mem_read_tab[7][i] = top_shared_read;
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mem_write_tab[7][i] = top_shared_store;
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}
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for (i = 0xe0; i <= 0xfe; i++) {
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mem_read_tab[0][i] = ram_read;
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mem_write_tab[0][i] = ram_store;
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mem_read_tab[1][i] = ram_read;
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mem_write_tab[1][i] = ram_store;
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mem_read_tab[2][i] = top_shared_read;
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mem_write_tab[2][i] = top_shared_store;
|
|
|
|
mem_read_tab[3][i] = top_shared_read;
|
|
|
|
mem_write_tab[3][i] = top_shared_store;
|
|
|
|
mem_read_tab[4][i] = ram_read;
|
|
|
|
mem_write_tab[4][i] = ram_store;
|
|
|
|
mem_read_tab[5][i] = ram_read;
|
|
|
|
mem_write_tab[5][i] = ram_store;
|
|
|
|
mem_read_tab[6][i] = top_shared_read;
|
|
|
|
mem_write_tab[6][i] = top_shared_store;
|
|
|
|
mem_read_tab[7][i] = top_shared_read;
|
|
|
|
mem_write_tab[7][i] = top_shared_store;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (j = 0; j < NUM_CONFIGS; j++) {
|
|
|
|
mem_read_tab[j][0xff] = mmu_ffxx_read_z80;
|
|
|
|
mem_write_tab[j][0xff] = mmu_ffxx_store;
|
|
|
|
|
|
|
|
mem_read_tab[j][0x100] = mem_read_tab[j][0x0];
|
|
|
|
mem_write_tab[j][0x100] = mem_write_tab[j][0x0];
|
|
|
|
}
|
|
|
|
|
|
|
|
_z80mem_read_tab_ptr = mem_read_tab[0];
|
|
|
|
_z80mem_write_tab_ptr = mem_write_tab[0];
|
|
|
|
_z80mem_read_base_tab_ptr = mem_read_base_tab[0];
|
|
|
|
z80mem_read_limit_tab_ptr = mem_read_limit_tab[0];
|
|
|
|
|
|
|
|
/* IO address space. */
|
|
|
|
|
|
|
|
/* At least we know what happens. */
|
|
|
|
for (i = 0; i <= 0x100; i++) {
|
|
|
|
io_read_tab[i] = read_unconnected_io;
|
|
|
|
io_write_tab[i] = store_unconnected_io;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
io_read_tab[0x10] = colorram_read;
|
|
|
|
io_write_tab[0x10] = colorram_store;
|
|
|
|
io_read_tab[0x11] = colorram_read;
|
|
|
|
io_write_tab[0x11] = colorram_store;
|
|
|
|
io_read_tab[0x12] = colorram_read;
|
|
|
|
io_write_tab[0x12] = colorram_store;
|
|
|
|
io_read_tab[0x13] = colorram_read;
|
|
|
|
io_write_tab[0x13] = colorram_store;
|
|
|
|
*/
|
|
|
|
io_read_tab[0xd0] = vicii_read;
|
|
|
|
io_write_tab[0xd0] = vicii_store;
|
|
|
|
io_read_tab[0xd1] = vicii_read;
|
|
|
|
io_write_tab[0xd1] = vicii_store;
|
|
|
|
io_read_tab[0xd2] = vicii_read;
|
|
|
|
io_write_tab[0xd2] = vicii_store;
|
|
|
|
io_read_tab[0xd3] = vicii_read;
|
|
|
|
io_write_tab[0xd3] = vicii_store;
|
|
|
|
|
|
|
|
io_read_tab[0xd4] = sid_read;
|
|
|
|
io_write_tab[0xd4] = sid_store;
|
|
|
|
|
|
|
|
io_read_tab[0xd5] = mmu_read;
|
|
|
|
io_write_tab[0xd5] = mmu_store;
|
|
|
|
|
|
|
|
io_read_tab[0xd6] = vdc_read;
|
|
|
|
io_write_tab[0xd6] = vdc_store;
|
|
|
|
io_read_tab[0xd7] = d7xx_read;
|
|
|
|
io_write_tab[0xd7] = d7xx_store;
|
|
|
|
|
|
|
|
io_read_tab[0xd8] = colorram_read;
|
|
|
|
io_write_tab[0xd8] = colorram_store;
|
|
|
|
io_read_tab[0xd9] = colorram_read;
|
|
|
|
io_write_tab[0xd9] = colorram_store;
|
|
|
|
io_read_tab[0xda] = colorram_read;
|
|
|
|
io_write_tab[0xda] = colorram_store;
|
|
|
|
io_read_tab[0xdb] = colorram_read;
|
|
|
|
io_write_tab[0xdb] = colorram_store;
|
|
|
|
|
|
|
|
io_read_tab[0xdc] = cia1_read;
|
|
|
|
io_write_tab[0xdc] = cia1_store;
|
|
|
|
io_read_tab[0xdd] = cia2_read;
|
|
|
|
io_write_tab[0xdd] = cia2_store;
|
|
|
|
|
|
|
|
io_read_tab[0xde] = c64io1_read;
|
|
|
|
io_write_tab[0xde] = c64io1_store;
|
|
|
|
io_read_tab[0xdf] = c64io2_read;
|
|
|
|
io_write_tab[0xdf] = c64io2_store;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef _MSC_VER
|
|
|
|
#pragma optimize("",on)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void z80mem_set_bank_pointer(BYTE **base, int *limit)
|
|
|
|
{
|
|
|
|
bank_base = base;
|
|
|
|
bank_limit = limit;
|
|
|
|
}
|
|
|
|
|
|
|
|
void z80mem_update_config(int config)
|
|
|
|
{
|
|
|
|
_z80mem_read_tab_ptr = mem_read_tab[config];
|
|
|
|
_z80mem_write_tab_ptr = mem_write_tab[config];
|
|
|
|
_z80mem_read_base_tab_ptr = mem_read_base_tab[config];
|
|
|
|
z80mem_read_limit_tab_ptr = mem_read_limit_tab[config];
|
|
|
|
/*
|
|
|
|
if (bank_limit != NULL) {
|
|
|
|
*bank_base = _z80mem_read_base_tab_ptr[z80_old_reg_pc >> 8];
|
|
|
|
if (*bank_base != 0)
|
|
|
|
*bank_base = _z80mem_read_base_tab_ptr[z80_old_reg_pc >> 8]
|
|
|
|
- (z80_old_reg_pc & 0xff00);
|
|
|
|
*bank_limit = z80mem_read_limit_tab_ptr[z80_old_reg_pc >> 8];
|
|
|
|
}
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
int z80mem_load(void)
|
|
|
|
{
|
|
|
|
// if (z80mem_log == LOG_ERR) // [AppleWin-TC]
|
|
|
|
// z80mem_log = log_open("Z80MEM");
|
|
|
|
|
|
|
|
z80mem_initialize();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|