mirror of
https://github.com/AppleWin/AppleWin.git
synced 2024-11-19 04:08:45 +00:00
Updated copyright year,
start cpu cleanup - move 6502 macros to cpu/
This commit is contained in:
mpohoreski
parent
ba55c09dfa
commit
0cd041d561
@ -4,7 +4,7 @@ AppleWin : An Apple //e emulator for Windows
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Copyright (C) 1994-1996, Michael O'Brien
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Copyright (C) 1999-2001, Oliver Schmidt
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Copyright (C) 2002-2005, Tom Charlesworth
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Copyright (C) 2006-2007, Tom Charlesworth, Michael Pohoreski
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Copyright (C) 2006-2010, Tom Charlesworth, Michael Pohoreski
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AppleWin is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -139,607 +139,9 @@ static volatile UINT32 g_bmIRQ = 0;
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static volatile UINT32 g_bmNMI = 0;
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static volatile BOOL g_bNmiFlank = FALSE; // Positive going flank on NMI line
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/****************************************************************************
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*
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* GENERAL PURPOSE MACROS
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*
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***/
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#include "cpu/cpu_general.inl"
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#define AF_TO_EF flagc = (regs.ps & AF_CARRY); \
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flagn = (regs.ps & AF_SIGN); \
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flagv = (regs.ps & AF_OVERFLOW); \
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flagz = (regs.ps & AF_ZERO);
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#define EF_TO_AF regs.ps = (regs.ps & ~(AF_CARRY | AF_SIGN | \
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AF_OVERFLOW | AF_ZERO)) \
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| flagc \
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| flagn \
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| (flagv ? AF_OVERFLOW : 0) \
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| (flagz ? AF_ZERO : 0) \
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| AF_RESERVED | AF_BREAK;
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// CYC(a): This can be optimised, as only certain opcodes will affect uExtraCycles
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#define CYC(a) uExecutedCycles += (a)+uExtraCycles; g_nIrqCheckTimeout -= (a)+uExtraCycles;
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#define POP (*(mem+((regs.sp >= 0x1FF) ? (regs.sp = 0x100) : ++regs.sp)))
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#define PUSH(a) *(mem+regs.sp--) = (a); \
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if (regs.sp < 0x100) \
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regs.sp = 0x1FF;
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#define READ ( \
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((addr & 0xF000) == 0xC000) \
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? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles) \
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: *(mem+addr) \
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)
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#define SETNZ(a) { \
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flagn = ((a) & 0x80); \
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flagz = !((a) & 0xFF); \
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}
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#define SETZ(a) flagz = !((a) & 0xFF);
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#define WRITE(a) { \
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memdirty[addr >> 8] = 0xFF; \
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LPBYTE page = memwrite[addr >> 8]; \
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if (page) \
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*(page+(addr & 0xFF)) = (BYTE)(a); \
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else if ((addr & 0xF000) == 0xC000) \
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IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
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}
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//
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// ExtraCycles:
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// +1 if branch taken
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// +1 if page boundary crossed
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#define BRANCH_TAKEN { \
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base = regs.pc; \
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regs.pc += addr; \
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if ((base ^ regs.pc) & 0xFF00) \
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uExtraCycles=2; \
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else \
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uExtraCycles=1; \
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}
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//
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#define CHECK_PAGE_CHANGE if (bSlowerOnPagecross) { \
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if ((base ^ addr) & 0xFF00) \
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uExtraCycles=1; \
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}
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/****************************************************************************
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*
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* ADDRESSING MODE MACROS
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*
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***/
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#define ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
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#define IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
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#define ABSX base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
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#define ABSY base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
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#define IABSCMOS base = *(LPWORD)(mem+regs.pc); \
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addr = *(LPWORD)(mem+base); \
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if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
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regs.pc += 2;
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#define IABSNMOS base = *(LPWORD)(mem+regs.pc); \
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if ((base & 0xFF) == 0xFF) \
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addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8);\
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else \
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addr = *(LPWORD)(mem+base); \
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regs.pc += 2;
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#define IMM addr = regs.pc++;
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#define INDX base = ((*(mem+regs.pc++))+regs.x) & 0xFF; \
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if (base == 0xFF) \
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addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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addr = *(LPWORD)(mem+base);
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#define INDY if (*(mem+regs.pc) == 0xFF) \
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base = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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base = *(LPWORD)(mem+*(mem+regs.pc)); \
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regs.pc++; \
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addr = base+(WORD)regs.y; \
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CHECK_PAGE_CHANGE;
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#define IZPG base = *(mem+regs.pc++); \
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if (base == 0xFF) \
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addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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addr = *(LPWORD)(mem+base);
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#define REL addr = (signed char)*(mem+regs.pc++);
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// Optimiation note:
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// . Opcodes that generate zero-page addresses can't be accessing $C000..$CFFF
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// so they could be paired with special READZP/WRITEZP macros (instead of READ/WRITE)
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#define ZPG addr = *(mem+regs.pc++);
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#define ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
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#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
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/****************************************************************************
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*
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* INSTRUCTION MACROS
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*
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***/
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#define ADC_NMOS bSlowerOnPagecross = 1; \
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temp = READ; \
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if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
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if (val > 0x09) \
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val += 0x06; \
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if (val <= 0x0F) \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0); \
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else \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0) + 0x10;\
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flagz = !((regs.a + temp + flagc) & 0xFF); \
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flagn = (val & 0x80); \
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flagv = ((regs.a ^ val) & 0x80) && !((regs.a ^ temp) & 0x80);\
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if ((val & 0x1F0) > 0x90) \
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val += 0x60; \
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flagc = ((val & 0xFF0) > 0xF0); \
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regs.a = val & 0xFF; \
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} \
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else { \
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val = regs.a + temp + flagc; \
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flagc = (val > 0xFF); \
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flagv = (((regs.a & 0x80) == (temp & 0x80)) && \
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((regs.a & 0x80) != (val & 0x80))); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a); \
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}
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#define ADC_CMOS bSlowerOnPagecross = 1; \
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temp = READ; \
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flagv = !((regs.a ^ temp) & 0x80); \
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if (regs.ps & AF_DECIMAL) { \
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uExtraCycles++; \
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val = (regs.a & 0x0f) + (temp & 0x0f) + flagc; \
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if (val >= 0x0A) \
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val = 0x10 | ((val + 6) & 0x0f); \
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val += (regs.a & 0xf0) + (temp & 0xf0); \
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if (val >= 0xA0) { \
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flagc = 1; \
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if (val >= 0x180) \
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flagv = 0; \
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val += 0x60; \
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} \
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else { \
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flagc = 0; \
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if (val < 0x80) \
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flagv = 0; \
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} \
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} \
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else { \
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val = regs.a + temp + flagc; \
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if (val >= 0x100) { \
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flagc = 1; \
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if (val >= 0x180) flagv = 0; \
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} \
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else { \
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flagc = 0; \
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if (val < 0x80) flagv = 0; \
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} \
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} \
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regs.a = val & 0xFF; \
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SETNZ(regs.a)
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#define ALR regs.a &= READ; \
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flagc = (regs.a & 1); \
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flagn = 0; \
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regs.a >>= 1; \
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SETZ(regs.a)
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#define AND bSlowerOnPagecross = 1; \
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regs.a &= READ; \
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SETNZ(regs.a)
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#define ANC regs.a &= READ; \
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SETNZ(regs.a) \
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flagc = !!flagn;
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#define ARR temp = regs.a & READ; /* Yes, this is sick */ \
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if (regs.ps & AF_DECIMAL) { \
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val = temp; \
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val |= (flagc ? 0x100 : 0); \
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val >>= 1; \
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flagn = (flagc ? 0x80 : 0); \
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SETZ(val) \
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flagv = ((val ^ temp) & 0x40); \
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if (((val & 0x0F) + (val & 0x01)) > 0x05) \
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val = (val & 0xF0) | ((val + 0x06) & 0x0F); \
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if (((val & 0xF0) + (val & 0x10)) > 0x50) { \
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val = (val & 0x0F) | ((val + 0x60) & 0xF0); \
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flagc = 1; \
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} \
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else \
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flagc = 0; \
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regs.a = (val & 0xFF); \
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} \
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else { \
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val = temp | (flagc ? 0x100 : 0); \
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val >>= 1; \
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SETNZ(val) \
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flagc = !!(val & 0x40); \
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flagv = ((val & 0x40) ^ ((val & 0x20) << 1)); \
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regs.a = (val & 0xFF); \
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}
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#define ASL_NMOS bSlowerOnPagecross = 0; \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ASL_CMOS bSlowerOnPagecross = 1; \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ASLA val = regs.a << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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regs.a = (BYTE)val;
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#define ASO bSlowerOnPagecross = 0; \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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WRITE(val) \
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regs.a |= val; \
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SETNZ(regs.a)
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#define AXA bSlowerOnPagecross = 0;/*FIXME: $93 case is still unclear*/ \
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val = regs.a & regs.x & (((base >> 8) + 1) & 0xFF); \
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WRITE(val)
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#define AXS bSlowerOnPagecross = 0; \
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WRITE(regs.a & regs.x)
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#define BCC if (!flagc) BRANCH_TAKEN;
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#define BCS if ( flagc) BRANCH_TAKEN;
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#define BEQ if ( flagz) BRANCH_TAKEN;
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#define BIT bSlowerOnPagecross = 1; \
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val = READ; \
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flagz = !(regs.a & val); \
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flagn = val & 0x80; \
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flagv = val & 0x40;
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#define BITI flagz = !(regs.a & READ);
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#define BMI if ( flagn) BRANCH_TAKEN;
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#define BNE if (!flagz) BRANCH_TAKEN;
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#define BPL if (!flagn) BRANCH_TAKEN;
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#define BRA BRANCH_TAKEN;
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#define BRK regs.pc++; \
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PUSH(regs.pc >> 8) \
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PUSH(regs.pc & 0xFF) \
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EF_TO_AF \
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PUSH(regs.ps); \
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regs.ps |= AF_INTERRUPT; \
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regs.pc = *(LPWORD)(mem+0xFFFE);
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#define BVC if (!flagv) BRANCH_TAKEN;
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#define BVS if ( flagv) BRANCH_TAKEN;
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#define CLC flagc = 0;
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#define CLD regs.ps &= ~AF_DECIMAL;
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#define CLI regs.ps &= ~AF_INTERRUPT;
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#define CLV flagv = 0;
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#define CMP bSlowerOnPagecross = 1; \
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val = READ; \
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flagc = (regs.a >= val); \
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val = regs.a-val; \
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SETNZ(val)
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#define CPX val = READ; \
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flagc = (regs.x >= val); \
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val = regs.x-val; \
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SETNZ(val)
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#define CPY val = READ; \
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flagc = (regs.y >= val); \
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val = regs.y-val; \
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SETNZ(val)
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#define DCM bSlowerOnPagecross = 0; \
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val = READ-1; \
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WRITE(val) \
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flagc = (regs.a >= val); \
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val = regs.a-val; \
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SETNZ(val)
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#define DEA --regs.a; \
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SETNZ(regs.a)
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#define DEC_NMOS bSlowerOnPagecross = 0; \
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val = READ-1; \
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SETNZ(val) \
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WRITE(val)
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#define DEC_CMOS bSlowerOnPagecross = 1; \
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val = READ-1; \
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SETNZ(val) \
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WRITE(val)
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#define DEX --regs.x; \
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SETNZ(regs.x)
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#define DEY --regs.y; \
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SETNZ(regs.y)
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#define EOR bSlowerOnPagecross = 1; \
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regs.a ^= READ; \
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SETNZ(regs.a)
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#define HLT regs.bJammed = 1; \
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--regs.pc;
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#define INA ++regs.a; \
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SETNZ(regs.a)
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#define INC_NMOS bSlowerOnPagecross = 0; \
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val = READ+1; \
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SETNZ(val) \
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WRITE(val)
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#define INC_CMOS bSlowerOnPagecross = 1; \
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val = READ+1; \
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SETNZ(val) \
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WRITE(val)
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#define INS bSlowerOnPagecross = 0; \
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val = READ+1; \
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WRITE(val) \
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temp = val; \
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temp2 = regs.a - temp - !flagc; \
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if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) - (temp & 0x0F) - !flagc; \
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if (val & 0x10) \
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val = ((val - 0x06) & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0) - 0x10);\
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else \
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val = (val & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0));\
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if (val & 0x100) \
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val -= 0x60; \
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flagc = (temp2 < 0x100); \
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SETNZ(temp2 & 0xFF); \
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flagv = ((regs.a ^ temp2) & 0x80) && ((regs.a ^ temp) & 0x80);\
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regs.a = val & 0xFF; \
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} \
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else { \
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val = temp2; \
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flagc = (val < 0x100); \
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flagv = (((regs.a & 0x80) != (temp & 0x80)) && \
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((regs.a & 0x80) != (val & 0x80))); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a); \
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}
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#define INX ++regs.x; \
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SETNZ(regs.x)
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#define INY ++regs.y; \
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SETNZ(regs.y)
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#define JMP regs.pc = addr;
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#define JSR --regs.pc; \
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PUSH(regs.pc >> 8) \
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PUSH(regs.pc & 0xFF) \
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regs.pc = addr;
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#define LAS bSlowerOnPagecross = 1; \
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val = (BYTE)(READ & regs.sp); \
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regs.a = regs.x = (BYTE) val; \
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regs.sp = val | 0x100; \
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SETNZ(val)
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#define LAX bSlowerOnPagecross = 1; \
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regs.a = regs.x = READ; \
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SETNZ(regs.a)
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#define LDA bSlowerOnPagecross = 1; \
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regs.a = READ; \
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SETNZ(regs.a)
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#define LDX bSlowerOnPagecross = 1; \
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regs.x = READ; \
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SETNZ(regs.x)
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#define LDY bSlowerOnPagecross = 1; \
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regs.y = READ; \
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SETNZ(regs.y)
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#define LSE bSlowerOnPagecross = 0; \
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val = READ; \
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flagc = (val & 1); \
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val >>= 1; \
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WRITE(val) \
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regs.a ^= val; \
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SETNZ(regs.a)
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#define LSR_NMOS bSlowerOnPagecross = 0; \
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val = READ; \
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flagc = (val & 1); \
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flagn = 0; \
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val >>= 1; \
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SETZ(val) \
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WRITE(val)
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#define LSR_CMOS bSlowerOnPagecross = 1; \
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val = READ; \
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flagc = (val & 1); \
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flagn = 0; \
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val >>= 1; \
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SETZ(val) \
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WRITE(val)
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#define LSRA flagc = (regs.a & 1); \
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flagn = 0; \
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regs.a >>= 1; \
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SETZ(regs.a)
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#define NOP bSlowerOnPagecross = 1;
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#define OAL regs.a |= 0xEE; \
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regs.a &= READ; \
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regs.x = regs.a; \
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SETNZ(regs.a)
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#define ORA bSlowerOnPagecross = 1; \
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regs.a |= READ; \
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SETNZ(regs.a)
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#define PHA PUSH(regs.a)
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#define PHP EF_TO_AF \
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PUSH(regs.ps)
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#define PHX PUSH(regs.x)
|
||||
#define PHY PUSH(regs.y)
|
||||
#define PLA regs.a = POP; \
|
||||
SETNZ(regs.a)
|
||||
#define PLP regs.ps = POP | AF_RESERVED | AF_BREAK; \
|
||||
AF_TO_EF
|
||||
#define PLX regs.x = POP; \
|
||||
SETNZ(regs.x)
|
||||
#define PLY regs.y = POP; \
|
||||
SETNZ(regs.y)
|
||||
#define RLA bSlowerOnPagecross = 0; \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
WRITE(val) \
|
||||
regs.a &= val; \
|
||||
SETNZ(regs.a)
|
||||
#define ROL_NMOS bSlowerOnPagecross = 0; \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ROL_CMOS bSlowerOnPagecross = 1; \
|
||||
val = (READ << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ROLA val = (((WORD)regs.a) << 1) | flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a);
|
||||
#define ROR_NMOS bSlowerOnPagecross = 0; \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define ROR_CMOS bSlowerOnPagecross = 1; \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
SETNZ(val) \
|
||||
WRITE(val)
|
||||
#define RORA val = (((WORD)regs.a) >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (regs.a & 1); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a)
|
||||
#define RRA bSlowerOnPagecross = 0; \
|
||||
temp = READ; \
|
||||
val = (temp >> 1) | (flagc ? 0x80 : 0); \
|
||||
flagc = (temp & 1); \
|
||||
WRITE(val) \
|
||||
temp = val; \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
|
||||
if (val > 0x09) \
|
||||
val += 0x06; \
|
||||
if (val <= 0x0F) \
|
||||
val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0); \
|
||||
else \
|
||||
val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0) + 0x10;\
|
||||
flagz = !((regs.a + temp + flagc) & 0xFF); \
|
||||
flagn = (val & 0x80); \
|
||||
flagv = ((regs.a ^ val) & 0x80) && !((regs.a ^ temp) & 0x80);\
|
||||
if ((val & 0x1F0) > 0x90) \
|
||||
val += 0x60; \
|
||||
flagc = ((val & 0xFF0) > 0xF0); \
|
||||
regs.a = val & 0xFF; \
|
||||
} \
|
||||
else { \
|
||||
val = regs.a + temp + flagc; \
|
||||
flagc = (val > 0xFF); \
|
||||
flagv = (((regs.a & 0x80) == (temp & 0x80)) && \
|
||||
((regs.a & 0x80) != (val & 0x80))); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a); \
|
||||
}
|
||||
#define RTI regs.ps = POP | AF_RESERVED | AF_BREAK; \
|
||||
AF_TO_EF \
|
||||
regs.pc = POP; \
|
||||
regs.pc |= (((WORD)POP) << 8);
|
||||
#define RTS regs.pc = POP; \
|
||||
regs.pc |= (((WORD)POP) << 8); \
|
||||
++regs.pc;
|
||||
#define SAX temp = regs.a & regs.x; \
|
||||
val = READ; \
|
||||
flagc = (temp >= val); \
|
||||
regs.x = temp-val; \
|
||||
SETNZ(regs.x)
|
||||
#define SAY bSlowerOnPagecross = 0; \
|
||||
val = regs.y & (((base >> 8) + 1) & 0xFF); \
|
||||
WRITE(val)
|
||||
#define SBC_NMOS bSlowerOnPagecross = 1; \
|
||||
temp = READ; \
|
||||
temp2 = regs.a - temp - !flagc; \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
val = (regs.a & 0x0F) - (temp & 0x0F) - !flagc; \
|
||||
if (val & 0x10) \
|
||||
val = ((val - 0x06) & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0) - 0x10);\
|
||||
else \
|
||||
val = (val & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0));\
|
||||
if (val & 0x100) \
|
||||
val -= 0x60; \
|
||||
flagc = (temp2 < 0x100); \
|
||||
SETNZ(temp2 & 0xFF); \
|
||||
flagv = ((regs.a ^ temp2) & 0x80) && ((regs.a ^ temp) & 0x80);\
|
||||
regs.a = val & 0xFF; \
|
||||
} \
|
||||
else { \
|
||||
val = temp2; \
|
||||
flagc = (val < 0x100); \
|
||||
flagv = (((regs.a & 0x80) != (temp & 0x80)) && \
|
||||
((regs.a & 0x80) != (val & 0x80))); \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a); \
|
||||
}
|
||||
#define SBC_CMOS bSlowerOnPagecross = 1; \
|
||||
temp = READ; \
|
||||
flagv = ((regs.a ^ temp) & 0x80); \
|
||||
if (regs.ps & AF_DECIMAL) { \
|
||||
uExtraCycles++; \
|
||||
temp2 = 0x0F + (regs.a & 0x0F) - (temp & 0x0F) + flagc; \
|
||||
if (temp2 < 0x10) { \
|
||||
val = 0; \
|
||||
temp2 -= 0x06; \
|
||||
} \
|
||||
else { \
|
||||
val = 0x10; \
|
||||
temp2 -= 0x10; \
|
||||
} \
|
||||
val += 0xF0 + (regs.a & 0xF0) - (temp & 0xF0); \
|
||||
if (val < 0x100) { \
|
||||
flagc = 0; \
|
||||
if (val < 0x80) \
|
||||
flagv = 0; \
|
||||
val -= 0x60; \
|
||||
} \
|
||||
else { \
|
||||
flagc = 1; \
|
||||
if (val >= 0x180) \
|
||||
flagv = 0; \
|
||||
} \
|
||||
val += temp2; \
|
||||
} \
|
||||
else { \
|
||||
val = 0xff + regs.a - temp + flagc; \
|
||||
if (val < 0x100) { \
|
||||
flagc = 0; \
|
||||
if (val < 0x80) \
|
||||
flagv = 0; \
|
||||
} \
|
||||
else { \
|
||||
flagc = 1; \
|
||||
if (val >= 0x180) \
|
||||
flagv = 0; \
|
||||
} \
|
||||
} \
|
||||
regs.a = val & 0xFF; \
|
||||
SETNZ(regs.a)
|
||||
#define SEC flagc = 1;
|
||||
#define SED regs.ps |= AF_DECIMAL;
|
||||
#define SEI regs.ps |= AF_INTERRUPT;
|
||||
#define STA bSlowerOnPagecross = 0; \
|
||||
WRITE(regs.a)
|
||||
#define STX bSlowerOnPagecross = 0; \
|
||||
WRITE(regs.x)
|
||||
#define STY bSlowerOnPagecross = 0; \
|
||||
WRITE(regs.y)
|
||||
#define STZ bSlowerOnPagecross = 0; \
|
||||
WRITE(0)
|
||||
#define TAS bSlowerOnPagecross = 0; \
|
||||
val = regs.a & regs.x; \
|
||||
regs.sp = 0x100 | val; \
|
||||
val &= (((base >> 8) + 1) & 0xFF); \
|
||||
WRITE(val)
|
||||
#define TAX regs.x = regs.a; \
|
||||
SETNZ(regs.x)
|
||||
#define TAY regs.y = regs.a; \
|
||||
SETNZ(regs.y)
|
||||
#define TRB bSlowerOnPagecross = 0; \
|
||||
val = READ; \
|
||||
flagz = !(regs.a & val); \
|
||||
val &= ~regs.a; \
|
||||
WRITE(val)
|
||||
#define TSB bSlowerOnPagecross = 0; \
|
||||
val = READ; \
|
||||
flagz = !(regs.a & val); \
|
||||
val |= regs.a; \
|
||||
WRITE(val)
|
||||
#define TSX regs.x = regs.sp & 0xFF; \
|
||||
SETNZ(regs.x)
|
||||
#define TXA regs.a = regs.x; \
|
||||
SETNZ(regs.a)
|
||||
#define TXS regs.sp = 0x100 | regs.x;
|
||||
#define TYA regs.a = regs.y; \
|
||||
SETNZ(regs.a)
|
||||
#define XAA regs.a = regs.x; \
|
||||
regs.a &= READ; \
|
||||
SETNZ(regs.a)
|
||||
#define XAS bSlowerOnPagecross = 0; \
|
||||
val = regs.x & (((base >> 8) + 1) & 0xFF); \
|
||||
WRITE(val)
|
||||
#include "cpu/cpu_instructions.inl"
|
||||
|
||||
void RequestDebugger()
|
||||
{
|
||||
@ -1590,6 +992,8 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
|
||||
return uExecutedCycles;
|
||||
}
|
||||
|
||||
//#include "cpu/cpu65d02.cpp"
|
||||
|
||||
//===========================================================================
|
||||
|
||||
static DWORD InternalCpuExecute (DWORD uTotalCycles)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user