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Fixes for CPU emulation relating to page-crossing: bugs #264, #278; and opcode (abx,x): bug #271

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tomcw 2015-04-25 21:15:17 +01:00
parent 60db3d6622
commit 151a7f3b33
6 changed files with 251 additions and 240 deletions
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2
source/CPU.cpp
View File

@ -63,7 +63,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// What about these:
// . 65C02: STZ?, TRB?, TSB?
// . Answer: TRB & TSB don't have affected adressing modes
// . Answer: TRB & TSB don't have affected addressing modes
// . STZ probably doesn't add a cycle since otherwise it would be slower than STA which doesn't make sense.
//
// NB. 'Zero-page indexed' opcodes wrap back to zero-page.

135
source/CPU/cpu6502.h
View File

@ -35,7 +35,6 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
WORD val;
AF_TO_EF
ULONG uExecutedCycles = 0;
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
WORD base;
g_bDebugBreakpointHit = 0;
@ -67,27 +66,27 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: $ IMM ANC CYC(2) break; // invald
case 0x0C: $ abx NOP CYC(4) break;
case 0x0B: $ IMM ANC CYC(2) break; // invalid
case 0x0C: $ ABSX_SLOW NOP CYC(4) break;
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLn CYC(6) break;
case 0x0F: $ ABS ASO CYC(6) break; // invalid
case 0x10: REL BPL CYC(2) break;
case 0x11: idy ORA CYC(5) break;
case 0x11: INDY_SLOW ORA CYC(5) break;
case 0x12: $ HLT CYC(2) break;
case 0x13: $ idy ASO CYC(8) break; // invalid
case 0x13: $ INDY_FAST ASO CYC(8) break; // invalid
case 0x14: $ zpx NOP CYC(4) break;
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLn CYC(6) break;
case 0x17: $ zpx ASO CYC(6) break; // invalid
case 0x18: CLC CYC(2) break;
case 0x19: aby ORA CYC(4) break;
case 0x19: ABSY_SLOW ORA CYC(4) break;
case 0x1A: $ NOP CYC(2) break;
case 0x1B: $ aby ASO CYC(7) break; // invalid
case 0x1C: $ abx NOP CYC(4) break;
case 0x1D: abx ORA CYC(4) break;
case 0x1E: abx ASLn CYC(6) break;
case 0x1F: $ abx ASO CYC(7) break; // invalid
case 0x1B: $ ABSY_FAST ASO CYC(7) break; // invalid
case 0x1C: $ ABSX_SLOW NOP CYC(4) break;
case 0x1D: ABSX_SLOW ORA CYC(4) break;
case 0x1E: ABSX_NMOS_RMW ASLn CYC(7) break;
case 0x1F: $ ABSX_FAST ASO CYC(7) break; // invalid
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: $ HLT CYC(2) break;
@ -105,21 +104,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0x2E: ABS ROLn CYC(6) break;
case 0x2F: $ ABS RLA CYC(6) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: idy AND CYC(5) break;
case 0x31: INDY_SLOW AND CYC(5) break;
case 0x32: $ HLT CYC(2) break;
case 0x33: $ idy RLA CYC(8) break; // invalid
case 0x33: $ INDY_FAST RLA CYC(8) break; // invalid
case 0x34: $ zpx NOP CYC(4) break;
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLn CYC(6) break;
case 0x37: $ zpx RLA CYC(6) break;
case 0x38: SEC CYC(2) break;
case 0x39: aby AND CYC(4) break;
case 0x39: ABSY_SLOW AND CYC(4) break;
case 0x3A: $ NOP CYC(2) break;
case 0x3B: $ aby RLA CYC(7) break; // invalid
case 0x3C: $ abx NOP CYC(4) break;
case 0x3D: abx AND CYC(4) break;
case 0x3E: abx ROLn CYC(6) break;
case 0x3F: $ abx RLA CYC(7) break; // invalid
case 0x3B: $ ABSY_FAST RLA CYC(7) break; // invalid
case 0x3C: $ ABSX_SLOW NOP CYC(4) break;
case 0x3D: ABSX_SLOW AND CYC(4) break;
case 0x3E: ABSX_FAST ROLn CYC(6) break;
case 0x3F: $ ABSX_FAST RLA CYC(7) break; // invalid
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: $ HLT CYC(2) break;
@ -137,21 +136,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0x4E: ABS LSRn CYC(6) break;
case 0x4F: $ ABS LSE CYC(6) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: idy EOR CYC(5) break;
case 0x51: INDY_SLOW EOR CYC(5) break;
case 0x52: $ HLT CYC(2) break;
case 0x53: $ idy LSE CYC(8) break;
case 0x53: $ INDY_FAST LSE CYC(8) break;
case 0x54: $ zpx NOP CYC(4) break;
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRn CYC(6) break;
case 0x57: $ zpx LSE CYC(6) break; // invalid
case 0x58: CLI CYC(2) break;
case 0x59: aby EOR CYC(4) break;
case 0x59: ABSY_SLOW EOR CYC(4) break;
case 0x5A: $ NOP CYC(2) break;
case 0x5B: $ aby LSE CYC(7) break; // invalid
case 0x5C: $ abx NOP CYC(4) break;
case 0x5D: abx EOR CYC(4) break;
case 0x5E: abx LSRn CYC(6) break;
case 0x5F: $ abx LSE CYC(7) break;
case 0x5B: $ ABSY_FAST LSE CYC(7) break; // invalid
case 0x5C: $ ABSX_SLOW NOP CYC(4) break;
case 0x5D: ABSX_SLOW EOR CYC(4) break;
case 0x5E: ABSX_FAST LSRn CYC(6) break;
case 0x5F: $ ABSX_FAST LSE CYC(7) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCn CYC(6) break;
case 0x62: $ HLT CYC(2) break;
@ -164,26 +163,26 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0x69: IMM ADCn CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: $ IMM ARR CYC(2) break; // invalid
case 0x6C: IABSNMOS JMP CYC(6) break;
case 0x6C: IABSNMOS JMP CYC(5) break; // GH#264
case 0x6D: ABS ADCn CYC(4) break;
case 0x6E: ABS RORn CYC(6) break;
case 0x6F: $ ABS RRA CYC(6) break; // invalid
case 0x70: REL BVS CYC(2) break;
case 0x71: idy ADCn CYC(5) break;
case 0x71: INDY_SLOW ADCn CYC(5) break;
case 0x72: $ HLT CYC(2) break;
case 0x73: $ idy RRA CYC(8) break; // invalid
case 0x73: $ INDY_FAST RRA CYC(8) break; // invalid
case 0x74: $ zpx NOP CYC(4) break;
case 0x75: zpx ADCn CYC(4) break;
case 0x76: zpx RORn CYC(6) break;
case 0x77: $ zpx RRA CYC(6) break; // invalid
case 0x78: SEI CYC(2) break;
case 0x79: aby ADCn CYC(4) break;
case 0x79: ABSY_SLOW ADCn CYC(4) break;
case 0x7A: $ NOP CYC(2) break;
case 0x7B: $ aby RRA CYC(7) break; // invalid
case 0x7C: $ abx NOP CYC(4) break;
case 0x7D: abx ADCn CYC(4) break;
case 0x7E: abx RORn CYC(6) break;
case 0x7F: $ abx RRA CYC(7) break; // invalid
case 0x7B: $ ABSY_FAST RRA CYC(7) break; // invalid
case 0x7C: $ ABSX_SLOW NOP CYC(4) break;
case 0x7D: ABSX_SLOW ADCn CYC(4) break;
case 0x7E: ABSX_FAST RORn CYC(6) break;
case 0x7F: $ ABSX_FAST RRA CYC(7) break; // invalid
case 0x80: $ IMM NOP CYC(2) break;
case 0x81: idx STA CYC(6) break;
case 0x82: $ IMM NOP CYC(2) break;
@ -201,21 +200,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ ABS AXS CYC(4) break; // invalid
case 0x90: REL BCC CYC(2) break;
case 0x91: idy STA CYC(6) break;
case 0x91: INDY_FAST STA CYC(6) break;
case 0x92: $ HLT CYC(2) break;
case 0x93: $ idy AXA CYC(6) break; // invalid
case 0x93: $ INDY_FAST AXA CYC(6) break; // invalid
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: $ zpy AXS CYC(4) break; // invalid
case 0x98: TYA CYC(2) break;
case 0x99: aby STA CYC(5) break;
case 0x99: ABSY_FAST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ aby TAS CYC(5) break; // invalid
case 0x9C: $ abx SAY CYC(5) break; // invalid
case 0x9D: abx STA CYC(5) break;
case 0x9E: $ aby XAS CYC(5) break;
case 0x9F: $ aby AXA CYC(5) break;
case 0x9B: $ ABSY_FAST TAS CYC(5) break; // invalid
case 0x9C: $ ABSX_FAST SAY CYC(5) break; // invalid
case 0x9D: ABSX_FAST STA CYC(5) break;
case 0x9E: $ ABSY_FAST XAS CYC(5) break;
case 0x9F: $ ABSY_FAST AXA CYC(5) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
@ -233,21 +232,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ ABS LAX CYC(4) break; // invalid
case 0xB0: REL BCS CYC(2) break;
case 0xB1: idy LDA CYC(5) break;
case 0xB1: INDY_SLOW LDA CYC(5) break;
case 0xB2: $ HLT CYC(2) break;
case 0xB3: $ idy LAX CYC(5) break;
case 0xB3: $ INDY_SLOW LAX CYC(5) break;
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ zpy LAX CYC(4) break; // invalid
case 0xB8: CLV CYC(2) break;
case 0xB9: aby LDA CYC(4) break;
case 0xB9: ABSY_SLOW LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ aby LAS CYC(4) break; // invalid
case 0xBC: abx LDY CYC(4) break;
case 0xBD: abx LDA CYC(4) break;
case 0xBE: aby LDX CYC(4) break;
case 0xBF: $ aby LAX CYC(4) break; // invalid
case 0xBB: $ ABSY_SLOW LAS CYC(4) break; // invalid
case 0xBC: ABSX_SLOW LDY CYC(4) break;
case 0xBD: ABSX_SLOW LDA CYC(4) break;
case 0xBE: ABSY_SLOW LDX CYC(4) break;
case 0xBF: $ ABSY_SLOW LAX CYC(4) break; // invalid
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: $ IMM NOP CYC(2) break;
@ -265,21 +264,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0xCE: ABS DECn CYC(5) break;
case 0xCF: $ ABS DCM CYC(6) break; // invalid
case 0xD0: REL BNE CYC(2) break;
case 0xD1: idy CMP CYC(5) break;
case 0xD1: INDY_SLOW CMP CYC(5) break;
case 0xD2: $ HLT CYC(2) break;
case 0xD3: $ idy DCM CYC(8) break; // invalid
case 0xD3: $ INDY_FAST DCM CYC(8) break; // invalid
case 0xD4: $ zpx NOP CYC(4) break;
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DECn CYC(6) break;
case 0xD7: $ zpx DCM CYC(6) break; // invalid
case 0xD8: CLD CYC(2) break;
case 0xD9: aby CMP CYC(4) break;
case 0xD9: ABSY_SLOW CMP CYC(4) break;
case 0xDA: $ NOP CYC(2) break;
case 0xDB: $ aby DCM CYC(7) break; // invalid
case 0xDC: $ abx NOP CYC(4) break;
case 0xDD: abx CMP CYC(4) break;
case 0xDE: abx DECn CYC(6) break;
case 0xDF: $ abx DCM CYC(7) break; // invalid
case 0xDB: $ ABSY_FAST DCM CYC(7) break; // invalid
case 0xDC: $ ABSX_SLOW NOP CYC(4) break;
case 0xDD: ABSX_SLOW CMP CYC(4) break;
case 0xDE: ABSX_NMOS_RMW DECn CYC(7) break;
case 0xDF: $ ABSX_FAST DCM CYC(7) break; // invalid
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCn CYC(6) break;
case 0xE2: $ IMM NOP CYC(2) break;
@ -297,21 +296,21 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
case 0xEE: ABS INCn CYC(6) break;
case 0xEF: $ ABS INS CYC(6) break; // invalid
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: idy SBCn CYC(5) break;
case 0xF1: INDY_SLOW SBCn CYC(5) break;
case 0xF2: $ HLT CYC(2) break;
case 0xF3: $ idy INS CYC(8) break; // invalid
case 0xF3: $ INDY_FAST INS CYC(8) break; // invalid
case 0xF4: $ zpx NOP CYC(4) break;
case 0xF5: zpx SBCn CYC(4) break;
case 0xF6: zpx INCn CYC(6) break;
case 0xF7: $ zpx INS CYC(6) break; // invalid
case 0xF8: SED CYC(2) break;
case 0xF9: aby SBCn CYC(4) break;
case 0xF9: ABSY_SLOW SBCn CYC(4) break;
case 0xFA: $ NOP CYC(2) break;
case 0xFB: $ aby INS CYC(7) break;
case 0xFC: $ abx NOP CYC(4) break;
case 0xFD: abx SBCn CYC(4) break;
case 0xFE: abx INCn CYC(6) break;
case 0xFF: $ abx INS CYC(7) break;
case 0xFB: $ ABSY_FAST INS CYC(7) break;
case 0xFC: $ ABSX_SLOW NOP CYC(4) break;
case 0xFD: ABSX_SLOW SBCn CYC(4) break;
case 0xFE: ABSX_NMOS_RMW INCn CYC(7) break;
case 0xFF: $ ABSX_FAST INS CYC(7) break;
}
}

75
source/CPU/cpu65C02.h
View File

@ -38,7 +38,6 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
WORD val;
AF_TO_EF
ULONG uExecutedCycles = 0;
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
WORD base;
g_bDebugBreakpointHit = 0;
@ -76,7 +75,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x0E: ABS ASLc CYC(6) break;
case 0x0F: $ NOP CYC(2) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: idy ORA CYC(5) break;
case 0x11: INDY_SLOW ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: $ NOP CYC(2) break;
case 0x14: ZPG TRB CYC(5) break;
@ -84,12 +83,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x16: zpx ASLc CYC(6) break;
case 0x17: $ NOP CYC(2) break;
case 0x18: CLC CYC(2) break;
case 0x19: aby ORA CYC(4) break;
case 0x19: ABSY_SLOW ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: $ NOP CYC(2) break;
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: abx ORA CYC(4) break;
case 0x1E: abx ASLc CYC(6) break;
case 0x1D: ABSX_SLOW ORA CYC(4) break;
case 0x1E: ABSX_SLOW ASLc CYC(6) break;
case 0x1F: $ NOP CYC(2) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
@ -108,7 +107,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x2E: ABS ROLc CYC(6) break;
case 0x2F: $ NOP CYC(2) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: idy AND CYC(5) break;
case 0x31: INDY_SLOW AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: $ NOP CYC(2) break;
case 0x34: zpx BIT CYC(4) break;
@ -116,12 +115,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x36: zpx ROLc CYC(6) break;
case 0x37: $ NOP CYC(2) break;
case 0x38: SEC CYC(2) break;
case 0x39: aby AND CYC(4) break;
case 0x39: ABSY_SLOW AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: $ NOP CYC(2) break;
case 0x3C: abx BIT CYC(4) break;
case 0x3D: abx AND CYC(4) break;
case 0x3E: abx ROLc CYC(6) break;
case 0x3C: ABSX_SLOW BIT CYC(4) break;
case 0x3D: ABSX_SLOW AND CYC(4) break;
case 0x3E: ABSX_SLOW ROLc CYC(6) break;
case 0x3F: $ NOP CYC(2) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
@ -140,7 +139,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x4E: ABS LSRc CYC(6) break;
case 0x4F: $ NOP CYC(2) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: idy EOR CYC(5) break;
case 0x51: INDY_SLOW EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: $ NOP CYC(2) break;
case 0x54: $ zpx NOP CYC(4) break;
@ -148,12 +147,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x56: zpx LSRc CYC(6) break;
case 0x57: $ NOP CYC(2) break;
case 0x58: CLI CYC(2) break;
case 0x59: aby EOR CYC(4) break;
case 0x59: ABSY_SLOW EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: $ NOP CYC(2) break;
case 0x5C: $ abx NOP CYC(8) break;
case 0x5D: abx EOR CYC(4) break;
case 0x5E: abx LSRc CYC(6) break;
case 0x5C: $ ABSX_SLOW NOP CYC(8) break;
case 0x5D: ABSX_SLOW EOR CYC(4) break;
case 0x5E: ABSX_SLOW LSRc CYC(6) break;
case 0x5F: $ NOP CYC(2) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCc CYC(6) break;
@ -172,7 +171,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x6E: ABS RORc CYC(6) break;
case 0x6F: $ NOP CYC(2) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: idy ADCc CYC(5) break;
case 0x71: INDY_SLOW ADCc CYC(5) break;
case 0x72: izp ADCc CYC(5) break;
case 0x73: $ NOP CYC(2) break;
case 0x74: zpx STZ CYC(4) break;
@ -180,12 +179,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x76: zpx RORc CYC(6) break;
case 0x77: $ NOP CYC(2) break;
case 0x78: SEI CYC(2) break;
case 0x79: aby ADCc CYC(4) break;
case 0x79: ABSY_SLOW ADCc CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: $ NOP CYC(2) break;
case 0x7C: IABSX JMP CYC(6) break; //
case 0x7D: abx ADCc CYC(4) break;
case 0x7E: abx RORc CYC(6) break;
case 0x7D: ABSX_SLOW ADCc CYC(4) break;
case 0x7E: ABSX_SLOW RORc CYC(6) break;
case 0x7F: $ NOP CYC(2) break;
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
@ -204,7 +203,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ NOP CYC(2) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: idy STA CYC(6) break;
case 0x91: INDY_FAST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: $ NOP CYC(2) break;
case 0x94: zpx STY CYC(4) break;
@ -212,12 +211,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0x96: zpy STX CYC(4) break;
case 0x97: $ NOP CYC(2) break;
case 0x98: TYA CYC(2) break;
case 0x99: aby STA CYC(5) break;
case 0x99: ABSY_FAST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ NOP CYC(2) break;
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: abx STA CYC(5) break;
case 0x9E: abx STZ CYC(5) break;
case 0x9D: ABSX_FAST STA CYC(5) break;
case 0x9E: ABSX_FAST STZ CYC(5) break;
case 0x9F: $ NOP CYC(2) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
@ -236,7 +235,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ NOP CYC(2) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: idy LDA CYC(5) break;
case 0xB1: INDY_SLOW LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: $ NOP CYC(2) break;
case 0xB4: zpx LDY CYC(4) break;
@ -244,12 +243,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ NOP CYC(2) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: aby LDA CYC(4) break;
case 0xB9: ABSY_SLOW LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ NOP CYC(2) break;
case 0xBC: abx LDY CYC(4) break;
case 0xBD: abx LDA CYC(4) break;
case 0xBE: aby LDX CYC(4) break;
case 0xBC: ABSX_SLOW LDY CYC(4) break;
case 0xBD: ABSX_SLOW LDA CYC(4) break;
case 0xBE: ABSY_SLOW LDX CYC(4) break;
case 0xBF: $ NOP CYC(2) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
@ -268,7 +267,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xCE: ABS DECc CYC(5) break;
case 0xCF: $ NOP CYC(2) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: idy CMP CYC(5) break;
case 0xD1: INDY_SLOW CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: $ NOP CYC(2) break;
case 0xD4: $ zpx NOP CYC(4) break;
@ -276,12 +275,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xD6: zpx DECc CYC(6) break;
case 0xD7: $ NOP CYC(2) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: aby CMP CYC(4) break;
case 0xD9: ABSY_SLOW CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: $ NOP CYC(2) break;
case 0xDC: $ abx NOP CYC(4) break;
case 0xDD: abx CMP CYC(4) break;
case 0xDE: abx DECc CYC(6) break;
case 0xDC: $ ABSX_SLOW NOP CYC(4) break;
case 0xDD: ABSX_SLOW CMP CYC(4) break;
case 0xDE: ABSX_SLOW DECc CYC(6) break;
case 0xDF: $ NOP CYC(2) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCc CYC(6) break;
@ -300,7 +299,7 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xEE: ABS INCc CYC(6) break;
case 0xEF: $ NOP CYC(2) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: idy SBCc CYC(5) break;
case 0xF1: INDY_SLOW SBCc CYC(5) break;
case 0xF2: izp SBCc CYC(5) break;
case 0xF3: $ NOP CYC(2) break;
case 0xF4: $ zpx NOP CYC(4) break;
@ -308,12 +307,12 @@ static DWORD Cpu65C02 (DWORD uTotalCycles)
case 0xF6: zpx INCc CYC(6) break;
case 0xF7: $ NOP CYC(2) break;
case 0xF8: SED CYC(2) break;
case 0xF9: aby SBCc CYC(4) break;
case 0xF9: ABSY_SLOW SBCc CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: $ NOP CYC(2) break;
case 0xFC: $ abx NOP CYC(4) break;
case 0xFD: abx SBCc CYC(4) break;
case 0xFE: abx INCc CYC(6) break;
case 0xFC: $ ABSX_SLOW NOP CYC(4) break;
case 0xFD: ABSX_SLOW SBCc CYC(4) break;
case 0xFE: ABSX_SLOW INCc CYC(6) break;
case 0xFF: $ NOP CYC(2) break;
}
#undef $

149
source/CPU/cpu65d02.h
View File

@ -97,7 +97,6 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
WORD val;
AF_TO_EF
ULONG uExecutedCycles = 0;
BOOL bSlowerOnPagecross = 0; // Set if opcode writes to memory (eg. ASL, STA)
WORD base;
g_bDebugBreakpointHit = 0;
@ -147,7 +146,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x0E: ABS ASL_CMOS CYC(6) break;
case 0x0F: INV NOP CYC(2) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: idy ORA CYC(5) break;
case 0x11: INDY_SLOW ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: INV NOP CYC(2) break;
case 0x14: ZPG TRB CYC(5) break;
@ -155,12 +154,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x16: zpx ASL_CMOS CYC(6) break;
case 0x17: INV NOP CYC(2) break;
case 0x18: CLC CYC(2) break;
case 0x19: aby ORA CYC(4) break;
case 0x19: ABSY_SLOW ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: INV NOP CYC(2) break;
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: abx ORA CYC(4) break;
case 0x1E: abx ASL_CMOS CYC(6) break;
case 0x1D: ABSX_SLOW ORA CYC(4) break;
case 0x1E: ABSX_SLOW ASL_CMOS CYC(6) break;
case 0x1F: INV NOP CYC(2) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
@ -179,7 +178,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x2E: ABS ROL_CMOS CYC(6) break;
case 0x2F: INV NOP CYC(2) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: idy AND CYC(5) break;
case 0x31: INDY_SLOW AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: INV NOP CYC(2) break;
case 0x34: zpx BIT CYC(4) break;
@ -187,12 +186,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x36: zpx ROL_CMOS CYC(6) break;
case 0x37: INV NOP CYC(2) break;
case 0x38: SEC CYC(2) break;
case 0x39: aby AND CYC(4) break;
case 0x39: ABSY_SLOW AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: INV NOP CYC(2) break;
case 0x3C: abx BIT CYC(4) break;
case 0x3D: abx AND CYC(4) break;
case 0x3E: abx ROL_CMOS CYC(6) break;
case 0x3C: ABSX_SLOW BIT CYC(4) break;
case 0x3D: ABSX_SLOW AND CYC(4) break;
case 0x3E: ABSX_SLOW ROL_CMOS CYC(6) break;
case 0x3F: INV NOP CYC(2) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
@ -211,7 +210,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x4E: ABS LSR_CMOS CYC(6) break;
case 0x4F: INV NOP CYC(2) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: idy EOR CYC(5) break;
case 0x51: INDY_SLOW EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: INV NOP CYC(2) break;
case 0x54: INV zpx NOP CYC(4) break;
@ -219,12 +218,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x56: zpx LSR_CMOS CYC(6) break;
case 0x57: INV NOP CYC(2) break;
case 0x58: CLI CYC(2) break;
case 0x59: aby EOR CYC(4) break;
case 0x59: ABSY_SLOW EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: INV NOP CYC(2) break;
case 0x5C: INV abx NOP CYC(8) break;
case 0x5D: abx EOR CYC(4) break;
case 0x5E: abx LSR_CMOS CYC(6) break;
case 0x5C: INV ABSX_SLOW NOP CYC(8) break;
case 0x5D: ABSX_SLOW EOR CYC(4) break;
case 0x5E: ABSX_SLOW LSR_CMOS CYC(6) break;
case 0x5F: INV NOP CYC(2) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADC_CMOS CYC(6) break;
@ -243,7 +242,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x6E: ABS ROR_CMOS CYC(6) break;
case 0x6F: INV NOP CYC(2) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: idy ADC_CMOS CYC(5) break;
case 0x71: INDY_SLOW ADC_CMOS CYC(5) break;
case 0x72: izp ADC_CMOS CYC(5) break;
case 0x73: INV NOP CYC(2) break;
case 0x74: zpx STZ CYC(4) break;
@ -251,12 +250,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x76: zpx ROR_CMOS CYC(6) break;
case 0x77: INV NOP CYC(2) break;
case 0x78: SEI CYC(2) break;
case 0x79: aby ADC_CMOS CYC(4) break;
case 0x79: ABSY_SLOW ADC_CMOS CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: INV NOP CYC(2) break;
case 0x7C: IABSX JMP CYC(6) break; // 0x7C // 65c02 IABSX JMP // 6502 ABSX NOP
case 0x7D: abx ADC_CMOS CYC(4) break;
case 0x7E: abx ROR_CMOS CYC(6) break;
case 0x7D: ABSX_SLOW ADC_CMOS CYC(4) break;
case 0x7E: ABSX_SLOW ROR_CMOS CYC(6) break;
case 0x7F: INV NOP CYC(2) break;
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
@ -275,7 +274,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x8E: ABS STX CYC(4) break;
case 0x8F: INV NOP CYC(2) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: idy STA CYC(6) break;
case 0x91: INDY_FAST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: INV NOP CYC(2) break;
case 0x94: zpx STY CYC(4) break;
@ -283,12 +282,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x96: zpy STX CYC(4) break;
case 0x97: INV NOP CYC(2) break;
case 0x98: TYA CYC(2) break;
case 0x99: aby STA CYC(5) break;
case 0x99: ABSY_FAST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: INV NOP CYC(2) break;
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: abx STA CYC(5) break;
case 0x9E: abx STZ CYC(5) break;
case 0x9D: ABSX_FAST STA CYC(5) break;
case 0x9E: ABSX_FAST STZ CYC(5) break;
case 0x9F: INV NOP CYC(2) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
@ -307,7 +306,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: INV NOP CYC(2) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: idy LDA CYC(5) break;
case 0xB1: INDY_SLOW LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: INV NOP CYC(2) break;
case 0xB4: zpx LDY CYC(4) break;
@ -315,12 +314,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: INV NOP CYC(2) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: aby LDA CYC(4) break;
case 0xB9: ABSY_SLOW LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: INV NOP CYC(2) break;
case 0xBC: abx LDY CYC(4) break;
case 0xBD: abx LDA CYC(4) break;
case 0xBE: aby LDX CYC(4) break;
case 0xBC: ABSX_SLOW LDY CYC(4) break;
case 0xBD: ABSX_SLOW LDA CYC(4) break;
case 0xBE: ABSY_SLOW LDX CYC(4) break;
case 0xBF: INV NOP CYC(2) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
@ -339,7 +338,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xCE: ABS DEC_CMOS CYC(5) break;
case 0xCF: INV NOP CYC(2) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: idy CMP CYC(5) break;
case 0xD1: INDY_SLOW CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: INV NOP CYC(2) break;
case 0xD4: INV zpx NOP CYC(4) break;
@ -347,12 +346,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xD6: zpx DEC_CMOS CYC(6) break;
case 0xD7: INV NOP CYC(2) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: aby CMP CYC(4) break;
case 0xD9: ABSY_SLOW CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: INV NOP CYC(2) break;
case 0xDC: INV abx NOP CYC(4) break;
case 0xDD: abx CMP CYC(4) break;
case 0xDE: abx DEC_CMOS CYC(6) break;
case 0xDC: INV ABSX_SLOW NOP CYC(4) break;
case 0xDD: ABSX_SLOW CMP CYC(4) break;
case 0xDE: ABSX_SLOW DEC_CMOS CYC(6) break;
case 0xDF: INV NOP CYC(2) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBC_CMOS CYC(6) break;
@ -371,7 +370,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xEE: ABS INC_CMOS CYC(6) break;
case 0xEF: INV NOP CYC(2) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: idy SBC_CMOS CYC(5) break;
case 0xF1: INDY_SLOW SBC_CMOS CYC(5) break;
case 0xF2: izp SBC_CMOS CYC(5) break;
case 0xF3: INV NOP CYC(2) break;
case 0xF4: INV zpx NOP CYC(4) break;
@ -379,12 +378,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xF6: zpx INC_CMOS CYC(6) break;
case 0xF7: INV NOP CYC(2) break;
case 0xF8: SED CYC(2) break;
case 0xF9: aby SBC_CMOS CYC(4) break;
case 0xF9: ABSY_SLOW SBC_CMOS CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: INV NOP CYC(2) break;
case 0xFC: INV abx NOP CYC(4) break;
case 0xFD: abx SBC_CMOS CYC(4) break;
case 0xFE: abx INC_CMOS CYC(6) break;
case 0xFC: INV ABSX_SLOW NOP CYC(4) break;
case 0xFD: ABSX_SLOW SBC_CMOS CYC(4) break;
case 0xFE: ABSX_SLOW INC_CMOS CYC(6) break;
case 0xFF: INV NOP CYC(2) break;
*/
// Version 2 opcode: $ AM Instruction // $=DebugBreak AM=AddressingMode
@ -406,7 +405,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x0E: ABS ASLc CYC(6) break;
case 0x0F: $ NOP CYC(2) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: idy ORA CYC(5) break;
case 0x11: INDY_SLOW ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: $ NOP CYC(2) break;
case 0x14: ZPG TRB CYC(5) break;
@ -414,12 +413,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x16: zpx ASLc CYC(6) break;
case 0x17: $ NOP CYC(2) break;
case 0x18: CLC CYC(2) break;
case 0x19: aby ORA CYC(4) break;
case 0x19: ABSY_SLOW ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: $ NOP CYC(2) break;
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: abx ORA CYC(4) break;
case 0x1E: abx ASLc CYC(6) break;
case 0x1D: ABSX_SLOW ORA CYC(4) break;
case 0x1E: ABSX_SLOW ASLc CYC(6) break;
case 0x1F: $ NOP CYC(2) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
@ -438,7 +437,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x2E: ABS ROLc CYC(6) break;
case 0x2F: $ NOP CYC(2) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: idy AND CYC(5) break;
case 0x31: INDY_SLOW AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: $ NOP CYC(2) break;
case 0x34: zpx BIT CYC(4) break;
@ -446,12 +445,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x36: zpx ROLc CYC(6) break;
case 0x37: $ NOP CYC(2) break;
case 0x38: SEC CYC(2) break;
case 0x39: aby AND CYC(4) break;
case 0x39: ABSY_SLOW AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: $ NOP CYC(2) break;
case 0x3C: abx BIT CYC(4) break;
case 0x3D: abx AND CYC(4) break;
case 0x3E: abx ROLc CYC(6) break;
case 0x3C: ABSX_SLOW BIT CYC(4) break;
case 0x3D: ABSX_SLOW AND CYC(4) break;
case 0x3E: ABSX_SLOW ROLc CYC(6) break;
case 0x3F: $ NOP CYC(2) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
@ -470,7 +469,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x4E: ABS LSRc CYC(6) break;
case 0x4F: $ NOP CYC(2) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: idy EOR CYC(5) break;
case 0x51: INDY_SLOW EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: $ NOP CYC(2) break;
case 0x54: $ zpx NOP CYC(4) break;
@ -478,12 +477,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x56: zpx LSRc CYC(6) break;
case 0x57: $ NOP CYC(2) break;
case 0x58: CLI CYC(2) break;
case 0x59: aby EOR CYC(4) break;
case 0x59: ABSY_SLOW EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: $ NOP CYC(2) break;
case 0x5C: $ abx NOP CYC(8) break;
case 0x5D: abx EOR CYC(4) break;
case 0x5E: abx LSRc CYC(6) break;
case 0x5C: $ ABSX_SLOW NOP CYC(8) break;
case 0x5D: ABSX_SLOW EOR CYC(4) break;
case 0x5E: ABSX_SLOW LSRc CYC(6) break;
case 0x5F: $ NOP CYC(2) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCc CYC(6) break;
@ -502,7 +501,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x6E: ABS RORc CYC(6) break;
case 0x6F: $ NOP CYC(2) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: idy ADCc CYC(5) break;
case 0x71: INDY_SLOW ADCc CYC(5) break;
case 0x72: izp ADCc CYC(5) break;
case 0x73: $ NOP CYC(2) break;
case 0x74: zpx STZ CYC(4) break;
@ -510,12 +509,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x76: zpx RORc CYC(6) break;
case 0x77: $ NOP CYC(2) break;
case 0x78: SEI CYC(2) break;
case 0x79: aby ADCc CYC(4) break;
case 0x79: ABSY_SLOW ADCc CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: $ NOP CYC(2) break;
case 0x7C: IABSX JMP CYC(6) break; // 0x7C // 65c02 IABSX JMP // 6502 ABSX NOP
case 0x7D: abx ADCc CYC(4) break;
case 0x7E: abx RORc CYC(6) break;
case 0x7D: ABSX_SLOW ADCc CYC(4) break;
case 0x7E: ABSX_SLOW RORc CYC(6) break;
case 0x7F: $ NOP CYC(2) break;
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
@ -534,7 +533,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ NOP CYC(2) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: idy STA CYC(6) break;
case 0x91: INDY_FAST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: $ NOP CYC(2) break;
case 0x94: zpx STY CYC(4) break;
@ -542,12 +541,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0x96: zpy STX CYC(4) break;
case 0x97: $ NOP CYC(2) break;
case 0x98: TYA CYC(2) break;
case 0x99: aby STA CYC(5) break;
case 0x99: ABSY_FAST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ NOP CYC(2) break;
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: abx STA CYC(5) break;
case 0x9E: abx STZ CYC(5) break;
case 0x9D: ABSX_FAST STA CYC(5) break;
case 0x9E: ABSX_FAST STZ CYC(5) break;
case 0x9F: $ NOP CYC(2) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
@ -566,7 +565,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ NOP CYC(2) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: idy LDA CYC(5) break;
case 0xB1: INDY_SLOW LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: $ NOP CYC(2) break;
case 0xB4: zpx LDY CYC(4) break;
@ -574,12 +573,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ NOP CYC(2) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: aby LDA CYC(4) break;
case 0xB9: ABSY_SLOW LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ NOP CYC(2) break;
case 0xBC: abx LDY CYC(4) break;
case 0xBD: abx LDA CYC(4) break;
case 0xBE: aby LDX CYC(4) break;
case 0xBC: ABSX_SLOW LDY CYC(4) break;
case 0xBD: ABSX_SLOW LDA CYC(4) break;
case 0xBE: ABSY_SLOW LDX CYC(4) break;
case 0xBF: $ NOP CYC(2) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
@ -598,7 +597,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xCE: ABS DECc CYC(5) break;
case 0xCF: $ NOP CYC(2) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: idy CMP CYC(5) break;
case 0xD1: INDY_SLOW CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: $ NOP CYC(2) break;
case 0xD4: $ zpx NOP CYC(4) break;
@ -606,12 +605,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xD6: zpx DECc CYC(6) break;
case 0xD7: $ NOP CYC(2) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: aby CMP CYC(4) break;
case 0xD9: ABSY_SLOW CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: $ NOP CYC(2) break;
case 0xDC: $ abx NOP CYC(4) break;
case 0xDD: abx CMP CYC(4) break;
case 0xDE: abx DECc CYC(6) break;
case 0xDC: $ ABSX_SLOW NOP CYC(4) break;
case 0xDD: ABSX_SLOW CMP CYC(4) break;
case 0xDE: ABSX_SLOW DECc CYC(6) break;
case 0xDF: $ NOP CYC(2) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCc CYC(6) break;
@ -630,7 +629,7 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xEE: ABS INCc CYC(6) break;
case 0xEF: $ NOP CYC(2) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: idy SBCc CYC(5) break;
case 0xF1: INDY_SLOW SBCc CYC(5) break;
case 0xF2: izp SBCc CYC(5) break;
case 0xF3: $ NOP CYC(2) break;
case 0xF4: $ zpx NOP CYC(4) break;
@ -638,12 +637,12 @@ static DWORD Cpu65D02 (DWORD uTotalCycles)
case 0xF6: zpx INCc CYC(6) break;
case 0xF7: $ NOP CYC(2) break;
case 0xF8: SED CYC(2) break;
case 0xF9: aby SBCc CYC(4) break;
case 0xF9: ABSY_SLOW SBCc CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: $ NOP CYC(2) break;
case 0xFC: $ abx NOP CYC(4) break;
case 0xFD: abx SBCc CYC(4) break;
case 0xFE: abx INCc CYC(6) break;
case 0xFC: $ ABSX_SLOW NOP CYC(4) break;
case 0xFD: ABSX_SLOW SBCc CYC(4) break;
case 0xFE: ABSX_SLOW INCc CYC(6) break;
case 0xFF: $ NOP CYC(2) break;
}
#undef $

42
source/CPU/cpu_general.inl
View File

@ -89,10 +89,9 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
#define CHECK_PAGE_CHANGE if (bSlowerOnPagecross) { \
if ((base ^ addr) & 0xFF00) \
uExtraCycles=1; \
}
// TODO Optimization Note: uExtraCycles = ((base ^ addr) >> 8) & 1;
#define CHECK_PAGE_CHANGE if ((base ^ addr) & 0xFF00) \
uExtraCycles=1;
/****************************************************************************
*
@ -102,8 +101,16 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
#define IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
#define ABSX base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
#define ABSY base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
#define ABSX_SLOW base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
#define ABSX_FAST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
#define ABSY_SLOW base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
#define ABSY_FAST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2;
// NMOS read-modify-write opcodes (asl/dec/inc abs,x) don't take an extra cycle if page-crossing (GH#271)
#define ABSX_NMOS_RMW base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
// TODO Optimization Note: uExtraCycles = ((base & 0xFF) + 1) >> 8;
#define IABSCMOS base = *(LPWORD)(mem+regs.pc); \
addr = *(LPWORD)(mem+base); \
@ -121,13 +128,21 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
addr = *(LPWORD)(mem+base);
#define INDY if (*(mem+regs.pc) == 0xFF) \
#define INDY_SLOW if (*(mem+regs.pc) == 0xFF) /*SLOW: incurs an extra cycle for page-crossing*/ \
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
base = *(LPWORD)(mem+*(mem+regs.pc)); \
regs.pc++; \
addr = base+(WORD)regs.y; \
CHECK_PAGE_CHANGE;
#define INDY_FAST if (*(mem+regs.pc) == 0xFF) /*FAST: no extra cycle for page-crossing*/ \
base = *(mem+0xFF)+(((WORD)*mem)<<8); \
else \
base = *(LPWORD)(mem+*(mem+regs.pc)); \
regs.pc++; \
addr = base+(WORD)regs.y;
#define IZPG base = *(mem+regs.pc++); \
if (base == 0xFF) \
addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
@ -143,12 +158,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
// Tidy 3 char addressing modes to keep the opcode table visually aligned, clean, and readable.
#undef abx
#undef abx
#undef aby
//#undef abx
//#undef aby
#undef asl
#undef idx
#undef idy
//#undef idy
#undef imm
#undef izp
#undef lsr
@ -158,11 +172,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#undef zpx
#undef zpy
#define abx ABSX
#define aby ABSY
//#define abx ABSX // ABSX -> ABSX_SLOW or ABSX_FAST
//#define aby ABSY // ABSY -> ABSY_SLOW or ABSY_FAST
#define asl ASLA // Arithmetic Shift Left
#define idx INDX
#define idy INDY
//#define idy INDY // INDY -> INDY_SLOW or INDY_FAST
#define imm IMM
#define izp IZPG
#define lsr LSRA // Logical Shift Right

88
source/CPU/cpu_instructions.inl
View File

@ -177,7 +177,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// ==========
#define ADC_NMOS bSlowerOnPagecross = 1; \
#define ADC_NMOS /*bSlowerOnPagecross = 1;*/ \
temp = READ; \
if (regs.ps & AF_DECIMAL) { \
val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
@ -203,7 +203,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
regs.a = val & 0xFF; \
SETNZ(regs.a); \
}
#define ADC_CMOS bSlowerOnPagecross = 1; \
#define ADC_CMOS /*bSlowerOnPagecross = 1*/; \
temp = READ; \
flagv = !((regs.a ^ temp) & 0x80); \
if (regs.ps & AF_DECIMAL) { \
@ -242,7 +242,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagn = 0; \
regs.a >>= 1; \
SETZ(regs.a)
#define AND bSlowerOnPagecross = 1; \
#define AND /*bSlowerOnPagecross = 1;*/ \
regs.a &= READ; \
SETNZ(regs.a)
#define ANC regs.a &= READ; \
@ -274,12 +274,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagv = ((val & 0x40) ^ ((val & 0x20) << 1)); \
regs.a = (val & 0xFF); \
}
#define ASL_NMOS bSlowerOnPagecross = 0; \
#define ASL_NMOS /*bSlowerOnPagecross = 0;*/ \
val = READ << 1; \
flagc = (val > 0xFF); \
SETNZ(val) \
WRITE(val)
#define ASL_CMOS bSlowerOnPagecross = 1; \
#define ASL_CMOS /*bSlowerOnPagecross = 1*/; \
val = READ << 1; \
flagc = (val > 0xFF); \
SETNZ(val) \
@ -288,21 +288,21 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagc = (val > 0xFF); \
SETNZ(val) \
regs.a = (BYTE)val;
#define ASO bSlowerOnPagecross = 0; \
#define ASO /*bSlowerOnPagecross = 0;*/ \
val = READ << 1; \
flagc = (val > 0xFF); \
WRITE(val) \
regs.a |= val; \
SETNZ(regs.a)
#define AXA bSlowerOnPagecross = 0;/*FIXME: $93 case is still unclear*/ \
#define AXA /*bSlowerOnPagecross = 0;*//*FIXME: $93 case is still unclear*/ \
val = regs.a & regs.x & (((base >> 8) + 1) & 0xFF); \
WRITE(val)
#define AXS bSlowerOnPagecross = 0; \
#define AXS /*bSlowerOnPagecross = 0;*/ \
WRITE(regs.a & regs.x)
#define BCC if (!flagc) BRANCH_TAKEN;
#define BCS if ( flagc) BRANCH_TAKEN;
#define BEQ if ( flagz) BRANCH_TAKEN;
#define BIT bSlowerOnPagecross = 1; \
#define BIT /*bSlowerOnPagecross = 1;*/ \
val = READ; \
flagz = !(regs.a & val); \
flagn = val & 0x80; \
@ -325,7 +325,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define CLD regs.ps &= ~AF_DECIMAL;
#define CLI regs.ps &= ~AF_INTERRUPT;
#define CLV flagv = 0;
#define CMP bSlowerOnPagecross = 1; \
#define CMP /*bSlowerOnPagecross = 1;*/ \
val = READ; \
flagc = (regs.a >= val); \
val = regs.a-val; \
@ -338,7 +338,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagc = (regs.y >= val); \
val = regs.y-val; \
SETNZ(val)
#define DCM bSlowerOnPagecross = 0; \
#define DCM /*bSlowerOnPagecross = 0;*/ \
val = READ-1; \
WRITE(val) \
flagc = (regs.a >= val); \
@ -346,11 +346,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
SETNZ(val)
#define DEA --regs.a; \
SETNZ(regs.a)
#define DEC_NMOS bSlowerOnPagecross = 0; \
#define DEC_NMOS /*bSlowerOnPagecross = 0;*/ \
val = READ-1; \
SETNZ(val) \
WRITE(val)
#define DEC_CMOS bSlowerOnPagecross = 1; \
#define DEC_CMOS /*bSlowerOnPagecross = 1;*/ \
val = READ-1; \
SETNZ(val) \
WRITE(val)
@ -358,22 +358,22 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
SETNZ(regs.x)
#define DEY --regs.y; \
SETNZ(regs.y)
#define EOR bSlowerOnPagecross = 1; \
#define EOR /*bSlowerOnPagecross = 1;*/ \
regs.a ^= READ; \
SETNZ(regs.a)
#define HLT regs.bJammed = 1; \
--regs.pc;
#define INA ++regs.a; \
SETNZ(regs.a)
#define INC_NMOS bSlowerOnPagecross = 0; \
#define INC_NMOS /*bSlowerOnPagecross = 0;*/ \
val = READ+1; \
SETNZ(val) \
WRITE(val)
#define INC_CMOS bSlowerOnPagecross = 1; \
#define INC_CMOS /*bSlowerOnPagecross = 1;*/ \
val = READ+1; \
SETNZ(val) \
WRITE(val)
#define INS bSlowerOnPagecross = 0; \
#define INS /*bSlowerOnPagecross = 0;*/ \
val = READ+1; \
WRITE(val) \
temp = val; \
@ -408,38 +408,38 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
PUSH(regs.pc >> 8) \
PUSH(regs.pc & 0xFF) \
regs.pc = addr;
#define LAS bSlowerOnPagecross = 1; \
#define LAS /*bSlowerOnPagecross = 1*/; \
val = (BYTE)(READ & regs.sp); \
regs.a = regs.x = (BYTE) val; \
regs.sp = val | 0x100; \
SETNZ(val)
#define LAX bSlowerOnPagecross = 1; \
#define LAX /*bSlowerOnPagecross = 1;*/ \
regs.a = regs.x = READ; \
SETNZ(regs.a)
#define LDA bSlowerOnPagecross = 1; \
#define LDA /*bSlowerOnPagecross = 1;*/ \
regs.a = READ; \
SETNZ(regs.a)
#define LDX bSlowerOnPagecross = 1; \
#define LDX /*bSlowerOnPagecross = 1;*/ \
regs.x = READ; \
SETNZ(regs.x)
#define LDY bSlowerOnPagecross = 1; \
#define LDY /*bSlowerOnPagecross = 1;*/ \
regs.y = READ; \
SETNZ(regs.y)
#define LSE bSlowerOnPagecross = 0; \
#define LSE /*bSlowerOnPagecross = 0;*/ \
val = READ; \
flagc = (val & 1); \
val >>= 1; \
WRITE(val) \
regs.a ^= val; \
SETNZ(regs.a)
#define LSR_NMOS bSlowerOnPagecross = 0; \
#define LSR_NMOS /*bSlowerOnPagecross = 0;*/ \
val = READ; \
flagc = (val & 1); \
flagn = 0; \
val >>= 1; \
SETZ(val) \
WRITE(val)
#define LSR_CMOS bSlowerOnPagecross = 1; \
#define LSR_CMOS /*bSlowerOnPagecross = 1;*/ \
val = READ; \
flagc = (val & 1); \
flagn = 0; \
@ -450,12 +450,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagn = 0; \
regs.a >>= 1; \
SETZ(regs.a)
#define NOP bSlowerOnPagecross = 1;
#define NOP /*bSlowerOnPagecross = 1;*/
#define OAL regs.a |= 0xEE; \
regs.a &= READ; \
regs.x = regs.a; \
SETNZ(regs.a)
#define ORA bSlowerOnPagecross = 1; \
#define ORA /*bSlowerOnPagecross = 1;*/ \
regs.a |= READ; \
SETNZ(regs.a)
#define PHA PUSH(regs.a)
@ -471,18 +471,18 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
SETNZ(regs.x)
#define PLY regs.y = POP; \
SETNZ(regs.y)
#define RLA bSlowerOnPagecross = 0; \
#define RLA /*bSlowerOnPagecross = 0;*/ \
val = (READ << 1) | flagc; \
flagc = (val > 0xFF); \
WRITE(val) \
regs.a &= val; \
SETNZ(regs.a)
#define ROL_NMOS bSlowerOnPagecross = 0; \
#define ROL_NMOS /*bSlowerOnPagecross = 0;*/ \
val = (READ << 1) | flagc; \
flagc = (val > 0xFF); \
SETNZ(val) \
WRITE(val)
#define ROL_CMOS bSlowerOnPagecross = 1; \
#define ROL_CMOS /*bSlowerOnPagecross = 1;*/ \
val = (READ << 1) | flagc; \
flagc = (val > 0xFF); \
SETNZ(val) \
@ -491,13 +491,13 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagc = (val > 0xFF); \
regs.a = val & 0xFF; \
SETNZ(regs.a);
#define ROR_NMOS bSlowerOnPagecross = 0; \
#define ROR_NMOS /*bSlowerOnPagecross = 0;*/ \
temp = READ; \
val = (temp >> 1) | (flagc ? 0x80 : 0); \
flagc = (temp & 1); \
SETNZ(val) \
WRITE(val)
#define ROR_CMOS bSlowerOnPagecross = 1; \
#define ROR_CMOS /*bSlowerOnPagecross = 1;*/ \
temp = READ; \
val = (temp >> 1) | (flagc ? 0x80 : 0); \
flagc = (temp & 1); \
@ -507,7 +507,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagc = (regs.a & 1); \
regs.a = val & 0xFF; \
SETNZ(regs.a)
#define RRA bSlowerOnPagecross = 0; \
#define RRA /*bSlowerOnPagecross = 0;*/ \
temp = READ; \
val = (temp >> 1) | (flagc ? 0x80 : 0); \
flagc = (temp & 1); \
@ -549,10 +549,10 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagc = (temp >= val); \
regs.x = temp-val; \
SETNZ(regs.x)
#define SAY bSlowerOnPagecross = 0; \
#define SAY /*bSlowerOnPagecross = 0;*/ \
val = regs.y & (((base >> 8) + 1) & 0xFF); \
WRITE(val)
#define SBC_NMOS bSlowerOnPagecross = 1; \
#define SBC_NMOS /*bSlowerOnPagecross = 1;*/ \
temp = READ; \
temp2 = regs.a - temp - !flagc; \
if (regs.ps & AF_DECIMAL) { \
@ -576,7 +576,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
regs.a = val & 0xFF; \
SETNZ(regs.a); \
}
#define SBC_CMOS bSlowerOnPagecross = 1; \
#define SBC_CMOS /*bSlowerOnPagecross = 1;*/ \
temp = READ; \
flagv = ((regs.a ^ temp) & 0x80); \
if (regs.ps & AF_DECIMAL) { \
@ -622,15 +622,15 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define SEC flagc = 1;
#define SED regs.ps |= AF_DECIMAL;
#define SEI regs.ps |= AF_INTERRUPT;
#define STA bSlowerOnPagecross = 0; \
#define STA /*bSlowerOnPagecross = 0;*/ \
WRITE(regs.a)
#define STX bSlowerOnPagecross = 0; \
#define STX /*bSlowerOnPagecross = 0;*/ \
WRITE(regs.x)
#define STY bSlowerOnPagecross = 0; \
#define STY /*bSlowerOnPagecross = 0;*/ \
WRITE(regs.y)
#define STZ bSlowerOnPagecross = 0; \
#define STZ /*bSlowerOnPagecross = 0;*/ \
WRITE(0)
#define TAS bSlowerOnPagecross = 0; \
#define TAS /*bSlowerOnPagecross = 0;*/ \
val = regs.a & regs.x; \
regs.sp = 0x100 | val; \
val &= (((base >> 8) + 1) & 0xFF); \
@ -639,12 +639,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
SETNZ(regs.x)
#define TAY regs.y = regs.a; \
SETNZ(regs.y)
#define TRB bSlowerOnPagecross = 0; \
#define TRB /*bSlowerOnPagecross = 0;*/ \
val = READ; \
flagz = !(regs.a & val); \
val &= ~regs.a; \
WRITE(val)
#define TSB bSlowerOnPagecross = 0; \
#define TSB /*bSlowerOnPagecross = 0;*/ \
val = READ; \
flagz = !(regs.a & val); \
val |= regs.a; \
@ -659,7 +659,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define XAA regs.a = regs.x; \
regs.a &= READ; \
SETNZ(regs.a)
#define XAS bSlowerOnPagecross = 0; \
#define XAS /*bSlowerOnPagecross = 0;*/ \
val = regs.x & (((base >> 8) + 1) & 0xFF); \
WRITE(val)