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6522: reset also clears DDRB, DDRA, PCR

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tomcw 2023-03-11 21:08:41 +00:00
parent 5a7076135e
commit 17a4746df6
1 changed files with 4 additions and 1 deletions
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source/6522.cpp
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@ -46,7 +46,10 @@ void SY6522::Reset(const bool powerCycle)
} }
CpuCreateCriticalSection(); // Reset() called by SY6522 global ctor, so explicitly create CPU's CriticalSection CpuCreateCriticalSection(); // Reset() called by SY6522 global ctor, so explicitly create CPU's CriticalSection
Write(rDDRB, 0x00); // DDRB = 0x00: all pins are inputs
Write(rDDRA, 0x00); // DDRA = 0x00: all pins are inputs
Write(rACR, 0x00); // ACR = 0x00: T1 one-shot mode Write(rACR, 0x00); // ACR = 0x00: T1 one-shot mode
Write(rPCR, 0x00); // PCR = 0x00: CB2/CA2 Control = Input (negative active edge)
Write(rIFR, 0x7f); // IFR = 0x7F: de-assert any IRQs Write(rIFR, 0x7f); // IFR = 0x7F: de-assert any IRQs
Write(rIER, 0x7f); // IER = 0x7F: disable all IRQs Write(rIER, 0x7f); // IER = 0x7F: disable all IRQs
@ -120,7 +123,7 @@ void SY6522::UpdatePortAForHiZ(void)
{ {
BYTE ora = GetReg(SY6522::rORA); BYTE ora = GetReg(SY6522::rORA);
ora |= GetReg(SY6522::rDDRA) ^ 0xff; // for any DDRA bits set as input (logical 0), then set them in ORA ora |= GetReg(SY6522::rDDRA) ^ 0xff; // for any DDRA bits set as input (logical 0), then set them in ORA
SetRegORA(ora); // empirically bus floats high (or pull-up?) if no AY chip-selected (so DDRA=0x00 will read 0xFF as input) SetRegORA(ora); // Empirically Phasor's 6522-AY8913 bus floats high (or pull-up?) if no AY chip-selected (so DDRA=0x00 will read 0xFF as input)
} }
void SY6522::UpdateIFR(BYTE clr_ifr, BYTE set_ifr /*= 0*/) void SY6522::UpdateIFR(BYTE clr_ifr, BYTE set_ifr /*= 0*/)