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Fixed timing for 6502 opcodes: rol abs,x; lsr abs,x; ror abs,x. (Fixes #801)
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@ -120,7 +120,7 @@ static DWORD Cpu6502(DWORD uTotalCycles, const bool bVideoUpdate)
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case 0x3B: $ ABSY_CONST RLA CYC(7) break;
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case 0x3C: $ ABSX_OPT NOP CYC(4) break;
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case 0x3D: ABSX_OPT AND CYC(4) break;
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case 0x3E: ABSX_CONST ROLn CYC(6) break;
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case 0x3E: ABSX_CONST ROLn CYC(7) break;
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case 0x3F: $ ABSX_CONST RLA CYC(7) break;
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case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
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case 0x41: idx EOR CYC(6) break;
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@ -152,7 +152,7 @@ static DWORD Cpu6502(DWORD uTotalCycles, const bool bVideoUpdate)
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case 0x5B: $ ABSY_CONST LSE CYC(7) break;
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case 0x5C: $ ABSX_OPT NOP CYC(4) break;
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case 0x5D: ABSX_OPT EOR CYC(4) break;
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case 0x5E: ABSX_CONST LSRn CYC(6) break;
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case 0x5E: ABSX_CONST LSRn CYC(7) break;
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case 0x5F: $ ABSX_CONST LSE CYC(7) break;
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case 0x60: RTS CYC(6) break;
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case 0x61: idx ADCn CYC(6) break;
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@ -184,7 +184,7 @@ static DWORD Cpu6502(DWORD uTotalCycles, const bool bVideoUpdate)
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case 0x7B: $ ABSY_CONST RRA CYC(7) break;
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case 0x7C: $ ABSX_OPT NOP CYC(4) break;
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case 0x7D: ABSX_OPT ADCn CYC(4) break;
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case 0x7E: ABSX_CONST RORn CYC(6) break;
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case 0x7E: ABSX_CONST RORn CYC(7) break;
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case 0x7F: $ ABSX_CONST RRA CYC(7) break;
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case 0x80: $ IMM NOP CYC(2) break;
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case 0x81: idx STA CYC(6) break;
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@ -374,7 +374,7 @@ const BYTE g_OpcodeTimings[256][4] =
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{7,7,1,1}, // 3B
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{4,5,4,5}, // 3C
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{4,5,4,5}, // 3D
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{6,6,6,7}, // 3E
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{7,7,6,7}, // 3E
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{7,7,1,1}, // 3F
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{6,6,6,6}, // 40
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{6,6,6,6}, // 41
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@ -406,7 +406,7 @@ const BYTE g_OpcodeTimings[256][4] =
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{7,7,1,1}, // 5B
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{4,5,8,8}, // 5C
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{4,5,4,5}, // 5D
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{6,6,6,7}, // 5E
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{7,7,6,7}, // 5E
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{7,7,1,1}, // 5F
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{6,6,6,6}, // 60
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{6,6,6,6}, // 61
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@ -438,7 +438,7 @@ const BYTE g_OpcodeTimings[256][4] =
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{7,7,1,1}, // 7B
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{4,5,6,6}, // 7C
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{4,5,4,5}, // 7D
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{6,6,6,7}, // 7E
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{7,7,6,7}, // 7E
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{7,7,1,1}, // 7F
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{2,2,3,3}, // 80
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{6,6,6,6}, // 81
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