diff --git a/source/CPU/cpu6502.h b/source/CPU/cpu6502.h
index 54f70219..98df871c 100644
--- a/source/CPU/cpu6502.h
+++ b/source/CPU/cpu6502.h
@@ -202,7 +202,7 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
 		case 0x90:   REL BCC	CYC(2)  break;
 		case 0x91:   INDY_FAST STA	CYC(6)  break;
 		case 0x92: $     HLT	CYC(2)  break;
-		case 0x93: $ INDY_INV AXA	CYC(6)  break; // invalid
+		case 0x93: $ INDY_FAST AXA	CYC(6)  break; // invalid
 		case 0x94:   zpx STY	CYC(4)  break;
 		case 0x95:   zpx STA	CYC(4)  break;
 		case 0x96:   zpy STX	CYC(4)  break;
@@ -214,7 +214,7 @@ static DWORD Cpu6502 (DWORD uTotalCycles)
 		case 0x9C: $ ABSX_FAST SAY	CYC(5)  break; // invalid
 		case 0x9D:   ABSX_FAST STA	CYC(5)  break;
 		case 0x9E: $ ABSY_FAST XAS	CYC(5)  break;
-		case 0x9F: $ ABSY_INV AXA	CYC(5)  break;
+		case 0x9F: $ ABSY_FAST AXA	CYC(5)  break;
 		case 0xA0:   IMM LDY	CYC(2)  break;
 		case 0xA1:   idx LDA	CYC(6)  break;
 		case 0xA2:   IMM LDX	CYC(2)  break;
diff --git a/source/CPU/cpu_general.inl b/source/CPU/cpu_general.inl
index a26f4406..b6846045 100644
--- a/source/CPU/cpu_general.inl
+++ b/source/CPU/cpu_general.inl
@@ -93,9 +93,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 #define CHECK_PAGE_CHANGE	if ((base ^ addr) & 0xFF00)			\
 									uExtraCycles=1;
 
-#define CHECK_PAGE_CHANGE_INV	if ((base ^ addr) & 0xFF00)			\
-									uExtraCycles=1;	/* Reuse as flag to opcode to replace hi-addr! */
-
 /****************************************************************************
 *
 *  ADDRESSING MODE MACROS
@@ -110,12 +107,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 
 #define ABSY_SLOW base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
 #define ABSY_FAST base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2;
-#define ABSY_INV  base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE_INV;
 
 // NMOS read-modify-write opcodes (asl/dec/inc abs,x) don't take an extra cycle if page-crossing (GH#271)
 #define ABSX_NMOS_RMW base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2;
 
-// TODO Optimization Note: uExtraCycles = ((base & 0xFF) + 1) >> 8;
+// TODO Optimization Note (just for IABSCMOS): uExtraCycles = ((base & 0xFF) + 1) >> 8;
 #define IABSCMOS base = *(LPWORD)(mem+regs.pc);	                          \
 		 addr = *(LPWORD)(mem+base);		                  \
 		 if ((base & 0xFF) == 0xFF) uExtraCycles=1;		  \
@@ -123,10 +119,12 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 #define IABSNMOS base = *(LPWORD)(mem+regs.pc);	                          \
 		 if ((base & 0xFF) == 0xFF)				  \
 		       addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8);\
-		   else                                                   \
+		 else                                                   \
 		       addr = *(LPWORD)(mem+base);                        \
 		 regs.pc += 2;
+
 #define IMM	 addr = regs.pc++;
+
 #define INDX	 base = ((*(mem+regs.pc++))+regs.x) & 0xFF;          \
 		 if (base == 0xFF)                                   \
 		     addr = *(mem+0xFF)+(((WORD)*mem)<<8);           \
@@ -146,19 +144,13 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 		     base = *(LPWORD)(mem+*(mem+regs.pc));           \
 		 regs.pc++;                                          \
 		 addr = base+(WORD)regs.y;
-#define INDY_INV	 if (*(mem+regs.pc) == 0xFF)             /*FAST: no extra cycle for page-crossing*/ \
-		     base = *(mem+0xFF)+(((WORD)*mem)<<8);           \
-		 else                                                \
-		     base = *(LPWORD)(mem+*(mem+regs.pc));           \
-		 regs.pc++;                                          \
-		 addr = base+(WORD)regs.y;                           \
-		 CHECK_PAGE_CHANGE_INV;
 
 #define IZPG	 base = *(mem+regs.pc++);                            \
 		 if (base == 0xFF)                                   \
 		     addr = *(mem+0xFF)+(((WORD)*mem)<<8);           \
 		 else                                                \
 		     addr = *(LPWORD)(mem+base);
+
 #define REL	 addr = (signed char)*(mem+regs.pc++);
 
 // TODO Optimization Note:
diff --git a/source/CPU/cpu_instructions.inl b/source/CPU/cpu_instructions.inl
index 624ac82d..89eb25f4 100644
--- a/source/CPU/cpu_instructions.inl
+++ b/source/CPU/cpu_instructions.inl
@@ -296,7 +296,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 		 SETNZ(regs.a)
 #define AXA	 /*bSlowerOnPagecross = 0;*/	    \
 		 val = regs.a & regs.x & (((base >> 8) + 1) & 0xFF);	    \
-		 if (uExtraCycles) {addr = (val<<8) | (addr&0xff); uExtraCycles = 0;} /* NB. Use 'uExtraCycles' to flag page-cross only */ \
+		 if ((base ^ addr) >> 8) {addr = (val<<8) | (addr&0xff);} /* GH#282 */	\
 		 WRITE(val)
 #define AXS	 /*bSlowerOnPagecross = 0;*/						    \
 		 WRITE(regs.a & regs.x)
@@ -552,6 +552,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 		 SETNZ(regs.x)
 #define SAY	 /*bSlowerOnPagecross = 0;*/						    \
 		 val = regs.y & (((base >> 8) + 1) & 0xFF);		    \
+		 if ((base ^ addr) >> 8) {addr = (val<<8) | (addr&0xff);} /* GH#282 */	\
 		 WRITE(val)
 #define SBC_NMOS /*bSlowerOnPagecross = 1;*/						    \
 		 temp = READ;						    \
@@ -635,6 +636,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 		 val = regs.a & regs.x;					    \
 		 regs.sp = 0x100 | val;					    \
 		 val &= (((base >> 8) + 1) & 0xFF);			    \
+		 if ((base ^ addr) >> 8) {addr = (val<<8) | (addr&0xff);} /* GH#282 */	\
 		 WRITE(val)
 #define TAX	 regs.x = regs.a;					    \
 		 SETNZ(regs.x)
@@ -662,5 +664,5 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 		 SETNZ(regs.a)
 #define XAS	 /*bSlowerOnPagecross = 0;*/						    \
 		 val = regs.x & (((base >> 8) + 1) & 0xFF);		    \
+		 if ((base ^ addr) >> 8) {addr = (val<<8) | (addr&0xff);} /* GH#282 */	\
 		 WRITE(val)
-