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MegaAudio card: Reads of 6522 IRB & IRA always return 0x00
. generalise the implementation: move AY READ logic down to 6522 read
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43daabec54
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@ -345,9 +345,11 @@ BYTE SY6522::Read(BYTE nReg)
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{
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{
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case 0x00: // IRB
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case 0x00: // IRB
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nValue = m_regs.ORB | (m_regs.DDRB ^ 0xff); // Input bits read back as 1's (GH#1260)
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nValue = m_regs.ORB | (m_regs.DDRB ^ 0xff); // Input bits read back as 1's (GH#1260)
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if (m_isMegaAudio) nValue = 0x00; // MegaAudio: IRB just reads as $00
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break;
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break;
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case 0x01: // IRA
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case 0x01: // IRA
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nValue = m_regs.ORA | (m_isBusDriven ? 0x00 : (m_regs.DDRA ^ 0xff)); // NB. Inputs bits driven by AY8913 if in PSG READ mode
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nValue = m_regs.ORA | (m_isBusDriven ? 0x00 : (m_regs.DDRA ^ 0xff)); // NB. Inputs bits driven by AY8913 if in PSG READ mode
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if (m_isMegaAudio) nValue = 0x00; // MegaAudio: IRA just reads as $00
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break;
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break;
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case 0x02: // DDRB
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case 0x02: // DDRB
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nValue = m_regs.DDRB;
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nValue = m_regs.DDRB;
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@ -313,18 +313,10 @@ void MockingboardCard::AY8913_Write(BYTE subunit, BYTE ay, BYTE value)
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{
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{
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bool busState = true; // Initially default to true
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bool busState = true; // Initially default to true
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if (QueryType() != CT_MegaAudio)
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if (pMB->isChipSelected[ay] && pMB->isAYLatchedAddressValid[ay])
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{
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r6522.SetRegIRA(AYReadReg(subunit, ay, pMB->nAYCurrentRegister[ay]) & (r6522.GetReg(SY6522::rDDRA) ^ 0xff));
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if (pMB->isChipSelected[ay] && pMB->isAYLatchedAddressValid[ay])
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r6522.SetRegIRA(AYReadReg(subunit, ay, pMB->nAYCurrentRegister[ay]) & (r6522.GetReg(SY6522::rDDRA) ^ 0xff));
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else
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busState = false;
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}
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else
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else
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{
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busState = false;
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r6522.SetRegIRA(0x00); // Reads not supported - always return 0x00.
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busState = true;
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}
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if (m_phasorEnable && m_phasorMode == PH_Phasor) // GH#1192
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if (m_phasorEnable && m_phasorMode == PH_Phasor) // GH#1192
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{
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{
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