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Corrected CLK_Z80 value
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@ -8,7 +8,7 @@ const double CLK_6502 = ((_M14 * 65.0) / 912.0); // 65 cycles per 912 14M clocks
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// The effective Z-80 clock rate is 2.041MHz
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// The effective Z-80 clock rate is 2.041MHz
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// See: http://www.apple2info.net/hardware/softcard/SC-SWHW_a2in.pdf
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// See: http://www.apple2info.net/hardware/softcard/SC-SWHW_a2in.pdf
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const double CLK_Z80 = 2.041e6;
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const double CLK_Z80 = (CLK_6502 * 2);
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const UINT uCyclesPerLine = 65; // 25 cycles of HBL & 40 cycles of HBL'
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const UINT uCyclesPerLine = 65; // 25 cycles of HBL & 40 cycles of HBL'
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const UINT uVisibleLinesPerFrame = 64*3; // 192
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const UINT uVisibleLinesPerFrame = 64*3; // 192
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