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synced 2024-06-13 02:29:40 +00:00
Fix save-state bug:
. Would always save physical 4K BANK1 (main or aux) in memmain[] or memaux[]. . If this 4K BANK1 was dirty at $D000, then these dirty changes would be lost! - NB. If 4K BANK2 was mapped into $D000 then this was fine. Reproducible by saving state in Manic Mansion, when transitioning between scenes (eg. moving up/down stairs).
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tomch
parent
cda9ed5c72
commit
7d8035bc70
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@ -39,8 +39,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// Memory Flag
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#define MF_80STORE 0x00000001
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#define MF_ALTZP 0x00000002
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#define MF_AUXREAD 0x00000004
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#define MF_AUXWRITE 0x00000008
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#define MF_AUXREAD 0x00000004 // RAMRD
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#define MF_AUXWRITE 0x00000008 // RAMWRT
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#define MF_BANK2 0x00000010
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#define MF_HIGHRAM 0x00000020
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#define MF_HIRES 0x00000040
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@ -114,6 +114,38 @@ SOFT SWITCH STATUS FLAGS
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//-----------------------------------------------------------------------------
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// Notes
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// -----
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//
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// mem
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// - a copy of the memimage ptr
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//
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// memimage
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// - 64KB
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// - reflects the current readable memory in the 6502's 64K address space
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// . excludes $Cxxx I/O memory
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// . could be a mix of RAM/ROM, main/aux, etc
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//
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// memmain, memaux
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// - physical contiguous 64KB RAM for main & aux respectively
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//
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// memwrite
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// - 1 ptr entry per 256-byte page
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// - used to write to a page
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//
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// memdirty
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// - 1 byte entry per 256-byte page
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// - set when a write occurs to a 256-byte page
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//
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// memshadow
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// - 1 ptr entry per 256-byte page
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// - reflects how 'mem' is setup
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// . EG: if ALTZP=1, then:
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// . mem will have copies of memaux's ZP & stack
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// . memshadow[0] = &memaux[0x0000]
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// . memshadow[1] = &memaux[0x0100]
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//
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//static DWORD imagemode;
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static LPBYTE memshadow[0x100];
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LPBYTE memwrite[0x100];
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@ -143,7 +175,7 @@ static LPBYTE pCxRomInternal = NULL;
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static LPBYTE pCxRomPeripheral = NULL;
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static DWORD memmode = MF_BANK2 | MF_SLOTCXROM | MF_WRITERAM;
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static BOOL modechanging = 0;
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static BOOL modechanging = 0; // An Optimisation: means delay calling UpdatePaging() for 1 instruction
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static BOOL Pravets8charmode = 0;
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MemoryInitPattern_e g_eMemoryInitPattern = MIP_FF_FF_00_00;
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@ -720,7 +752,7 @@ static bool IsCardInSlot(const UINT uSlot)
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//===========================================================================
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//// Only called by MemSetFastPaging()
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//void BackMainImage ()
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//static void BackMainImage ()
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//{
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// for (UINT loop = 0; loop < 256; loop++)
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// {
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@ -733,13 +765,45 @@ static bool IsCardInSlot(const UINT uSlot)
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//===========================================================================
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static void SetMemMode(const DWORD uNewMemMode)
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{
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#if defined(_DEBUG) && 0
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static DWORD dwOldDiff = 0;
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DWORD dwDiff = memmode ^ uNewMemMode;
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dwDiff &= ~(MF_SLOTC3ROM | MF_SLOTCXROM);
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if (dwOldDiff != dwDiff)
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{
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dwOldDiff = dwDiff;
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char szStr[100];
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char* psz = szStr;
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psz += sprintf(psz, "diff = %08X ", dwDiff);
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psz += sprintf(psz, "80=%d " , SW_80STORE ? 1 : 0);
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psz += sprintf(psz, "ALTZP=%d ", SW_ALTZP ? 1 : 0);
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psz += sprintf(psz, "AUXR=%d " , SW_AUXREAD ? 1 : 0);
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psz += sprintf(psz, "AUXW=%d " , SW_AUXWRITE ? 1 : 0);
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psz += sprintf(psz, "BANK2=%d ", SW_BANK2 ? 1 : 0);
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psz += sprintf(psz, "HIRAM=%d ", SW_HIGHRAM ? 1 : 0);
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psz += sprintf(psz, "HIRES=%d ", SW_HIRES ? 1 : 0);
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psz += sprintf(psz, "PAGE2=%d ", SW_PAGE2 ? 1 : 0);
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psz += sprintf(psz, "C3=%d " , SW_SLOTC3ROM ? 1 : 0);
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psz += sprintf(psz, "CX=%d " , SW_SLOTCXROM ? 1 : 0);
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psz += sprintf(psz, "WRAM=%d " , SW_WRITERAM ? 1 : 0);
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psz += sprintf(psz, "\n");
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OutputDebugString(szStr);
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}
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#endif
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memmode = uNewMemMode;
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}
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//===========================================================================
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void ResetPaging (BOOL initialize)
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{
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//if (!initialize)
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// MemSetFastPaging(0);
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lastwriteram = 0;
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memmode = MF_BANK2 | MF_SLOTCXROM | MF_WRITERAM;
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SetMemMode(MF_BANK2 | MF_SLOTCXROM | MF_WRITERAM);
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UpdatePaging(initialize, 0);
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}
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@ -886,6 +950,11 @@ static void UpdatePaging (BOOL initialize, BOOL updatewriteonly /*Always zero*/)
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// MOVE MEMORY BACK AND FORTH AS NECESSARY BETWEEN THE SHADOW AREAS AND
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// THE MAIN RAM IMAGE TO KEEP BOTH SETS OF MEMORY CONSISTENT WITH THE NEW
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// PAGING SHADOW TABLE
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//
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// NB. the condition 'loop <= 1' is there because:
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// . Page0 (ZP) : memdirty[0] is set when the 6502 CPU does a ZP-write, but perhaps older versions didn't set this flag (eg. the asm version?).
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// . Page1 (stack) : memdirty[1] is NOT set when the 6502 CPU writes to this page with JSR, etc.
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//if (!updatewriteonly)
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{
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for (loop = 0x00; loop < 0x100; loop++)
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@ -992,10 +1061,18 @@ bool MemCheckSLOTCXROM()
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}
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//===========================================================================
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LPBYTE MemGetAuxPtr (WORD offset)
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LPBYTE MemGetAuxPtr(const WORD offset)
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{
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if ((offset & 0xF000) == 0xC000) // Requesting RAM at physical addr $C000 (ie. 4K RAM BANK1)
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{
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const BYTE bank1page = (offset >> 8) & 0xF;
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if (memshadow[0xD0+bank1page] == memaux+(0xC0+bank1page)*256) // 'mem' has (a potentially dirty) aux 4K RAM BANK1 mapped in at $D000
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return mem+offset+0x1000; // Return ptr to $Dxxx address
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}
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LPBYTE lpMem = (memshadow[(offset >> 8)] == (memaux+(offset & 0xFF00)))
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? mem+offset
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? mem+offset // Return 'mem' copy if possible, as page could be dirty
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: memaux+offset;
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#ifdef RAMWORKS
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@ -1014,11 +1091,19 @@ LPBYTE MemGetAuxPtr (WORD offset)
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}
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//===========================================================================
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LPBYTE MemGetMainPtr (WORD offset)
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LPBYTE MemGetMainPtr(const WORD offset)
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{
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return (memshadow[(offset >> 8)] == (memmain+(offset & 0xFF00)))
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? mem+offset
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: memmain+offset;
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if ((offset & 0xF000) == 0xC000) // Requesting RAM at physical addr $C000 (ie. 4K RAM BANK1)
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{
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const BYTE bank1page = (offset >> 8) & 0xF;
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if (memshadow[0xD0+bank1page] == memmain+(0xC0+bank1page)*256) // 'mem' has (a potentially dirty) main 4K RAM BANK1 mapped in at $D000
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return mem+offset+0x1000; // Return ptr to $Dxxx address
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}
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return (memshadow[(offset >> 8)] == (memmain+(offset & 0xFF00)))
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? mem+offset // Return 'mem' copy if possible, as page could be dirty
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: memmain+offset;
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}
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//===========================================================================
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@ -1371,36 +1456,36 @@ BYTE __stdcall MemSetPaging (WORD programcounter, WORD address, BYTE write, BYTE
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if ((address >= 0x80) && (address <= 0x8F))
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{
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BOOL writeram = (address & 1);
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memmode &= ~(MF_BANK2 | MF_HIGHRAM | MF_WRITERAM);
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SetMemMode(memmode & ~(MF_BANK2 | MF_HIGHRAM | MF_WRITERAM));
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lastwriteram = 1; // note: because diags.do doesn't set switches twice!
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if (lastwriteram && writeram)
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memmode |= MF_WRITERAM;
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SetMemMode(memmode | MF_WRITERAM);
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if (!(address & 8))
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memmode |= MF_BANK2;
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SetMemMode(memmode | MF_BANK2);
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if (((address & 2) >> 1) == (address & 1))
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memmode |= MF_HIGHRAM;
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SetMemMode(memmode | MF_HIGHRAM);
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lastwriteram = writeram;
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}
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else if (!IS_APPLE2)
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{
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switch (address)
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{
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case 0x00: memmode &= ~MF_80STORE; break;
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case 0x01: memmode |= MF_80STORE; break;
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case 0x02: memmode &= ~MF_AUXREAD; break;
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case 0x03: memmode |= MF_AUXREAD; break;
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case 0x04: memmode &= ~MF_AUXWRITE; break;
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case 0x05: memmode |= MF_AUXWRITE; break;
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case 0x06: memmode |= MF_SLOTCXROM; break;
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case 0x07: memmode &= ~MF_SLOTCXROM; break;
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case 0x08: memmode &= ~MF_ALTZP; break;
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case 0x09: memmode |= MF_ALTZP; break;
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case 0x0A: memmode &= ~MF_SLOTC3ROM; break;
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case 0x0B: memmode |= MF_SLOTC3ROM; break;
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case 0x54: memmode &= ~MF_PAGE2; break;
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case 0x55: memmode |= MF_PAGE2; break;
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case 0x56: memmode &= ~MF_HIRES; break;
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case 0x57: memmode |= MF_HIRES; break;
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case 0x00: SetMemMode(memmode & ~MF_80STORE); break;
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case 0x01: SetMemMode(memmode | MF_80STORE); break;
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case 0x02: SetMemMode(memmode & ~MF_AUXREAD); break;
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case 0x03: SetMemMode(memmode | MF_AUXREAD); break;
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case 0x04: SetMemMode(memmode & ~MF_AUXWRITE); break;
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case 0x05: SetMemMode(memmode | MF_AUXWRITE); break;
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case 0x06: SetMemMode(memmode | MF_SLOTCXROM); break;
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case 0x07: SetMemMode(memmode & ~MF_SLOTCXROM); break;
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case 0x08: SetMemMode(memmode & ~MF_ALTZP); break;
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case 0x09: SetMemMode(memmode | MF_ALTZP); break;
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case 0x0A: SetMemMode(memmode & ~MF_SLOTC3ROM); break;
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case 0x0B: SetMemMode(memmode | MF_SLOTC3ROM); break;
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case 0x54: SetMemMode(memmode & ~MF_PAGE2); break;
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case 0x55: SetMemMode(memmode | MF_PAGE2); break;
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case 0x56: SetMemMode(memmode & ~MF_HIRES); break;
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case 0x57: SetMemMode(memmode | MF_HIRES); break;
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#ifdef RAMWORKS
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case 0x71: // extended memory aux page number
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case 0x73: // Ramworks III set aux page number
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@ -1422,6 +1507,9 @@ BYTE __stdcall MemSetPaging (WORD programcounter, WORD address, BYTE write, BYTE
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// IF THE EMULATED PROGRAM HAS JUST UPDATE THE MEMORY WRITE MODE AND IS
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// ABOUT TO UPDATE THE MEMORY READ MODE, HOLD OFF ON ANY PROCESSING UNTIL
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// IT DOES SO.
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//
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// NB. A 6502 interrupt occurring between these memory write & read updates could lead to incorrect behaviour.
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// - although any date-race is probably a bug in the 6502 code too.
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if ((address >= 4) && (address <= 5) &&
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((*(LPDWORD)(mem+programcounter) & 0x00FFFEFF) == 0x00C0028D)) {
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modechanging = 1;
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@ -1520,6 +1608,10 @@ LPVOID MemGetSlotParameters (UINT uSlot)
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//===========================================================================
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// NB. Don't need to save 'modechanging', as this is just an optimisation to save calling UpdatePaging() twice.
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// . If we were to save the state when 'modechanging' is set, then on restoring the state, the 6502 code will immediately update the read memory mode.
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// . This will work correctly.
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DWORD MemGetSnapshot(SS_BaseMemory* pSS)
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{
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pSS->dwMemMode = memmode;
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@ -1536,11 +1628,12 @@ DWORD MemGetSnapshot(SS_BaseMemory* pSS)
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DWORD MemSetSnapshot(SS_BaseMemory* pSS)
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{
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memmode = pSS->dwMemMode;
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SetMemMode(pSS->dwMemMode);
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lastwriteram = pSS->bLastWriteRam;
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memcpy(memmain, pSS->nMemMain, nMemMainSize);
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memcpy(memaux, pSS->nMemAux, nMemAuxSize);
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memset(memdirty, 0, 0x100);
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//
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@ -36,8 +36,8 @@ void RegisterIoHandler(UINT uSlot, iofunction IOReadC0, iofunction IOWriteC0, io
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void MemDestroy ();
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bool MemGet80Store();
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bool MemCheckSLOTCXROM();
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LPBYTE MemGetAuxPtr (WORD);
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LPBYTE MemGetMainPtr (WORD);
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LPBYTE MemGetAuxPtr(const WORD);
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LPBYTE MemGetMainPtr(const WORD);
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LPBYTE MemGetBankPtr(const UINT nBank);
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LPBYTE MemGetCxRomPeripheral();
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void MemInitialize ();
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