diff --git a/source/CPU/cpu6502.h b/source/CPU/cpu6502.h index e7039c07..1815e941 100644 --- a/source/CPU/cpu6502.h +++ b/source/CPU/cpu6502.h @@ -100,7 +100,7 @@ static DWORD Cpu6502 (DWORD uTotalCycles) case 0x2A: rol CYC(2) break; case 0x2B: $ IMM ANC CYC(2) break; case 0x2C: ABS BIT CYC(4) break; - case 0x2D: ABS AND CYC(2) break; + case 0x2D: ABS AND CYC(4) break; case 0x2E: ABS ROLn CYC(6) break; case 0x2F: $ ABS RLA CYC(6) break; case 0x30: REL BMI CYC(2) break; diff --git a/source/CPU/cpu65C02.h b/source/CPU/cpu65C02.h index 0a547dca..2cafc375 100644 --- a/source/CPU/cpu65C02.h +++ b/source/CPU/cpu65C02.h @@ -61,259 +61,259 @@ static DWORD Cpu65C02 (DWORD uTotalCycles) case 0x00: BRK CYC(7) break; case 0x01: idx ORA CYC(6) break; case 0x02: $ IMM NOP CYC(2) break; - case 0x03: $ NOP CYC(2) break; + case 0x03: $ NOP CYC(1) break; case 0x04: ZPG TSB CYC(5) break; case 0x05: ZPG ORA CYC(3) break; case 0x06: ZPG ASLc CYC(5) break; - case 0x07: $ NOP CYC(2) break; + case 0x07: $ NOP CYC(1) break; case 0x08: PHP CYC(3) break; case 0x09: IMM ORA CYC(2) break; case 0x0A: asl CYC(2) break; - case 0x0B: $ NOP CYC(2) break; + case 0x0B: $ NOP CYC(1) break; case 0x0C: ABS TSB CYC(6) break; case 0x0D: ABS ORA CYC(4) break; case 0x0E: ABS ASLc CYC(6) break; - case 0x0F: $ NOP CYC(2) break; + case 0x0F: $ NOP CYC(1) break; case 0x10: REL BPL CYC(2) break; case 0x11: INDY_OPT ORA CYC(5) break; case 0x12: izp ORA CYC(5) break; - case 0x13: $ NOP CYC(2) break; + case 0x13: $ NOP CYC(1) break; case 0x14: ZPG TRB CYC(5) break; case 0x15: zpx ORA CYC(4) break; case 0x16: zpx ASLc CYC(6) break; - case 0x17: $ NOP CYC(2) break; + case 0x17: $ NOP CYC(1) break; case 0x18: CLC CYC(2) break; case 0x19: ABSY_OPT ORA CYC(4) break; case 0x1A: INA CYC(2) break; - case 0x1B: $ NOP CYC(2) break; + case 0x1B: $ NOP CYC(1) break; case 0x1C: ABS TRB CYC(6) break; case 0x1D: ABSX_OPT ORA CYC(4) break; case 0x1E: ABSX_OPT ASLc CYC(6) break; - case 0x1F: $ NOP CYC(2) break; + case 0x1F: $ NOP CYC(1) break; case 0x20: ABS JSR CYC(6) break; case 0x21: idx AND CYC(6) break; case 0x22: $ IMM NOP CYC(2) break; - case 0x23: $ NOP CYC(2) break; + case 0x23: $ NOP CYC(1) break; case 0x24: ZPG BIT CYC(3) break; case 0x25: ZPG AND CYC(3) break; case 0x26: ZPG ROLc CYC(5) break; - case 0x27: $ NOP CYC(2) break; + case 0x27: $ NOP CYC(1) break; case 0x28: PLP CYC(4) break; case 0x29: IMM AND CYC(2) break; case 0x2A: rol CYC(2) break; - case 0x2B: $ NOP CYC(2) break; + case 0x2B: $ NOP CYC(1) break; case 0x2C: ABS BIT CYC(4) break; - case 0x2D: ABS AND CYC(2) break; + case 0x2D: ABS AND CYC(4) break; case 0x2E: ABS ROLc CYC(6) break; - case 0x2F: $ NOP CYC(2) break; + case 0x2F: $ NOP CYC(1) break; case 0x30: REL BMI CYC(2) break; case 0x31: INDY_OPT AND CYC(5) break; case 0x32: izp AND CYC(5) break; - case 0x33: $ NOP CYC(2) break; + case 0x33: $ NOP CYC(1) break; case 0x34: zpx BIT CYC(4) break; case 0x35: zpx AND CYC(4) break; case 0x36: zpx ROLc CYC(6) break; - case 0x37: $ NOP CYC(2) break; + case 0x37: $ NOP CYC(1) break; case 0x38: SEC CYC(2) break; case 0x39: ABSY_OPT AND CYC(4) break; case 0x3A: DEA CYC(2) break; - case 0x3B: $ NOP CYC(2) break; + case 0x3B: $ NOP CYC(1) break; case 0x3C: ABSX_OPT BIT CYC(4) break; case 0x3D: ABSX_OPT AND CYC(4) break; case 0x3E: ABSX_OPT ROLc CYC(6) break; - case 0x3F: $ NOP CYC(2) break; + case 0x3F: $ NOP CYC(1) break; case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break; case 0x41: idx EOR CYC(6) break; case 0x42: $ IMM NOP CYC(2) break; - case 0x43: $ NOP CYC(2) break; + case 0x43: $ NOP CYC(1) break; case 0x44: $ ZPG NOP CYC(3) break; case 0x45: ZPG EOR CYC(3) break; case 0x46: ZPG LSRc CYC(5) break; - case 0x47: $ NOP CYC(2) break; + case 0x47: $ NOP CYC(1) break; case 0x48: PHA CYC(3) break; case 0x49: IMM EOR CYC(2) break; case 0x4A: lsr CYC(2) break; - case 0x4B: $ NOP CYC(2) break; + case 0x4B: $ NOP CYC(1) break; case 0x4C: ABS JMP CYC(3) break; case 0x4D: ABS EOR CYC(4) break; case 0x4E: ABS LSRc CYC(6) break; - case 0x4F: $ NOP CYC(2) break; + case 0x4F: $ NOP CYC(1) break; case 0x50: REL BVC CYC(2) break; case 0x51: INDY_OPT EOR CYC(5) break; case 0x52: izp EOR CYC(5) break; - case 0x53: $ NOP CYC(2) break; + case 0x53: $ NOP CYC(1) break; case 0x54: $ zpx NOP CYC(4) break; case 0x55: zpx EOR CYC(4) break; case 0x56: zpx LSRc CYC(6) break; - case 0x57: $ NOP CYC(2) break; + case 0x57: $ NOP CYC(1) break; case 0x58: CLI CYC(2) break; case 0x59: ABSY_OPT EOR CYC(4) break; case 0x5A: PHY CYC(3) break; - case 0x5B: $ NOP CYC(2) break; - case 0x5C: $ ABSX_OPT NOP CYC(8) break; + case 0x5B: $ NOP CYC(1) break; + case 0x5C: $ ABS NOP CYC(8) break; case 0x5D: ABSX_OPT EOR CYC(4) break; case 0x5E: ABSX_OPT LSRc CYC(6) break; - case 0x5F: $ NOP CYC(2) break; + case 0x5F: $ NOP CYC(1) break; case 0x60: RTS CYC(6) break; case 0x61: idx ADCc CYC(6) break; case 0x62: $ IMM NOP CYC(2) break; - case 0x63: $ NOP CYC(2) break; + case 0x63: $ NOP CYC(1) break; case 0x64: ZPG STZ CYC(3) break; case 0x65: ZPG ADCc CYC(3) break; case 0x66: ZPG RORc CYC(5) break; - case 0x67: $ NOP CYC(2) break; + case 0x67: $ NOP CYC(1) break; case 0x68: PLA CYC(4) break; case 0x69: IMM ADCc CYC(2) break; case 0x6A: ror CYC(2) break; - case 0x6B: $ NOP CYC(2) break; + case 0x6B: $ NOP CYC(1) break; case 0x6C: IABS_CMOS JMP CYC(6) break; case 0x6D: ABS ADCc CYC(4) break; case 0x6E: ABS RORc CYC(6) break; - case 0x6F: $ NOP CYC(2) break; + case 0x6F: $ NOP CYC(1) break; case 0x70: REL BVS CYC(2) break; case 0x71: INDY_OPT ADCc CYC(5) break; case 0x72: izp ADCc CYC(5) break; - case 0x73: $ NOP CYC(2) break; + case 0x73: $ NOP CYC(1) break; case 0x74: zpx STZ CYC(4) break; case 0x75: zpx ADCc CYC(4) break; case 0x76: zpx RORc CYC(6) break; - case 0x77: $ NOP CYC(2) break; + case 0x77: $ NOP CYC(1) break; case 0x78: SEI CYC(2) break; case 0x79: ABSY_OPT ADCc CYC(4) break; case 0x7A: PLY CYC(4) break; - case 0x7B: $ NOP CYC(2) break; + case 0x7B: $ NOP CYC(1) break; case 0x7C: IABSX JMP CYC(6) break; case 0x7D: ABSX_OPT ADCc CYC(4) break; case 0x7E: ABSX_OPT RORc CYC(6) break; - case 0x7F: $ NOP CYC(2) break; + case 0x7F: $ NOP CYC(1) break; case 0x80: REL BRA CYC(2) break; case 0x81: idx STA CYC(6) break; case 0x82: $ IMM NOP CYC(2) break; - case 0x83: $ NOP CYC(2) break; + case 0x83: $ NOP CYC(1) break; case 0x84: ZPG STY CYC(3) break; case 0x85: ZPG STA CYC(3) break; case 0x86: ZPG STX CYC(3) break; - case 0x87: $ NOP CYC(2) break; + case 0x87: $ NOP CYC(1) break; case 0x88: DEY CYC(2) break; case 0x89: IMM BITI CYC(2) break; case 0x8A: TXA CYC(2) break; - case 0x8B: $ NOP CYC(2) break; + case 0x8B: $ NOP CYC(1) break; case 0x8C: ABS STY CYC(4) break; case 0x8D: ABS STA CYC(4) break; case 0x8E: ABS STX CYC(4) break; - case 0x8F: $ NOP CYC(2) break; + case 0x8F: $ NOP CYC(1) break; case 0x90: REL BCC CYC(2) break; case 0x91: INDY_CONST STA CYC(6) break; case 0x92: izp STA CYC(5) break; - case 0x93: $ NOP CYC(2) break; + case 0x93: $ NOP CYC(1) break; case 0x94: zpx STY CYC(4) break; case 0x95: zpx STA CYC(4) break; case 0x96: zpy STX CYC(4) break; - case 0x97: $ NOP CYC(2) break; + case 0x97: $ NOP CYC(1) break; case 0x98: TYA CYC(2) break; case 0x99: ABSY_CONST STA CYC(5) break; case 0x9A: TXS CYC(2) break; - case 0x9B: $ NOP CYC(2) break; + case 0x9B: $ NOP CYC(1) break; case 0x9C: ABS STZ CYC(4) break; case 0x9D: ABSX_CONST STA CYC(5) break; case 0x9E: ABSX_CONST STZ CYC(5) break; - case 0x9F: $ NOP CYC(2) break; + case 0x9F: $ NOP CYC(1) break; case 0xA0: IMM LDY CYC(2) break; case 0xA1: idx LDA CYC(6) break; case 0xA2: IMM LDX CYC(2) break; - case 0xA3: $ NOP CYC(2) break; + case 0xA3: $ NOP CYC(1) break; case 0xA4: ZPG LDY CYC(3) break; case 0xA5: ZPG LDA CYC(3) break; case 0xA6: ZPG LDX CYC(3) break; - case 0xA7: $ NOP CYC(2) break; + case 0xA7: $ NOP CYC(1) break; case 0xA8: TAY CYC(2) break; case 0xA9: IMM LDA CYC(2) break; case 0xAA: TAX CYC(2) break; - case 0xAB: $ NOP CYC(2) break; + case 0xAB: $ NOP CYC(1) break; case 0xAC: ABS LDY CYC(4) break; case 0xAD: ABS LDA CYC(4) break; case 0xAE: ABS LDX CYC(4) break; - case 0xAF: $ NOP CYC(2) break; + case 0xAF: $ NOP CYC(1) break; case 0xB0: REL BCS CYC(2) break; case 0xB1: INDY_OPT LDA CYC(5) break; case 0xB2: izp LDA CYC(5) break; - case 0xB3: $ NOP CYC(2) break; + case 0xB3: $ NOP CYC(1) break; case 0xB4: zpx LDY CYC(4) break; case 0xB5: zpx LDA CYC(4) break; case 0xB6: zpy LDX CYC(4) break; - case 0xB7: $ NOP CYC(2) break; + case 0xB7: $ NOP CYC(1) break; case 0xB8: CLV CYC(2) break; case 0xB9: ABSY_OPT LDA CYC(4) break; case 0xBA: TSX CYC(2) break; - case 0xBB: $ NOP CYC(2) break; + case 0xBB: $ NOP CYC(1) break; case 0xBC: ABSX_OPT LDY CYC(4) break; case 0xBD: ABSX_OPT LDA CYC(4) break; case 0xBE: ABSY_OPT LDX CYC(4) break; - case 0xBF: $ NOP CYC(2) break; + case 0xBF: $ NOP CYC(1) break; case 0xC0: IMM CPY CYC(2) break; case 0xC1: idx CMP CYC(6) break; case 0xC2: $ IMM NOP CYC(2) break; - case 0xC3: $ NOP CYC(2) break; + case 0xC3: $ NOP CYC(1) break; case 0xC4: ZPG CPY CYC(3) break; case 0xC5: ZPG CMP CYC(3) break; case 0xC6: ZPG DEC CYC(5) break; - case 0xC7: $ NOP CYC(2) break; + case 0xC7: $ NOP CYC(1) break; case 0xC8: INY CYC(2) break; case 0xC9: IMM CMP CYC(2) break; case 0xCA: DEX CYC(2) break; - case 0xCB: $ NOP CYC(2) break; + case 0xCB: $ NOP CYC(1) break; case 0xCC: ABS CPY CYC(4) break; case 0xCD: ABS CMP CYC(4) break; case 0xCE: ABS DEC CYC(6) break; - case 0xCF: $ NOP CYC(2) break; + case 0xCF: $ NOP CYC(1) break; case 0xD0: REL BNE CYC(2) break; case 0xD1: INDY_OPT CMP CYC(5) break; case 0xD2: izp CMP CYC(5) break; - case 0xD3: $ NOP CYC(2) break; + case 0xD3: $ NOP CYC(1) break; case 0xD4: $ zpx NOP CYC(4) break; case 0xD5: zpx CMP CYC(4) break; case 0xD6: zpx DEC CYC(6) break; - case 0xD7: $ NOP CYC(2) break; + case 0xD7: $ NOP CYC(1) break; case 0xD8: CLD CYC(2) break; case 0xD9: ABSY_OPT CMP CYC(4) break; case 0xDA: PHX CYC(3) break; - case 0xDB: $ NOP CYC(2) break; - case 0xDC: $ ABSX_OPT NOP CYC(4) break; + case 0xDB: $ NOP CYC(1) break; + case 0xDC: $ ABS LDD CYC(4) break; case 0xDD: ABSX_OPT CMP CYC(4) break; case 0xDE: ABSX_CONST DEC CYC(7) break; - case 0xDF: $ NOP CYC(2) break; + case 0xDF: $ NOP CYC(1) break; case 0xE0: IMM CPX CYC(2) break; case 0xE1: idx SBCc CYC(6) break; case 0xE2: $ IMM NOP CYC(2) break; - case 0xE3: $ NOP CYC(2) break; + case 0xE3: $ NOP CYC(1) break; case 0xE4: ZPG CPX CYC(3) break; case 0xE5: ZPG SBCc CYC(3) break; case 0xE6: ZPG INC CYC(5) break; - case 0xE7: $ NOP CYC(2) break; + case 0xE7: $ NOP CYC(1) break; case 0xE8: INX CYC(2) break; case 0xE9: IMM SBCc CYC(2) break; case 0xEA: NOP CYC(2) break; - case 0xEB: $ NOP CYC(2) break; + case 0xEB: $ NOP CYC(1) break; case 0xEC: ABS CPX CYC(4) break; case 0xED: ABS SBCc CYC(4) break; case 0xEE: ABS INC CYC(6) break; - case 0xEF: $ NOP CYC(2) break; + case 0xEF: $ NOP CYC(1) break; case 0xF0: REL BEQ CYC(2) break; case 0xF1: INDY_OPT SBCc CYC(5) break; case 0xF2: izp SBCc CYC(5) break; - case 0xF3: $ NOP CYC(2) break; + case 0xF3: $ NOP CYC(1) break; case 0xF4: $ zpx NOP CYC(4) break; case 0xF5: zpx SBCc CYC(4) break; case 0xF6: zpx INC CYC(6) break; - case 0xF7: $ NOP CYC(2) break; + case 0xF7: $ NOP CYC(1) break; case 0xF8: SED CYC(2) break; case 0xF9: ABSY_OPT SBCc CYC(4) break; case 0xFA: PLX CYC(4) break; - case 0xFB: $ NOP CYC(2) break; - case 0xFC: $ ABSX_OPT NOP CYC(4) break; + case 0xFB: $ NOP CYC(1) break; + case 0xFC: $ ABS LDD CYC(4) break; case 0xFD: ABSX_OPT SBCc CYC(4) break; case 0xFE: ABSX_CONST INC CYC(7) break; - case 0xFF: $ NOP CYC(2) break; + case 0xFF: $ NOP CYC(1) break; } #undef $ } diff --git a/source/CPU/cpu_instructions.inl b/source/CPU/cpu_instructions.inl index 2fc4b2e1..8daa6178 100644 --- a/source/CPU/cpu_instructions.inl +++ b/source/CPU/cpu_instructions.inl @@ -402,6 +402,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA #define LDA /*bSlowerOnPagecross = 1;*/ \ regs.a = READ; \ SETNZ(regs.a) +#define LDD /*Undocumented 65C02: LoaD and Discard*/ \ + READ; #define LDX /*bSlowerOnPagecross = 1;*/ \ regs.x = READ; \ SETNZ(regs.x) diff --git a/test/TestCPU6502/TestCPU6502.cpp b/test/TestCPU6502/TestCPU6502.cpp index e5fe5bb9..30147f82 100644 --- a/test/TestCPU6502/TestCPU6502.cpp +++ b/test/TestCPU6502/TestCPU6502.cpp @@ -312,259 +312,259 @@ const BYTE g_OpcodeTimings[256][4] = {7,7,7,7}, // 00 {6,6,6,6}, // 01 {2,2,2,2}, // 02 - {8,8,2,2}, // 03 + {8,8,1,1}, // 03 {3,3,5,5}, // 04 {3,3,3,3}, // 05 {5,5,5,5}, // 06 - {5,5,2,2}, // 07 + {5,5,1,1}, // 07 {3,3,3,3}, // 08 {2,2,2,2}, // 09 {2,2,2,2}, // 0A - {2,2,2,2}, // 0B + {2,2,1,1}, // 0B {4,5,6,6}, // 0C {4,4,4,4}, // 0D {6,6,6,6}, // 0E - {6,6,2,2}, // 0F + {6,6,1,1}, // 0F {3,3,3,3}, // 10 {5,6,5,6}, // 11 {2,2,5,5}, // 12 - {8,8,2,2}, // 13 + {8,8,1,1}, // 13 {4,4,5,5}, // 14 {4,4,4,4}, // 15 {6,6,6,6}, // 16 - {6,6,2,2}, // 17 + {6,6,1,1}, // 17 {2,2,2,2}, // 18 {4,5,4,5}, // 19 {2,2,2,2}, // 1A - {7,7,2,2}, // 1B + {7,7,1,1}, // 1B {4,5,6,6}, // 1C {4,5,4,5}, // 1D {7,7,6,7}, // 1E - {7,7,2,2}, // 1F + {7,7,1,1}, // 1F {6,6,6,6}, // 20 {6,6,6,6}, // 21 {2,2,2,2}, // 22 - {8,8,2,2}, // 23 + {8,8,1,1}, // 23 {3,3,3,3}, // 24 {3,3,3,3}, // 25 {5,5,5,5}, // 26 - {5,5,2,2}, // 27 + {5,5,1,1}, // 27 {4,4,4,4}, // 28 {2,2,2,2}, // 29 {2,2,2,2}, // 2A - {2,2,2,2}, // 2B + {2,2,1,1}, // 2B {4,4,4,4}, // 2C - {2,2,2,2}, // 2D + {4,4,4,4}, // 2D {6,6,6,6}, // 2E - {6,6,2,2}, // 2F + {6,6,1,1}, // 2F {2,2,2,2}, // 30 {5,6,5,6}, // 31 {2,2,5,5}, // 32 - {8,8,2,2}, // 33 + {8,8,1,1}, // 33 {4,4,4,4}, // 34 {4,4,4,4}, // 35 {6,6,6,6}, // 36 - {6,6,2,2}, // 37 + {6,6,1,1}, // 37 {2,2,2,2}, // 38 {4,5,4,5}, // 39 {2,2,2,2}, // 3A - {7,7,2,2}, // 3B + {7,7,1,1}, // 3B {4,5,4,5}, // 3C {4,5,4,5}, // 3D {6,6,6,7}, // 3E - {7,7,2,2}, // 3F + {7,7,1,1}, // 3F {6,6,6,6}, // 40 {6,6,6,6}, // 41 {2,2,2,2}, // 42 - {8,8,2,2}, // 43 + {8,8,1,1}, // 43 {3,3,3,3}, // 44 {3,3,3,3}, // 45 {5,5,5,5}, // 46 - {5,5,2,2}, // 47 + {5,5,1,1}, // 47 {3,3,3,3}, // 48 {2,2,2,2}, // 49 {2,2,2,2}, // 4A - {2,2,2,2}, // 4B + {2,2,1,1}, // 4B {3,3,3,3}, // 4C {4,4,4,4}, // 4D {6,6,6,6}, // 4E - {6,6,2,2}, // 4F + {6,6,1,1}, // 4F {3,3,3,3}, // 50 {5,6,5,6}, // 51 {2,2,5,5}, // 52 - {8,8,2,2}, // 53 + {8,8,1,1}, // 53 {4,4,4,4}, // 54 {4,4,4,4}, // 55 {6,6,6,6}, // 56 - {6,6,2,2}, // 57 + {6,6,1,1}, // 57 {2,2,2,2}, // 58 {4,5,4,5}, // 59 {2,2,3,3}, // 5A - {7,7,2,2}, // 5B - {4,5,8,9}, // 5C + {7,7,1,1}, // 5B + {4,5,8,8}, // 5C {4,5,4,5}, // 5D {6,6,6,7}, // 5E - {7,7,2,2}, // 5F + {7,7,1,1}, // 5F {6,6,6,6}, // 60 {6,6,6,6}, // 61 {2,2,2,2}, // 62 - {8,8,2,2}, // 63 + {8,8,1,1}, // 63 {3,3,3,3}, // 64 {3,3,3,3}, // 65 {5,5,5,5}, // 66 - {5,5,2,2}, // 67 + {5,5,1,1}, // 67 {4,4,4,4}, // 68 {2,2,2,2}, // 69 {2,2,2,2}, // 6A - {2,2,2,2}, // 6B + {2,2,1,1}, // 6B {5,5,7,7}, // 6C {4,4,4,4}, // 6D {6,6,6,6}, // 6E - {6,6,2,2}, // 6F + {6,6,1,1}, // 6F {2,2,2,2}, // 70 {5,6,5,6}, // 71 {2,2,5,5}, // 72 - {8,8,2,2}, // 73 + {8,8,1,1}, // 73 {4,4,4,4}, // 74 {4,4,4,4}, // 75 {6,6,6,6}, // 76 - {6,6,2,2}, // 77 + {6,6,1,1}, // 77 {2,2,2,2}, // 78 {4,5,4,5}, // 79 {2,2,4,4}, // 7A - {7,7,2,2}, // 7B + {7,7,1,1}, // 7B {4,5,6,6}, // 7C {4,5,4,5}, // 7D {6,6,6,7}, // 7E - {7,7,2,2}, // 7F + {7,7,1,1}, // 7F {2,2,3,3}, // 80 {6,6,6,6}, // 81 {2,2,2,2}, // 82 - {6,6,2,2}, // 83 + {6,6,1,1}, // 83 {3,3,3,3}, // 84 {3,3,3,3}, // 85 {3,3,3,3}, // 86 - {3,3,2,2}, // 87 + {3,3,1,1}, // 87 {2,2,2,2}, // 88 {2,2,2,2}, // 89 {2,2,2,2}, // 8A - {2,2,2,2}, // 8B + {2,2,1,1}, // 8B {4,4,4,4}, // 8C {4,4,4,4}, // 8D {4,4,4,4}, // 8E - {4,4,2,2}, // 8F + {4,4,1,1}, // 8F {3,3,3,3}, // 90 {6,6,6,6}, // 91 {2,2,5,5}, // 92 - {6,6,2,2}, // 93 + {6,6,1,1}, // 93 {4,4,4,4}, // 94 {4,4,4,4}, // 95 {4,4,4,4}, // 96 - {4,4,2,2}, // 97 + {4,4,1,1}, // 97 {2,2,2,2}, // 98 {5,5,5,5}, // 99 {2,2,2,2}, // 9A - {5,5,2,2}, // 9B + {5,5,1,1}, // 9B {5,5,4,4}, // 9C {5,5,5,5}, // 9D {5,5,5,5}, // 9E - {5,5,2,2}, // 9F + {5,5,1,1}, // 9F {2,2,2,2}, // A0 {6,6,6,6}, // A1 {2,2,2,2}, // A2 - {6,6,2,2}, // A3 + {6,6,1,1}, // A3 {3,3,3,3}, // A4 {3,3,3,3}, // A5 {3,3,3,3}, // A6 - {3,3,2,2}, // A7 + {3,3,1,1}, // A7 {2,2,2,2}, // A8 {2,2,2,2}, // A9 {2,2,2,2}, // AA - {2,2,2,2}, // AB + {2,2,1,1}, // AB {4,4,4,4}, // AC {4,4,4,4}, // AD {4,4,4,4}, // AE - {4,4,2,2}, // AF + {4,4,1,1}, // AF {2,2,2,2}, // B0 {5,6,5,6}, // B1 {2,2,5,5}, // B2 - {5,6,2,2}, // B3 + {5,6,1,1}, // B3 {4,4,4,4}, // B4 {4,4,4,4}, // B5 {4,4,4,4}, // B6 - {4,4,2,2}, // B7 + {4,4,1,1}, // B7 {2,2,2,2}, // B8 {4,5,4,5}, // B9 {2,2,2,2}, // BA - {4,5,2,2}, // BB + {4,5,1,1}, // BB {4,5,4,5}, // BC {4,5,4,5}, // BD {4,5,4,5}, // BE - {4,5,2,2}, // BF + {4,5,1,1}, // BF {2,2,2,2}, // C0 {6,6,6,6}, // C1 {2,2,2,2}, // C2 - {8,8,2,2}, // C3 + {8,8,1,1}, // C3 {3,3,3,3}, // C4 {3,3,3,3}, // C5 {5,5,5,5}, // C6 - {5,5,2,2}, // C7 + {5,5,1,1}, // C7 {2,2,2,2}, // C8 {2,2,2,2}, // C9 {2,2,2,2}, // CA - {2,2,2,2}, // CB + {2,2,1,1}, // CB {4,4,4,4}, // CC {4,4,4,4}, // CD {6,6,6,6}, // CE - {6,6,2,2}, // CF + {6,6,1,1}, // CF {3,3,3,3}, // D0 {5,6,5,6}, // D1 {2,2,5,5}, // D2 - {8,8,2,2}, // D3 + {8,8,1,1}, // D3 {4,4,4,4}, // D4 {4,4,4,4}, // D5 {6,6,6,6}, // D6 - {6,6,2,2}, // D7 + {6,6,1,1}, // D7 {2,2,2,2}, // D8 {4,5,4,5}, // D9 {2,2,3,3}, // DA - {7,7,2,2}, // DB - {4,5,4,5}, // DC + {7,7,1,1}, // DB + {4,5,4,4}, // DC {4,5,4,5}, // DD {7,7,7,7}, // DE - {7,7,2,2}, // DF + {7,7,1,1}, // DF {2,2,2,2}, // E0 {6,6,6,6}, // E1 {2,2,2,2}, // E2 - {8,8,2,2}, // E3 + {8,8,1,1}, // E3 {3,3,3,3}, // E4 {3,3,3,3}, // E5 {5,5,5,5}, // E6 - {5,5,2,2}, // E7 + {5,5,1,1}, // E7 {2,2,2,2}, // E8 {2,2,2,2}, // E9 {2,2,2,2}, // EA - {2,2,2,2}, // EB + {2,2,1,1}, // EB {4,4,4,4}, // EC {4,4,4,4}, // ED {6,6,6,6}, // EE - {6,6,2,2}, // EF + {6,6,1,1}, // EF {2,2,2,2}, // F0 {5,6,5,6}, // F1 {2,2,5,5}, // F2 - {8,8,2,2}, // F3 + {8,8,1,1}, // F3 {4,4,4,4}, // F4 {4,4,4,4}, // F5 {6,6,6,6}, // F6 - {6,6,2,2}, // F7 + {6,6,1,1}, // F7 {2,2,2,2}, // F8 {4,5,4,5}, // F9 {2,2,4,4}, // FA - {7,7,2,2}, // FB - {4,5,4,5}, // FC + {7,7,1,1}, // FB + {4,5,4,4}, // FC {4,5,4,5}, // FD {7,7,7,7}, // FE - {7,7,2,2}, // FF + {7,7,1,1}, // FF }; int GH278_Bcc_Sub(BYTE op, BYTE ps_not_taken, BYTE ps_taken, WORD pc) @@ -1043,6 +1043,54 @@ int GH282_test(void) //------------------------------------- +int g_fn_C000_count = 0; + +BYTE __stdcall fn_C000(WORD, WORD, BYTE, BYTE, ULONG) +{ + g_fn_C000_count++; + return 42; +} + +int GH292_test(void) +{ + // Undocumented 65C02 NOPs: 1 cycle & 1 byte + for (UINT op=0; op<256; op+=0x10) + { + reset(); + WORD base=regs.pc; + + mem[regs.pc] = op+0x03; if (Cpu65C02(0) != 1 || regs.pc != base+1) return 1; + mem[regs.pc] = op+0x07; if (Cpu65C02(0) != 1 || regs.pc != base+2) return 1; + mem[regs.pc] = op+0x0B; if (Cpu65C02(0) != 1 || regs.pc != base+3) return 1; + mem[regs.pc] = op+0x0F; if (Cpu65C02(0) != 1 || regs.pc != base+4) return 1; + } + + // + + // Undocumented 65C02 NOP: LDD - LoaD and Discard + IORead[0] = fn_C000; + + reset(); + WORD base = regs.pc; + mem[regs.pc+0] = 0xDC; + mem[regs.pc+1] = 0x00; + mem[regs.pc+2] = 0xC0; + if (Cpu65C02(0) != 4 || regs.pc != base+3 || g_fn_C000_count != 1 || regs.a != 0) return 1; + + reset(); + base = regs.pc; + mem[regs.pc+0] = 0xFC; + mem[regs.pc+1] = 0x00; + mem[regs.pc+2] = 0xC0; + if (Cpu65C02(0) != 4 || regs.pc != base+3 || g_fn_C000_count != 2 || regs.a != 0) return 1; + + IORead[0] = NULL; + + return 0; +} + +//------------------------------------- + int _tmain(int argc, _TCHAR* argv[]) { int res = 1; @@ -1061,5 +1109,8 @@ int _tmain(int argc, _TCHAR* argv[]) res = GH282_test(); if (res) return res; + res = GH292_test(); + if (res) return res; + return 0; }