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https://github.com/AppleWin/AppleWin.git
synced 2024-06-26 01:29:30 +00:00
Fix for "Mad Effect 1&2" demos (PR #725)
. 6502 interrupt delays 1 opcode when interrupt occurs on last cycle of opcode (#724). . Only 1-cycle delay for VF_TEXT & VF_MIXED mode changes (#656). NB. Mad Effect 1 still has a bit of flicker on Space Invader (left edge)
This commit is contained in:
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@ -403,10 +403,23 @@ static __forceinline void NMI(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn,
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#endif
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#endif
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}
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}
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static bool g_irqOnLastOpcodeCycle = false;
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static bool g_irqDefer1Opcode = false;
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static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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{
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if(g_bmIRQ && !(regs.ps & AF_INTERRUPT))
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if(g_bmIRQ && !(regs.ps & AF_INTERRUPT))
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{
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{
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// if 6522 interrupt occurs on opcode's last cycle, then defer IRQ by 1 opcode
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if (g_irqOnLastOpcodeCycle && !g_irqDefer1Opcode)
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{
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g_irqOnLastOpcodeCycle = false;
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g_irqDefer1Opcode = true; // if INT occurs again on next opcode, then do NOT defer
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return;
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}
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g_irqDefer1Opcode = false;
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// IRQ signals are deasserted when a specific r/w operation is done on device
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// IRQ signals are deasserted when a specific r/w operation is done on device
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#ifdef _DEBUG
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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@ -420,6 +433,8 @@ static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn,
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UINT uExtraCycles = 0; // Needed for CYC(a) macro
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UINT uExtraCycles = 0; // Needed for CYC(a) macro
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CYC(7)
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CYC(7)
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}
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}
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g_irqOnLastOpcodeCycle = false;
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}
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}
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const int IRQ_CHECK_OPCODE_FULL_SPEED = 40; // ~128 cycles (assume 3 cycles per opcode)
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const int IRQ_CHECK_OPCODE_FULL_SPEED = 40; // ~128 cycles (assume 3 cycles per opcode)
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@ -435,7 +450,9 @@ static __forceinline void CheckInterruptSources(ULONG uExecutedCycles, const boo
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g_fullSpeedOpcodeCount = IRQ_CHECK_OPCODE_FULL_SPEED;
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g_fullSpeedOpcodeCount = IRQ_CHECK_OPCODE_FULL_SPEED;
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}
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}
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MB_UpdateCycles(uExecutedCycles);
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if (MB_UpdateCycles(uExecutedCycles))
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g_irqOnLastOpcodeCycle = true;
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if (sg_Mouse.IsActive())
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if (sg_Mouse.IsActive())
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sg_Mouse.SetVBlank( !VideoGetVblBar(uExecutedCycles) );
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sg_Mouse.SetVBlank( !VideoGetVblBar(uExecutedCycles) );
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}
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}
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@ -536,11 +553,10 @@ DWORD CpuExecute(const DWORD uCycles, const bool bVideoUpdate)
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// >0 : Do multi-opcode emulation
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// >0 : Do multi-opcode emulation
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const DWORD uExecutedCycles = InternalCpuExecute(uCycles, bVideoUpdate);
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const DWORD uExecutedCycles = InternalCpuExecute(uCycles, bVideoUpdate);
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// NB. Required for normal-speed (even though 6522 is updated after every opcode), as may've finished on IRQ()
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MB_UpdateCycles(uExecutedCycles); // Update 6522s (NB. Do this before updating g_nCumulativeCycles below)
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MB_UpdateCycles(uExecutedCycles); // Update 6522s (NB. Do this before updating g_nCumulativeCycles below)
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// NB. Ensures that 6522 regs are up-to-date for any potential save-state
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// NB. Ensures that 6522 regs are up-to-date for any potential save-state
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//
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const UINT nRemainingCycles = uExecutedCycles - g_nCyclesExecuted;
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const UINT nRemainingCycles = uExecutedCycles - g_nCyclesExecuted;
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g_nCumulativeCycles += nRemainingCycles;
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g_nCumulativeCycles += nRemainingCycles;
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@ -129,6 +129,8 @@ struct SY6522_AY8910
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SSI263A SpeechChip;
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SSI263A SpeechChip;
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MockingboardUnitState_e state; // Where a unit is a 6522+AY8910 pair
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MockingboardUnitState_e state; // Where a unit is a 6522+AY8910 pair
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MockingboardUnitState_e stateB; // Phasor: 6522 & 2nd AY8910
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MockingboardUnitState_e stateB; // Phasor: 6522 & 2nd AY8910
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bool bLoadT1C;
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bool bLoadT2C;
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};
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};
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@ -376,6 +378,8 @@ static void UpdateIFR(SY6522_AY8910* pMB, BYTE clr_ifr, BYTE set_ifr=0)
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CpuIrqDeassert(IS_6522);
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CpuIrqDeassert(IS_6522);
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}
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}
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#define DEFER_T1C_LOAD
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static void SY6522_Write(BYTE nDevice, BYTE nReg, BYTE nValue)
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static void SY6522_Write(BYTE nDevice, BYTE nReg, BYTE nValue)
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{
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{
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g_bMB_Active = true;
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g_bMB_Active = true;
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@ -433,7 +437,7 @@ static void SY6522_Write(BYTE nDevice, BYTE nReg, BYTE nValue)
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UpdateIFR(pMB, IxR_TIMER1);
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UpdateIFR(pMB, IxR_TIMER1);
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pMB->sy6522.TIMER1_LATCH.h = nValue;
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pMB->sy6522.TIMER1_LATCH.h = nValue;
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pMB->sy6522.TIMER1_COUNTER.w = pMB->sy6522.TIMER1_LATCH.w;
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pMB->bLoadT1C = true;
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StartTimer1(pMB);
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StartTimer1(pMB);
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CpuAdjustIrqCheck(pMB->sy6522.TIMER1_LATCH.w); // Sync IRQ check timeout with 6522 counter underflow - GH#608
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CpuAdjustIrqCheck(pMB->sy6522.TIMER1_LATCH.w); // Sync IRQ check timeout with 6522 counter underflow - GH#608
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@ -529,7 +533,8 @@ static BYTE SY6522_Read(BYTE nDevice, BYTE nReg)
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nValue = pMB->sy6522.DDRA;
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nValue = pMB->sy6522.DDRA;
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break;
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break;
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case 0x04: // TIMER1L_COUNTER
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case 0x04: // TIMER1L_COUNTER
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nValue = pMB->sy6522.TIMER1_COUNTER.l;
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// NB. GH#701 (T1C:=0xFFFF, LDA T1C_L, A==0xFC)
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nValue = (pMB->sy6522.TIMER1_COUNTER.w - 3) & 0xff; // -3 to compensate for the (assumed) 4-cycle STA 6522.T1C_H
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UpdateIFR(pMB, IxR_TIMER1);
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UpdateIFR(pMB, IxR_TIMER1);
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break;
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break;
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case 0x05: // TIMER1H_COUNTER
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case 0x05: // TIMER1H_COUNTER
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@ -1541,7 +1546,8 @@ void MB_Reset() // CTRL+RESET or power-cycle
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static BYTE __stdcall MB_Read(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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static BYTE __stdcall MB_Read(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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{
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{
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MB_UpdateCycles(nExecutedCycles);
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if (g_bFullSpeed)
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MB_UpdateCycles(nExecutedCycles);
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#ifdef _DEBUG
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#ifdef _DEBUG
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if(!IS_APPLE2 && MemCheckINTCXROM())
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if(!IS_APPLE2 && MemCheckINTCXROM())
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@ -1604,7 +1610,8 @@ static BYTE __stdcall MB_Read(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULO
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static BYTE __stdcall MB_Write(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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static BYTE __stdcall MB_Write(WORD PC, WORD nAddr, BYTE bWrite, BYTE nValue, ULONG nExecutedCycles)
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{
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{
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MB_UpdateCycles(nExecutedCycles);
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if (g_bFullSpeed)
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MB_UpdateCycles(nExecutedCycles);
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#ifdef _DEBUG
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#ifdef _DEBUG
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if(!IS_APPLE2 && MemCheckINTCXROM())
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if(!IS_APPLE2 && MemCheckINTCXROM())
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@ -1828,24 +1835,45 @@ static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay,
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// Called by:
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// Called by:
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// . CpuExecute() every ~1000 @ 1MHz
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// . CpuExecute() every ~1000 @ 1MHz
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// . CheckInterruptSources() every opcode (or every 40 opcodes at full-speed)
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// . CheckInterruptSources() every opcode (or every 40 opcodes at full-speed)
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// . MB_Read() / MB_Write()
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// . MB_Read() / MB_Write() (only for full-speed)
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void MB_UpdateCycles(ULONG uExecutedCycles)
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bool MB_UpdateCycles(ULONG uExecutedCycles)
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{
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{
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if (g_SoundcardType == CT_Empty)
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if (g_SoundcardType == CT_Empty)
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return;
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return false;
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CpuCalcCycles(uExecutedCycles);
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CpuCalcCycles(uExecutedCycles);
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UINT64 uCycles = g_nCumulativeCycles - g_uLastCumulativeCycles;
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UINT64 uCycles = g_nCumulativeCycles - g_uLastCumulativeCycles;
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if (uCycles == 0)
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return false; // Likely when called from CpuExecute()
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_ASSERT(uCycles > 1);
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const bool isOpcode = (uCycles > 1 && uCycles <= 7); // todo: better to pass in a flag?
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g_uLastCumulativeCycles = g_nCumulativeCycles;
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g_uLastCumulativeCycles = g_nCumulativeCycles;
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_ASSERT(uCycles < 0x10000);
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_ASSERT(uCycles < 0x10000);
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USHORT nClocks = (USHORT) uCycles;
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USHORT nClocks = (USHORT) uCycles;
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bool bIrqOnLastOpcodeCycle = false;
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for (int i=0; i<NUM_SY6522; i++)
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for (int i=0; i<NUM_SY6522; i++)
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{
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{
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SY6522_AY8910* pMB = &g_MB[i];
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SY6522_AY8910* pMB = &g_MB[i];
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bool bTimer1Underflow = false; // Just for Willy Byte!
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bool bTimer1Underflow = false; // Just for Willy Byte!
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const bool bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks, &bTimer1Underflow);
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bool bTimer1Irq = false;
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bool bTimer1IrqOnLastCycle = false;
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if (isOpcode)
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{
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bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks-1, &bTimer1Underflow);
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bTimer1IrqOnLastCycle = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, 1, &bTimer1Underflow);
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bTimer1Irq = bTimer1Irq || bTimer1IrqOnLastCycle;
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}
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else
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{
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bTimer1Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER1_COUNTER.w, pMB->sy6522.timer1IrqDelay, nClocks, &bTimer1Underflow);
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}
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const bool bTimer2Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER2_COUNTER.w, pMB->sy6522.timer2IrqDelay, nClocks);
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const bool bTimer2Irq = CheckTimerUnderflowAndIrq(pMB->sy6522.TIMER2_COUNTER.w, pMB->sy6522.timer2IrqDelay, nClocks);
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if (!pMB->bTimer1Active && bTimer1Underflow)
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if (!pMB->bTimer1Active && bTimer1Underflow)
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@ -1864,6 +1892,7 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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if (pMB->bTimer1Active && bTimer1Irq)
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if (pMB->bTimer1Active && bTimer1Irq)
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{
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{
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UpdateIFR(pMB, 0, IxR_TIMER1);
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UpdateIFR(pMB, 0, IxR_TIMER1);
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bIrqOnLastOpcodeCycle = true;
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MB_Update();
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MB_Update();
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@ -1880,6 +1909,9 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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// - Ultima4/5 change ACCESS_TIMER1 after a couple of IRQs into tune
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// - Ultima4/5 change ACCESS_TIMER1 after a couple of IRQs into tune
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pMB->sy6522.TIMER1_COUNTER.w += pMB->sy6522.TIMER1_LATCH.w; // GH#651: account for underflowed cycles too
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pMB->sy6522.TIMER1_COUNTER.w += pMB->sy6522.TIMER1_LATCH.w; // GH#651: account for underflowed cycles too
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pMB->sy6522.TIMER1_COUNTER.w += 2; // GH#652: account for extra 2 cycles (Rockwell, Fig.16: period=N+2cycles)
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pMB->sy6522.TIMER1_COUNTER.w += 2; // GH#652: account for extra 2 cycles (Rockwell, Fig.16: period=N+2cycles)
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// EG. T1C=0xFFFE, T1L=0x0001
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// . T1C += T1L = 0xFFFF
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// . T1C += 2 = 0x0001
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if (pMB->sy6522.TIMER1_COUNTER.w > pMB->sy6522.TIMER1_LATCH.w)
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if (pMB->sy6522.TIMER1_COUNTER.w > pMB->sy6522.TIMER1_LATCH.w)
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{
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{
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if (pMB->sy6522.TIMER1_LATCH.w)
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if (pMB->sy6522.TIMER1_LATCH.w)
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@ -1891,6 +1923,12 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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}
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}
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}
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}
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if (pMB->bLoadT1C)
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{
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pMB->bLoadT1C = false;
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pMB->sy6522.TIMER1_COUNTER.w = pMB->sy6522.TIMER1_LATCH.w;
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}
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if (pMB->bTimer2Active && bTimer2Irq)
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if (pMB->bTimer2Active && bTimer2Irq)
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{
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{
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UpdateIFR(pMB, 0, IxR_TIMER2);
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UpdateIFR(pMB, 0, IxR_TIMER2);
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@ -1913,6 +1951,8 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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}
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}
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}
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}
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}
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}
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return bIrqOnLastOpcodeCycle;
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}
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}
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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@ -11,7 +11,7 @@ void MB_Demute();
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void MB_StartOfCpuExecute();
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void MB_StartOfCpuExecute();
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void MB_PeriodicUpdate(UINT executedCycles);
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void MB_PeriodicUpdate(UINT executedCycles);
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void MB_CheckIRQ();
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void MB_CheckIRQ();
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void MB_UpdateCycles(ULONG uExecutedCycles);
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bool MB_UpdateCycles(ULONG uExecutedCycles);
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SS_CARDTYPE MB_GetSoundcardType();
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SS_CARDTYPE MB_GetSoundcardType();
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bool MB_IsActive();
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bool MB_IsActive();
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DWORD MB_GetVolume();
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DWORD MB_GetVolume();
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@ -660,9 +660,10 @@ BYTE VideoSetMode(WORD, WORD address, BYTE write, BYTE, ULONG uExecutedCycles)
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if (!IS_APPLE2)
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if (!IS_APPLE2)
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RGB_SetVideoMode(address);
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RGB_SetVideoMode(address);
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bool delay = true;
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// Only 1-cycle delay for VF_TEXT & VF_MIXED mode changes (GH#656)
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if ((oldVideoMode ^ g_uVideoMode) & VF_PAGE2)
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bool delay = false;
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delay = false; // PAGE2 flag changed state, so no 1 cycle delay (GH#656)
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if ((oldVideoMode ^ g_uVideoMode) & (VF_TEXT|VF_MIXED))
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delay = true;
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NTSC_SetVideoMode( g_uVideoMode, delay );
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NTSC_SetVideoMode( g_uVideoMode, delay );
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