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Removed 65d02 and used the regular 65c02/6502 headers instead (PR #825) 

Removed 65d02.h and reconstructed this code using a combination of existing 6502.h/65c02.h and extra C Pre-Processor macros to include (or omit) the extra heatmap functionality.

We still end up with a normal 65c02 instance and also a debug 65c02 instance, but both will derive from the same 65c02.h file (+ same for the 6502 normal/debug instances).

Also:
. Added cpu_heatmap.inl for the built-in debugger's read/write operations.
. Support CpuRead/Write() from Z80 to hook the heatmap r/w.
This commit is contained in:
TomCh 2020-08-31 10:03:29 +01:00 committed by GitHub
parent 06f8ccb384
commit ef913fe827
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GPG Key ID: 4AEE18F83AFDEB23
19 changed files with 676 additions and 999 deletions
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16
AppleWinExpress2008.vcproj
View File

@ -826,11 +826,11 @@
>
</File>
<File
RelativePath=".\source\CPU\cpu65d02.h"
RelativePath=".\source\CPU\cpu_general.inl"
>
</File>
<File
RelativePath=".\source\CPU\cpu_general.inl"
RelativePath=".\source\CPU\cpu_heatmap.inl"
>
</File>
<File
@ -1087,10 +1087,6 @@
RelativePath=".\resource\Apple2.rom"
>
</File>
<File
RelativePath=".\resource\Apple2_Plus.rom"
>
</File>
<File
RelativePath=".\resource\Apple2_JPlus.rom"
>
@ -1099,6 +1095,10 @@
RelativePath=".\resource\Apple2_JPlus_Video.rom"
>
</File>
<File
RelativePath=".\resource\Apple2_Plus.rom"
>
</File>
<File
RelativePath=".\resource\Apple2e.rom"
>
@ -1186,11 +1186,11 @@
>
</File>
<File
RelativePath=".\resource\Disk2.rom"
RelativePath=".\resource\Disk2-13sector.rom"
>
</File>
<File
RelativePath=".\resource\Disk2-13sector.rom"
RelativePath=".\resource\Disk2.rom"
>
</File>
<File

1
AppleWinExpress2013.vcxproj
View File

@ -48,7 +48,6 @@
<ClInclude Include="source\CPU.h" />
<ClInclude Include="source\CPU\cpu6502.h" />
<ClInclude Include="source\CPU\cpu65C02.h" />
<ClInclude Include="source\CPU\cpu65d02.h" />
<ClInclude Include="source\Debugger\Debug.h" />
<ClInclude Include="source\Debugger\DebugDefs.h" />
<ClInclude Include="source\Debugger\Debugger_Assembler.h" />

3
AppleWinExpress2013.vcxproj.filters
View File

@ -237,9 +237,6 @@
<ClInclude Include="source\CPU\cpu6502.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65d02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65C02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>

1
AppleWinExpress2015.vcxproj
View File

@ -48,7 +48,6 @@
<ClInclude Include="source\CPU.h" />
<ClInclude Include="source\CPU\cpu6502.h" />
<ClInclude Include="source\CPU\cpu65C02.h" />
<ClInclude Include="source\CPU\cpu65d02.h" />
<ClInclude Include="source\Debugger\Debug.h" />
<ClInclude Include="source\Debugger\DebugDefs.h" />
<ClInclude Include="source\Debugger\Debugger_Assembler.h" />

3
AppleWinExpress2015.vcxproj.filters
View File

@ -237,9 +237,6 @@
<ClInclude Include="source\CPU\cpu6502.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65d02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65C02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>

1
AppleWinExpress2017.vcxproj
View File

@ -48,7 +48,6 @@
<ClInclude Include="source\CPU.h" />
<ClInclude Include="source\CPU\cpu6502.h" />
<ClInclude Include="source\CPU\cpu65C02.h" />
<ClInclude Include="source\CPU\cpu65d02.h" />
<ClInclude Include="source\Debugger\Debug.h" />
<ClInclude Include="source\Debugger\DebugDefs.h" />
<ClInclude Include="source\Debugger\Debugger_Assembler.h" />

3
AppleWinExpress2017.vcxproj.filters
View File

@ -237,9 +237,6 @@
<ClInclude Include="source\CPU\cpu6502.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65d02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65C02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>

1
AppleWinExpress2019.vcxproj
View File

@ -48,7 +48,6 @@
<ClInclude Include="source\CPU.h" />
<ClInclude Include="source\CPU\cpu6502.h" />
<ClInclude Include="source\CPU\cpu65C02.h" />
<ClInclude Include="source\CPU\cpu65d02.h" />
<ClInclude Include="source\Debugger\Debug.h" />
<ClInclude Include="source\Debugger\DebugDefs.h" />
<ClInclude Include="source\Debugger\Debugger_Assembler.h" />

3
AppleWinExpress2019.vcxproj.filters
View File

@ -237,9 +237,6 @@
<ClInclude Include="source\CPU\cpu6502.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65d02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>
<ClInclude Include="source\CPU\cpu65C02.h">
<Filter>Source Files\CPU</Filter>
</ClInclude>

89
source/CPU.cpp
View File

@ -214,13 +214,8 @@ void SetMouseCardInstalled(bool installed)
//
#include "CPU/cpu_general.inl"
#include "CPU/cpu_instructions.inl"
// Break into debugger on invalid opcodes
//#define INV IsDebugBreakOnInvalid(AM_1);
#define INV
/****************************************************************************
*
* OPCODE TABLE
@ -275,18 +270,6 @@ static __forceinline void DoIrqProfiling(DWORD uCycles)
//===========================================================================
BYTE CpuRead(USHORT addr, ULONG uExecutedCycles)
{
return READ;
}
void CpuWrite(USHORT addr, BYTE a, ULONG uExecutedCycles)
{
WRITE(a);
}
//===========================================================================
#ifdef USE_SPEECH_API
const USHORT COUT = 0xFDED;
@ -487,18 +470,57 @@ void CpuAdjustIrqCheck(UINT uCyclesUntilInterrupt)
//===========================================================================
#define READ _READ
#define WRITE(value) _WRITE(value)
#define HEATMAP_X(address)
#include "CPU/cpu6502.h" // MOS 6502
#include "CPU/cpu65C02.h" // WDC 65C02
#include "CPU/cpu65d02.h" // Debug CPU Memory Visualizer
#undef READ
#undef WRITE
#undef HEATMAP_X
//-----------------
#define READ Heatmap_ReadByte(addr, uExecutedCycles)
#define WRITE(value) Heatmap_WriteByte(addr, value, uExecutedCycles);
#define HEATMAP_X(address) Heatmap_X(address)
#include "CPU/cpu_heatmap.inl"
#define Cpu6502 Cpu6502_debug
#include "CPU/cpu6502.h" // MOS 6502
#undef Cpu6502
#define Cpu65C02 Cpu65C02_debug
#include "CPU/cpu65C02.h" // WDC 65C02
#undef Cpu65C02
#undef READ
#undef WRITE
#undef HEATMAP_X
//===========================================================================
static DWORD InternalCpuExecute(const DWORD uTotalCycles, const bool bVideoUpdate)
{
if (GetMainCpu() == CPU_6502)
return Cpu6502(uTotalCycles, bVideoUpdate); // Apple ][, ][+, //e, Clones
if (g_nAppMode == MODE_RUNNING)
{
if (GetMainCpu() == CPU_6502)
return Cpu6502(uTotalCycles, bVideoUpdate); // Apple ][, ][+, //e, Clones
else
return Cpu65C02(uTotalCycles, bVideoUpdate); // Enhanced Apple //e
}
else
return Cpu65C02(uTotalCycles, bVideoUpdate); // Enhanced Apple //e
{
_ASSERT(g_nAppMode == MODE_STEPPING || g_nAppMode == MODE_DEBUG);
if (GetMainCpu() == CPU_6502)
return Cpu6502_debug(uTotalCycles, bVideoUpdate); // Apple ][, ][+, //e, Clones
else
return Cpu65C02_debug(uTotalCycles, bVideoUpdate); // Enhanced Apple //e
}
}
//
@ -507,6 +529,31 @@ static DWORD InternalCpuExecute(const DWORD uTotalCycles, const bool bVideoUpdat
//===========================================================================
// Called by z80_RDMEM()
BYTE CpuRead(USHORT addr, ULONG uExecutedCycles)
{
if (g_nAppMode == MODE_RUNNING)
{
return _READ;
}
return Heatmap_ReadByte(addr, uExecutedCycles);
}
// Called by z80_WRMEM()
void CpuWrite(USHORT addr, BYTE value, ULONG uExecutedCycles)
{
if (g_nAppMode == MODE_RUNNING)
{
_WRITE(value);
return;
}
Heatmap_WriteByte(addr, value, uExecutedCycles);
}
//===========================================================================
void CpuDestroy ()
{
if (g_bCritSectionValid)

2
source/CPU.h
View File

@ -32,7 +32,7 @@ void CpuSaveSnapshot(class YamlSaveHelper& yamlSaveHelper);
void CpuLoadSnapshot(class YamlLoadHelper& yamlLoadHelper, UINT version);
BYTE CpuRead(USHORT addr, ULONG uExecutedCycles);
void CpuWrite(USHORT addr, BYTE a, ULONG uExecutedCycles);
void CpuWrite(USHORT addr, BYTE value, ULONG uExecutedCycles);
enum eCpuType {CPU_UNKNOWN=0, CPU_6502=1, CPU_65C02, CPU_Z80}; // Don't change! Persisted to Registry

517
source/CPU/cpu6502.h
View File

@ -52,270 +52,269 @@ static DWORD Cpu6502(DWORD uTotalCycles, const bool bVideoUpdate)
}
else
{
HEATMAP_X( regs.pc );
Fetch(iOpcode, uExecutedCycles);
//#define $ INV // INV = Invalid -> Debugger Break
#define $
switch (iOpcode)
{
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;
case 0x02: $ HLT CYC(2) break;
case 0x03: $ idx ASO CYC(8) break;
case 0x04: $ ZPG NOP CYC(3) break;
case 0x05: ZPG ORA CYC(3) break;
case 0x06: ZPG ASLn CYC(5) break;
case 0x07: $ ZPG ASO CYC(5) break;
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: $ IMM ANC CYC(2) break;
case 0x0C: $ ABSX_OPT NOP CYC(4) break;
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLn CYC(6) break;
case 0x0F: $ ABS ASO CYC(6) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: INDY_OPT ORA CYC(5) break;
case 0x12: $ HLT CYC(2) break;
case 0x13: $ INDY_CONST ASO CYC(8) break;
case 0x14: $ zpx NOP CYC(4) break;
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLn CYC(6) break;
case 0x17: $ zpx ASO CYC(6) break;
case 0x18: CLC CYC(2) break;
case 0x19: ABSY_OPT ORA CYC(4) break;
case 0x1A: $ NOP CYC(2) break;
case 0x1B: $ ABSY_CONST ASO CYC(7) break;
case 0x1C: $ ABSX_OPT NOP CYC(4) break;
case 0x1D: ABSX_OPT ORA CYC(4) break;
case 0x1E: ABSX_CONST ASLn CYC(7) break;
case 0x1F: $ ABSX_CONST ASO CYC(7) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: $ HLT CYC(2) break;
case 0x23: $ idx RLA CYC(8) break;
case 0x24: ZPG BIT CYC(3) break;
case 0x25: ZPG AND CYC(3) break;
case 0x26: ZPG ROLn CYC(5) break;
case 0x27: $ ZPG RLA CYC(5) break;
case 0x28: PLP CYC(4) break;
case 0x29: IMM AND CYC(2) break;
case 0x2A: rol CYC(2) break;
case 0x2B: $ IMM ANC CYC(2) break;
case 0x2C: ABS BIT CYC(4) break;
case 0x2D: ABS AND CYC(4) break;
case 0x2E: ABS ROLn CYC(6) break;
case 0x2F: $ ABS RLA CYC(6) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: INDY_OPT AND CYC(5) break;
case 0x32: $ HLT CYC(2) break;
case 0x33: $ INDY_CONST RLA CYC(8) break;
case 0x34: $ zpx NOP CYC(4) break;
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLn CYC(6) break;
case 0x37: $ zpx RLA CYC(6) break;
case 0x38: SEC CYC(2) break;
case 0x39: ABSY_OPT AND CYC(4) break;
case 0x3A: $ NOP CYC(2) break;
case 0x3B: $ ABSY_CONST RLA CYC(7) break;
case 0x3C: $ ABSX_OPT NOP CYC(4) break;
case 0x3D: ABSX_OPT AND CYC(4) break;
case 0x3E: ABSX_CONST ROLn CYC(7) break;
case 0x3F: $ ABSX_CONST RLA CYC(7) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: $ HLT CYC(2) break;
case 0x43: $ idx LSE CYC(8) break;
case 0x44: $ ZPG NOP CYC(3) break;
case 0x45: ZPG EOR CYC(3) break;
case 0x46: ZPG LSRn CYC(5) break;
case 0x47: $ ZPG LSE CYC(5) break;
case 0x48: PHA CYC(3) break;
case 0x49: IMM EOR CYC(2) break;
case 0x4A: lsr CYC(2) break;
case 0x4B: $ IMM ALR CYC(2) break;
case 0x4C: ABS JMP CYC(3) break;
case 0x4D: ABS EOR CYC(4) break;
case 0x4E: ABS LSRn CYC(6) break;
case 0x4F: $ ABS LSE CYC(6) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: INDY_OPT EOR CYC(5) break;
case 0x52: $ HLT CYC(2) break;
case 0x53: $ INDY_CONST LSE CYC(8) break;
case 0x54: $ zpx NOP CYC(4) break;
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRn CYC(6) break;
case 0x57: $ zpx LSE CYC(6) break;
case 0x58: CLI CYC(2) break;
case 0x59: ABSY_OPT EOR CYC(4) break;
case 0x5A: $ NOP CYC(2) break;
case 0x5B: $ ABSY_CONST LSE CYC(7) break;
case 0x5C: $ ABSX_OPT NOP CYC(4) break;
case 0x5D: ABSX_OPT EOR CYC(4) break;
case 0x5E: ABSX_CONST LSRn CYC(7) break;
case 0x5F: $ ABSX_CONST LSE CYC(7) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCn CYC(6) break;
case 0x62: $ HLT CYC(2) break;
case 0x63: $ idx RRA CYC(8) break;
case 0x64: $ ZPG NOP CYC(3) break;
case 0x65: ZPG ADCn CYC(3) break;
case 0x66: ZPG RORn CYC(5) break;
case 0x67: $ ZPG RRA CYC(5) break;
case 0x68: PLA CYC(4) break;
case 0x69: IMM ADCn CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: $ IMM ARR CYC(2) break;
case 0x6C: IABS_NMOS JMP CYC(5) break; // GH#264
case 0x6D: ABS ADCn CYC(4) break;
case 0x6E: ABS RORn CYC(6) break;
case 0x6F: $ ABS RRA CYC(6) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: INDY_OPT ADCn CYC(5) break;
case 0x72: $ HLT CYC(2) break;
case 0x73: $ INDY_CONST RRA CYC(8) break;
case 0x74: $ zpx NOP CYC(4) break;
case 0x75: zpx ADCn CYC(4) break;
case 0x76: zpx RORn CYC(6) break;
case 0x77: $ zpx RRA CYC(6) break;
case 0x78: SEI CYC(2) break;
case 0x79: ABSY_OPT ADCn CYC(4) break;
case 0x7A: $ NOP CYC(2) break;
case 0x7B: $ ABSY_CONST RRA CYC(7) break;
case 0x7C: $ ABSX_OPT NOP CYC(4) break;
case 0x7D: ABSX_OPT ADCn CYC(4) break;
case 0x7E: ABSX_CONST RORn CYC(7) break;
case 0x7F: $ ABSX_CONST RRA CYC(7) break;
case 0x80: $ IMM NOP CYC(2) break;
case 0x81: idx STA CYC(6) break;
case 0x82: $ IMM NOP CYC(2) break;
case 0x83: $ idx AXS CYC(6) break;
case 0x84: ZPG STY CYC(3) break;
case 0x85: ZPG STA CYC(3) break;
case 0x86: ZPG STX CYC(3) break;
case 0x87: $ ZPG AXS CYC(3) break;
case 0x88: DEY CYC(2) break;
case 0x89: $ IMM NOP CYC(2) break;
case 0x8A: TXA CYC(2) break;
case 0x8B: $ IMM XAA CYC(2) break;
case 0x8C: ABS STY CYC(4) break;
case 0x8D: ABS STA CYC(4) break;
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ ABS AXS CYC(4) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: INDY_CONST STA CYC(6) break;
case 0x92: $ HLT CYC(2) break;
case 0x93: $ INDY_CONST AXA CYC(6) break;
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: $ zpy AXS CYC(4) break;
case 0x98: TYA CYC(2) break;
case 0x99: ABSY_CONST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ ABSY_CONST TAS CYC(5) break;
case 0x9C: $ ABSX_CONST SAY CYC(5) break;
case 0x9D: ABSX_CONST STA CYC(5) break;
case 0x9E: $ ABSY_CONST XAS CYC(5) break;
case 0x9F: $ ABSY_CONST AXA CYC(5) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
case 0xA3: $ idx LAX CYC(6) break;
case 0xA4: ZPG LDY CYC(3) break;
case 0xA5: ZPG LDA CYC(3) break;
case 0xA6: ZPG LDX CYC(3) break;
case 0xA7: $ ZPG LAX CYC(3) break;
case 0xA8: TAY CYC(2) break;
case 0xA9: IMM LDA CYC(2) break;
case 0xAA: TAX CYC(2) break;
case 0xAB: $ IMM OAL CYC(2) break;
case 0xAC: ABS LDY CYC(4) break;
case 0xAD: ABS LDA CYC(4) break;
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ ABS LAX CYC(4) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: INDY_OPT LDA CYC(5) break;
case 0xB2: $ HLT CYC(2) break;
case 0xB3: $ INDY_OPT LAX CYC(5) break;
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ zpy LAX CYC(4) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: ABSY_OPT LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ ABSY_OPT LAS CYC(4) break;
case 0xBC: ABSX_OPT LDY CYC(4) break;
case 0xBD: ABSX_OPT LDA CYC(4) break;
case 0xBE: ABSY_OPT LDX CYC(4) break;
case 0xBF: $ ABSY_OPT LAX CYC(4) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: $ IMM NOP CYC(2) break;
case 0xC3: $ idx DCM CYC(8) break;
case 0xC4: ZPG CPY CYC(3) break;
case 0xC5: ZPG CMP CYC(3) break;
case 0xC6: ZPG DEC CYC(5) break;
case 0xC7: $ ZPG DCM CYC(5) break;
case 0xC8: INY CYC(2) break;
case 0xC9: IMM CMP CYC(2) break;
case 0xCA: DEX CYC(2) break;
case 0xCB: $ IMM SAX CYC(2) break;
case 0xCC: ABS CPY CYC(4) break;
case 0xCD: ABS CMP CYC(4) break;
case 0xCE: ABS DEC CYC(6) break;
case 0xCF: $ ABS DCM CYC(6) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: INDY_OPT CMP CYC(5) break;
case 0xD2: $ HLT CYC(2) break;
case 0xD3: $ INDY_CONST DCM CYC(8) break;
case 0xD4: $ zpx NOP CYC(4) break;
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DEC CYC(6) break;
case 0xD7: $ zpx DCM CYC(6) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: ABSY_OPT CMP CYC(4) break;
case 0xDA: $ NOP CYC(2) break;
case 0xDB: $ ABSY_CONST DCM CYC(7) break;
case 0xDC: $ ABSX_OPT NOP CYC(4) break;
case 0xDD: ABSX_OPT CMP CYC(4) break;
case 0xDE: ABSX_CONST DEC CYC(7) break;
case 0xDF: $ ABSX_CONST DCM CYC(7) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCn CYC(6) break;
case 0xE2: $ IMM NOP CYC(2) break;
case 0xE3: $ idx INS CYC(8) break;
case 0xE4: ZPG CPX CYC(3) break;
case 0xE5: ZPG SBCn CYC(3) break;
case 0xE6: ZPG INC CYC(5) break;
case 0xE7: $ ZPG INS CYC(5) break;
case 0xE8: INX CYC(2) break;
case 0xE9: IMM SBCn CYC(2) break;
case 0xEA: NOP CYC(2) break;
case 0xEB: $ IMM SBCn CYC(2) break;
case 0xEC: ABS CPX CYC(4) break;
case 0xED: ABS SBCn CYC(4) break;
case 0xEE: ABS INC CYC(6) break;
case 0xEF: $ ABS INS CYC(6) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: INDY_OPT SBCn CYC(5) break;
case 0xF2: $ HLT CYC(2) break;
case 0xF3: $ INDY_CONST INS CYC(8) break;
case 0xF4: $ zpx NOP CYC(4) break;
case 0xF5: zpx SBCn CYC(4) break;
case 0xF6: zpx INC CYC(6) break;
case 0xF7: $ zpx INS CYC(6) break;
case 0xF8: SED CYC(2) break;
case 0xF9: ABSY_OPT SBCn CYC(4) break;
case 0xFA: $ NOP CYC(2) break;
case 0xFB: $ ABSY_CONST INS CYC(7) break;
case 0xFC: $ ABSX_OPT NOP CYC(4) break;
case 0xFD: ABSX_OPT SBCn CYC(4) break;
case 0xFE: ABSX_CONST INC CYC(7) break;
case 0xFF: $ ABSX_CONST INS CYC(7) break;
// TODO-MP Optimization Note: ?? Move CYC(#) to array ??
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;
case 0x02: HLT CYC(2) break; // invalid
case 0x03: idx ASO CYC(8) break; // invalid
case 0x04: ZPG NOP CYC(3) break; // invalid
case 0x05: ZPG ORA CYC(3) break;
case 0x06: ZPG ASLn CYC(5) break;
case 0x07: ZPG ASO CYC(5) break; // invalid
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: IMM ANC CYC(2) break; // invalid
case 0x0C: ABSX_OPT NOP CYC(4) break; // invalid
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLn CYC(6) break;
case 0x0F: ABS ASO CYC(6) break; // invalid
case 0x10: REL BPL CYC(2) break;
case 0x11: INDY_OPT ORA CYC(5) break;
case 0x12: HLT CYC(2) break; // invalid
case 0x13: INDY_CONST ASO CYC(8) break; // invalid
case 0x14: zpx NOP CYC(4) break; // invalid
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLn CYC(6) break;
case 0x17: zpx ASO CYC(6) break; // invalid
case 0x18: CLC CYC(2) break;
case 0x19: ABSY_OPT ORA CYC(4) break;
case 0x1A: NOP CYC(2) break; // invalid
case 0x1B: ABSY_CONST ASO CYC(7) break; // invalid
case 0x1C: ABSX_OPT NOP CYC(4) break; // invalid
case 0x1D: ABSX_OPT ORA CYC(4) break;
case 0x1E: ABSX_CONST ASLn CYC(7) break;
case 0x1F: ABSX_CONST ASO CYC(7) break; // invalid
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: HLT CYC(2) break; // invalid
case 0x23: idx RLA CYC(8) break; // invalid
case 0x24: ZPG BIT CYC(3) break;
case 0x25: ZPG AND CYC(3) break;
case 0x26: ZPG ROLn CYC(5) break;
case 0x27: ZPG RLA CYC(5) break; // invalid
case 0x28: PLP CYC(4) break;
case 0x29: IMM AND CYC(2) break;
case 0x2A: rol CYC(2) break;
case 0x2B: IMM ANC CYC(2) break; // invalid
case 0x2C: ABS BIT CYC(4) break;
case 0x2D: ABS AND CYC(4) break;
case 0x2E: ABS ROLn CYC(6) break;
case 0x2F: ABS RLA CYC(6) break; // invalid
case 0x30: REL BMI CYC(2) break;
case 0x31: INDY_OPT AND CYC(5) break;
case 0x32: HLT CYC(2) break; // invalid
case 0x33: INDY_CONST RLA CYC(8) break; // invalid
case 0x34: zpx NOP CYC(4) break; // invalid
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLn CYC(6) break;
case 0x37: zpx RLA CYC(6) break; // invalid
case 0x38: SEC CYC(2) break;
case 0x39: ABSY_OPT AND CYC(4) break;
case 0x3A: NOP CYC(2) break; // invalid
case 0x3B: ABSY_CONST RLA CYC(7) break; // invalid
case 0x3C: ABSX_OPT NOP CYC(4) break; // invalid
case 0x3D: ABSX_OPT AND CYC(4) break;
case 0x3E: ABSX_CONST ROLn CYC(7) break;
case 0x3F: ABSX_CONST RLA CYC(7) break; // invalid
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: HLT CYC(2) break; // invalid
case 0x43: idx LSE CYC(8) break; // invalid
case 0x44: ZPG NOP CYC(3) break; // invalid
case 0x45: ZPG EOR CYC(3) break;
case 0x46: ZPG LSRn CYC(5) break;
case 0x47: ZPG LSE CYC(5) break; // invalid
case 0x48: PHA CYC(3) break;
case 0x49: IMM EOR CYC(2) break;
case 0x4A: lsr CYC(2) break;
case 0x4B: IMM ALR CYC(2) break; // invalid
case 0x4C: ABS JMP CYC(3) break;
case 0x4D: ABS EOR CYC(4) break;
case 0x4E: ABS LSRn CYC(6) break;
case 0x4F: ABS LSE CYC(6) break; // invalid
case 0x50: REL BVC CYC(2) break;
case 0x51: INDY_OPT EOR CYC(5) break;
case 0x52: HLT CYC(2) break; // invalid
case 0x53: INDY_CONST LSE CYC(8) break; // invalid
case 0x54: zpx NOP CYC(4) break; // invalid
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRn CYC(6) break;
case 0x57: zpx LSE CYC(6) break; // invalid
case 0x58: CLI CYC(2) break;
case 0x59: ABSY_OPT EOR CYC(4) break;
case 0x5A: NOP CYC(2) break; // invalid
case 0x5B: ABSY_CONST LSE CYC(7) break; // invalid
case 0x5C: ABSX_OPT NOP CYC(4) break; // invalid
case 0x5D: ABSX_OPT EOR CYC(4) break;
case 0x5E: ABSX_CONST LSRn CYC(7) break;
case 0x5F: ABSX_CONST LSE CYC(7) break; // invalid
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCn CYC(6) break;
case 0x62: HLT CYC(2) break; // invalid
case 0x63: idx RRA CYC(8) break; // invalid
case 0x64: ZPG NOP CYC(3) break; // invalid
case 0x65: ZPG ADCn CYC(3) break;
case 0x66: ZPG RORn CYC(5) break;
case 0x67: ZPG RRA CYC(5) break; // invalid
case 0x68: PLA CYC(4) break;
case 0x69: IMM ADCn CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: IMM ARR CYC(2) break; // invalid
case 0x6C: IABS_NMOS JMP CYC(5) break; // GH#264
case 0x6D: ABS ADCn CYC(4) break;
case 0x6E: ABS RORn CYC(6) break;
case 0x6F: ABS RRA CYC(6) break; // invalid
case 0x70: REL BVS CYC(2) break;
case 0x71: INDY_OPT ADCn CYC(5) break;
case 0x72: HLT CYC(2) break; // invalid
case 0x73: INDY_CONST RRA CYC(8) break; // invalid
case 0x74: zpx NOP CYC(4) break; // invalid
case 0x75: zpx ADCn CYC(4) break;
case 0x76: zpx RORn CYC(6) break;
case 0x77: zpx RRA CYC(6) break; // invalid
case 0x78: SEI CYC(2) break;
case 0x79: ABSY_OPT ADCn CYC(4) break;
case 0x7A: NOP CYC(2) break; // invalid
case 0x7B: ABSY_CONST RRA CYC(7) break; // invalid
case 0x7C: ABSX_OPT NOP CYC(4) break; // invalid
case 0x7D: ABSX_OPT ADCn CYC(4) break;
case 0x7E: ABSX_CONST RORn CYC(7) break;
case 0x7F: ABSX_CONST RRA CYC(7) break; // invalid
case 0x80: IMM NOP CYC(2) break; // invalid
case 0x81: idx STA CYC(6) break;
case 0x82: IMM NOP CYC(2) break; // invalid
case 0x83: idx AXS CYC(6) break; // invalid
case 0x84: ZPG STY CYC(3) break;
case 0x85: ZPG STA CYC(3) break;
case 0x86: ZPG STX CYC(3) break;
case 0x87: ZPG AXS CYC(3) break; // invalid
case 0x88: DEY CYC(2) break;
case 0x89: IMM NOP CYC(2) break; // invalid
case 0x8A: TXA CYC(2) break;
case 0x8B: IMM XAA CYC(2) break; // invalid
case 0x8C: ABS STY CYC(4) break;
case 0x8D: ABS STA CYC(4) break;
case 0x8E: ABS STX CYC(4) break;
case 0x8F: ABS AXS CYC(4) break; // invalid
case 0x90: REL BCC CYC(2) break;
case 0x91: INDY_CONST STA CYC(6) break;
case 0x92: HLT CYC(2) break; // invalid
case 0x93: INDY_CONST AXA CYC(6) break; // invalid
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: zpy AXS CYC(4) break; // invalid
case 0x98: TYA CYC(2) break;
case 0x99: ABSY_CONST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: ABSY_CONST TAS CYC(5) break; // invalid
case 0x9C: ABSX_CONST SAY CYC(5) break; // invalid
case 0x9D: ABSX_CONST STA CYC(5) break;
case 0x9E: ABSY_CONST XAS CYC(5) break; // invalid
case 0x9F: ABSY_CONST AXA CYC(5) break; // invalid
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
case 0xA3: idx LAX CYC(6) break; // invalid
case 0xA4: ZPG LDY CYC(3) break;
case 0xA5: ZPG LDA CYC(3) break;
case 0xA6: ZPG LDX CYC(3) break;
case 0xA7: ZPG LAX CYC(3) break; // invalid
case 0xA8: TAY CYC(2) break;
case 0xA9: IMM LDA CYC(2) break;
case 0xAA: TAX CYC(2) break;
case 0xAB: IMM OAL CYC(2) break; // invalid
case 0xAC: ABS LDY CYC(4) break;
case 0xAD: ABS LDA CYC(4) break;
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: ABS LAX CYC(4) break; // invalid
case 0xB0: REL BCS CYC(2) break;
case 0xB1: INDY_OPT LDA CYC(5) break;
case 0xB2: HLT CYC(2) break; // invalid
case 0xB3: INDY_OPT LAX CYC(5) break; // invalid
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: zpy LAX CYC(4) break; // invalid
case 0xB8: CLV CYC(2) break;
case 0xB9: ABSY_OPT LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: ABSY_OPT LAS CYC(4) break; // invalid
case 0xBC: ABSX_OPT LDY CYC(4) break;
case 0xBD: ABSX_OPT LDA CYC(4) break;
case 0xBE: ABSY_OPT LDX CYC(4) break;
case 0xBF: ABSY_OPT LAX CYC(4) break; // invalid
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: IMM NOP CYC(2) break; // invalid
case 0xC3: idx DCM CYC(8) break; // invalid
case 0xC4: ZPG CPY CYC(3) break;
case 0xC5: ZPG CMP CYC(3) break;
case 0xC6: ZPG DEC CYC(5) break;
case 0xC7: ZPG DCM CYC(5) break; // invalid
case 0xC8: INY CYC(2) break;
case 0xC9: IMM CMP CYC(2) break;
case 0xCA: DEX CYC(2) break;
case 0xCB: IMM SAX CYC(2) break; // invalid
case 0xCC: ABS CPY CYC(4) break;
case 0xCD: ABS CMP CYC(4) break;
case 0xCE: ABS DEC CYC(6) break;
case 0xCF: ABS DCM CYC(6) break; // invalid
case 0xD0: REL BNE CYC(2) break;
case 0xD1: INDY_OPT CMP CYC(5) break;
case 0xD2: HLT CYC(2) break; // invalid
case 0xD3: INDY_CONST DCM CYC(8) break; // invalid
case 0xD4: zpx NOP CYC(4) break; // invalid
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DEC CYC(6) break;
case 0xD7: zpx DCM CYC(6) break; // invalid
case 0xD8: CLD CYC(2) break;
case 0xD9: ABSY_OPT CMP CYC(4) break;
case 0xDA: NOP CYC(2) break; // invalid
case 0xDB: ABSY_CONST DCM CYC(7) break; // invalid
case 0xDC: ABSX_OPT NOP CYC(4) break; // invalid
case 0xDD: ABSX_OPT CMP CYC(4) break;
case 0xDE: ABSX_CONST DEC CYC(7) break;
case 0xDF: ABSX_CONST DCM CYC(7) break; // invalid
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCn CYC(6) break;
case 0xE2: IMM NOP CYC(2) break; // invalid
case 0xE3: idx INS CYC(8) break; // invalid
case 0xE4: ZPG CPX CYC(3) break;
case 0xE5: ZPG SBCn CYC(3) break;
case 0xE6: ZPG INC CYC(5) break;
case 0xE7: ZPG INS CYC(5) break; // invalid
case 0xE8: INX CYC(2) break;
case 0xE9: IMM SBCn CYC(2) break;
case 0xEA: NOP CYC(2) break;
case 0xEB: IMM SBCn CYC(2) break; // invalid
case 0xEC: ABS CPX CYC(4) break;
case 0xED: ABS SBCn CYC(4) break;
case 0xEE: ABS INC CYC(6) break;
case 0xEF: ABS INS CYC(6) break; // invalid
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: INDY_OPT SBCn CYC(5) break;
case 0xF2: HLT CYC(2) break; // invalid
case 0xF3: INDY_CONST INS CYC(8) break; // invalid
case 0xF4: zpx NOP CYC(4) break; // invalid
case 0xF5: zpx SBCn CYC(4) break;
case 0xF6: zpx INC CYC(6) break;
case 0xF7: zpx INS CYC(6) break; // invalid
case 0xF8: SED CYC(2) break;
case 0xF9: ABSY_OPT SBCn CYC(4) break;
case 0xFA: NOP CYC(2) break; // invalid
case 0xFB: ABSY_CONST INS CYC(7) break; // invalid
case 0xFC: ABSX_OPT NOP CYC(4) break; // invalid
case 0xFD: ABSX_OPT SBCn CYC(4) break;
case 0xFE: ABSX_CONST INC CYC(7) break;
case 0xFF: ABSX_CONST INS CYC(7) break; // invalid
}
#undef $
}
CheckInterruptSources(uExecutedCycles, bVideoUpdate);

520
source/CPU/cpu65C02.h
View File

@ -25,9 +25,6 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
static DWORD Cpu65C02(DWORD uTotalCycles, const bool bVideoUpdate)
{
// Optimisation:
// . Copy the global /regs/ vars to stack-based local vars
// (Oliver Schmidt says this gives a performance gain, see email - The real deal: "1.10.5")
WORD addr;
BOOL flagc; // must always be 0 or 1, no other values allowed
BOOL flagn; // must always be 0 or 0x80.
@ -55,270 +52,269 @@ static DWORD Cpu65C02(DWORD uTotalCycles, const bool bVideoUpdate)
}
else
{
HEATMAP_X( regs.pc );
Fetch(iOpcode, uExecutedCycles);
//#define $ INV // INV = Invalid -> Debugger Break
#define $
switch (iOpcode)
{
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;
case 0x02: $ IMM NOP CYC(2) break;
case 0x03: $ NOP CYC(1) break;
case 0x04: ZPG TSB CYC(5) break;
case 0x05: ZPG ORA CYC(3) break;
case 0x06: ZPG ASLc CYC(5) break;
case 0x07: $ NOP CYC(1) break;
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: $ NOP CYC(1) break;
case 0x0C: ABS TSB CYC(6) break;
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLc CYC(6) break;
case 0x0F: $ NOP CYC(1) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: INDY_OPT ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: $ NOP CYC(1) break;
case 0x14: ZPG TRB CYC(5) break;
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLc CYC(6) break;
case 0x17: $ NOP CYC(1) break;
case 0x18: CLC CYC(2) break;
case 0x19: ABSY_OPT ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: $ NOP CYC(1) break;
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: ABSX_OPT ORA CYC(4) break;
case 0x1E: ABSX_OPT ASLc CYC(6) break;
case 0x1F: $ NOP CYC(1) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: $ IMM NOP CYC(2) break;
case 0x23: $ NOP CYC(1) break;
case 0x24: ZPG BIT CYC(3) break;
case 0x25: ZPG AND CYC(3) break;
case 0x26: ZPG ROLc CYC(5) break;
case 0x27: $ NOP CYC(1) break;
case 0x28: PLP CYC(4) break;
case 0x29: IMM AND CYC(2) break;
case 0x2A: rol CYC(2) break;
case 0x2B: $ NOP CYC(1) break;
case 0x2C: ABS BIT CYC(4) break;
case 0x2D: ABS AND CYC(4) break;
case 0x2E: ABS ROLc CYC(6) break;
case 0x2F: $ NOP CYC(1) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: INDY_OPT AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: $ NOP CYC(1) break;
case 0x34: zpx BIT CYC(4) break;
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLc CYC(6) break;
case 0x37: $ NOP CYC(1) break;
case 0x38: SEC CYC(2) break;
case 0x39: ABSY_OPT AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: $ NOP CYC(1) break;
case 0x3C: ABSX_OPT BIT CYC(4) break;
case 0x3D: ABSX_OPT AND CYC(4) break;
case 0x3E: ABSX_OPT ROLc CYC(6) break;
case 0x3F: $ NOP CYC(1) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: $ IMM NOP CYC(2) break;
case 0x43: $ NOP CYC(1) break;
case 0x44: $ ZPG NOP CYC(3) break;
case 0x45: ZPG EOR CYC(3) break;
case 0x46: ZPG LSRc CYC(5) break;
case 0x47: $ NOP CYC(1) break;
case 0x48: PHA CYC(3) break;
case 0x49: IMM EOR CYC(2) break;
case 0x4A: lsr CYC(2) break;
case 0x4B: $ NOP CYC(1) break;
case 0x4C: ABS JMP CYC(3) break;
case 0x4D: ABS EOR CYC(4) break;
case 0x4E: ABS LSRc CYC(6) break;
case 0x4F: $ NOP CYC(1) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: INDY_OPT EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: $ NOP CYC(1) break;
case 0x54: $ zpx NOP CYC(4) break;
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRc CYC(6) break;
case 0x57: $ NOP CYC(1) break;
case 0x58: CLI CYC(2) break;
case 0x59: ABSY_OPT EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: $ NOP CYC(1) break;
case 0x5C: $ ABS NOP CYC(8) break;
case 0x5D: ABSX_OPT EOR CYC(4) break;
case 0x5E: ABSX_OPT LSRc CYC(6) break;
case 0x5F: $ NOP CYC(1) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCc CYC(6) break;
case 0x62: $ IMM NOP CYC(2) break;
case 0x63: $ NOP CYC(1) break;
case 0x64: ZPG STZ CYC(3) break;
case 0x65: ZPG ADCc CYC(3) break;
case 0x66: ZPG RORc CYC(5) break;
case 0x67: $ NOP CYC(1) break;
case 0x68: PLA CYC(4) break;
case 0x69: IMM ADCc CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: $ NOP CYC(1) break;
case 0x6C: IABS_CMOS JMP CYC(6) break;
case 0x6D: ABS ADCc CYC(4) break;
case 0x6E: ABS RORc CYC(6) break;
case 0x6F: $ NOP CYC(1) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: INDY_OPT ADCc CYC(5) break;
case 0x72: izp ADCc CYC(5) break;
case 0x73: $ NOP CYC(1) break;
case 0x74: zpx STZ CYC(4) break;
case 0x75: zpx ADCc CYC(4) break;
case 0x76: zpx RORc CYC(6) break;
case 0x77: $ NOP CYC(1) break;
case 0x78: SEI CYC(2) break;
case 0x79: ABSY_OPT ADCc CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: $ NOP CYC(1) break;
case 0x7C: IABSX JMP CYC(6) break;
case 0x7D: ABSX_OPT ADCc CYC(4) break;
case 0x7E: ABSX_OPT RORc CYC(6) break;
case 0x7F: $ NOP CYC(1) break;
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
case 0x82: $ IMM NOP CYC(2) break;
case 0x83: $ NOP CYC(1) break;
case 0x84: ZPG STY CYC(3) break;
case 0x85: ZPG STA CYC(3) break;
case 0x86: ZPG STX CYC(3) break;
case 0x87: $ NOP CYC(1) break;
case 0x88: DEY CYC(2) break;
case 0x89: IMM BITI CYC(2) break;
case 0x8A: TXA CYC(2) break;
case 0x8B: $ NOP CYC(1) break;
case 0x8C: ABS STY CYC(4) break;
case 0x8D: ABS STA CYC(4) break;
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ NOP CYC(1) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: INDY_CONST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: $ NOP CYC(1) break;
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: $ NOP CYC(1) break;
case 0x98: TYA CYC(2) break;
case 0x99: ABSY_CONST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ NOP CYC(1) break;
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: ABSX_CONST STA CYC(5) break;
case 0x9E: ABSX_CONST STZ CYC(5) break;
case 0x9F: $ NOP CYC(1) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
case 0xA3: $ NOP CYC(1) break;
case 0xA4: ZPG LDY CYC(3) break;
case 0xA5: ZPG LDA CYC(3) break;
case 0xA6: ZPG LDX CYC(3) break;
case 0xA7: $ NOP CYC(1) break;
case 0xA8: TAY CYC(2) break;
case 0xA9: IMM LDA CYC(2) break;
case 0xAA: TAX CYC(2) break;
case 0xAB: $ NOP CYC(1) break;
case 0xAC: ABS LDY CYC(4) break;
case 0xAD: ABS LDA CYC(4) break;
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ NOP CYC(1) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: INDY_OPT LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: $ NOP CYC(1) break;
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ NOP CYC(1) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: ABSY_OPT LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ NOP CYC(1) break;
case 0xBC: ABSX_OPT LDY CYC(4) break;
case 0xBD: ABSX_OPT LDA CYC(4) break;
case 0xBE: ABSY_OPT LDX CYC(4) break;
case 0xBF: $ NOP CYC(1) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: $ IMM NOP CYC(2) break;
case 0xC3: $ NOP CYC(1) break;
case 0xC4: ZPG CPY CYC(3) break;
case 0xC5: ZPG CMP CYC(3) break;
case 0xC6: ZPG DEC CYC(5) break;
case 0xC7: $ NOP CYC(1) break;
case 0xC8: INY CYC(2) break;
case 0xC9: IMM CMP CYC(2) break;
case 0xCA: DEX CYC(2) break;
case 0xCB: $ NOP CYC(1) break;
case 0xCC: ABS CPY CYC(4) break;
case 0xCD: ABS CMP CYC(4) break;
case 0xCE: ABS DEC CYC(6) break;
case 0xCF: $ NOP CYC(1) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: INDY_OPT CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: $ NOP CYC(1) break;
case 0xD4: $ zpx NOP CYC(4) break;
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DEC CYC(6) break;
case 0xD7: $ NOP CYC(1) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: ABSY_OPT CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: $ NOP CYC(1) break;
case 0xDC: $ ABS LDD CYC(4) break;
case 0xDD: ABSX_OPT CMP CYC(4) break;
case 0xDE: ABSX_CONST DEC CYC(7) break;
case 0xDF: $ NOP CYC(1) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCc CYC(6) break;
case 0xE2: $ IMM NOP CYC(2) break;
case 0xE3: $ NOP CYC(1) break;
case 0xE4: ZPG CPX CYC(3) break;
case 0xE5: ZPG SBCc CYC(3) break;
case 0xE6: ZPG INC CYC(5) break;
case 0xE7: $ NOP CYC(1) break;
case 0xE8: INX CYC(2) break;
case 0xE9: IMM SBCc CYC(2) break;
case 0xEA: NOP CYC(2) break;
case 0xEB: $ NOP CYC(1) break;
case 0xEC: ABS CPX CYC(4) break;
case 0xED: ABS SBCc CYC(4) break;
case 0xEE: ABS INC CYC(6) break;
case 0xEF: $ NOP CYC(1) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: INDY_OPT SBCc CYC(5) break;
case 0xF2: izp SBCc CYC(5) break;
case 0xF3: $ NOP CYC(1) break;
case 0xF4: $ zpx NOP CYC(4) break;
case 0xF5: zpx SBCc CYC(4) break;
case 0xF6: zpx INC CYC(6) break;
case 0xF7: $ NOP CYC(1) break;
case 0xF8: SED CYC(2) break;
case 0xF9: ABSY_OPT SBCc CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: $ NOP CYC(1) break;
case 0xFC: $ ABS LDD CYC(4) break;
case 0xFD: ABSX_OPT SBCc CYC(4) break;
case 0xFE: ABSX_CONST INC CYC(7) break;
case 0xFF: $ NOP CYC(1) break;
// TODO-MP Optimization Note: ?? Move CYC(#) to array ??
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;
case 0x02: IMM NOP CYC(2) break; // invalid
case 0x03: NOP CYC(1) break; // invalid
case 0x04: ZPG TSB CYC(5) break;
case 0x05: ZPG ORA CYC(3) break;
case 0x06: ZPG ASLc CYC(5) break;
case 0x07: NOP CYC(1) break; // invalid
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: NOP CYC(1) break; // invalid
case 0x0C: ABS TSB CYC(6) break;
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLc CYC(6) break;
case 0x0F: NOP CYC(1) break; // invalid
case 0x10: REL BPL CYC(2) break;
case 0x11: INDY_OPT ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: NOP CYC(1) break; // invalid
case 0x14: ZPG TRB CYC(5) break;
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLc CYC(6) break;
case 0x17: NOP CYC(1) break; // invalid
case 0x18: CLC CYC(2) break;
case 0x19: ABSY_OPT ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: NOP CYC(1) break; // invalid
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: ABSX_OPT ORA CYC(4) break;
case 0x1E: ABSX_OPT ASLc CYC(6) break;
case 0x1F: NOP CYC(1) break; // invalid
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: IMM NOP CYC(2) break; // invalid
case 0x23: NOP CYC(1) break; // invalid
case 0x24: ZPG BIT CYC(3) break;
case 0x25: ZPG AND CYC(3) break;
case 0x26: ZPG ROLc CYC(5) break;
case 0x27: NOP CYC(1) break; // invalid
case 0x28: PLP CYC(4) break;
case 0x29: IMM AND CYC(2) break;
case 0x2A: rol CYC(2) break;
case 0x2B: NOP CYC(1) break; // invalid
case 0x2C: ABS BIT CYC(4) break;
case 0x2D: ABS AND CYC(4) break;
case 0x2E: ABS ROLc CYC(6) break;
case 0x2F: NOP CYC(1) break; // invalid
case 0x30: REL BMI CYC(2) break;
case 0x31: INDY_OPT AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: NOP CYC(1) break; // invalid
case 0x34: zpx BIT CYC(4) break;
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLc CYC(6) break;
case 0x37: NOP CYC(1) break; // invalid
case 0x38: SEC CYC(2) break;
case 0x39: ABSY_OPT AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: NOP CYC(1) break; // invalid
case 0x3C: ABSX_OPT BIT CYC(4) break;
case 0x3D: ABSX_OPT AND CYC(4) break;
case 0x3E: ABSX_OPT ROLc CYC(6) break;
case 0x3F: NOP CYC(1) break; // invalid
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: IMM NOP CYC(2) break; // invalid
case 0x43: NOP CYC(1) break; // invalid
case 0x44: ZPG NOP CYC(3) break; // invalid
case 0x45: ZPG EOR CYC(3) break;
case 0x46: ZPG LSRc CYC(5) break;
case 0x47: NOP CYC(1) break; // invalid
case 0x48: PHA CYC(3) break;
case 0x49: IMM EOR CYC(2) break;
case 0x4A: lsr CYC(2) break;
case 0x4B: NOP CYC(1) break; // invalid
case 0x4C: ABS JMP CYC(3) break;
case 0x4D: ABS EOR CYC(4) break;
case 0x4E: ABS LSRc CYC(6) break;
case 0x4F: NOP CYC(1) break; // invalid
case 0x50: REL BVC CYC(2) break;
case 0x51: INDY_OPT EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: NOP CYC(1) break; // invalid
case 0x54: zpx NOP CYC(4) break; // invalid
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRc CYC(6) break;
case 0x57: NOP CYC(1) break; // invalid
case 0x58: CLI CYC(2) break;
case 0x59: ABSY_OPT EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: NOP CYC(1) break; // invalid
case 0x5C: ABS NOP CYC(8) break; // invalid
case 0x5D: ABSX_OPT EOR CYC(4) break;
case 0x5E: ABSX_OPT LSRc CYC(6) break;
case 0x5F: NOP CYC(1) break; // invalid
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCc CYC(6) break;
case 0x62: IMM NOP CYC(2) break; // invalid
case 0x63: NOP CYC(1) break; // invalid
case 0x64: ZPG STZ CYC(3) break;
case 0x65: ZPG ADCc CYC(3) break;
case 0x66: ZPG RORc CYC(5) break;
case 0x67: NOP CYC(1) break; // invalid
case 0x68: PLA CYC(4) break;
case 0x69: IMM ADCc CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: NOP CYC(1) break; // invalid
case 0x6C: IABS_CMOS JMP CYC(6) break;
case 0x6D: ABS ADCc CYC(4) break;
case 0x6E: ABS RORc CYC(6) break;
case 0x6F: NOP CYC(1) break; // invalid
case 0x70: REL BVS CYC(2) break;
case 0x71: INDY_OPT ADCc CYC(5) break;
case 0x72: izp ADCc CYC(5) break;
case 0x73: NOP CYC(1) break; // invalid
case 0x74: zpx STZ CYC(4) break;
case 0x75: zpx ADCc CYC(4) break;
case 0x76: zpx RORc CYC(6) break;
case 0x77: NOP CYC(1) break; // invalid
case 0x78: SEI CYC(2) break;
case 0x79: ABSY_OPT ADCc CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: NOP CYC(1) break; // invalid
case 0x7C: IABSX JMP CYC(6) break;
case 0x7D: ABSX_OPT ADCc CYC(4) break;
case 0x7E: ABSX_OPT RORc CYC(6) break;
case 0x7F: NOP CYC(1) break; // invalid
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
case 0x82: IMM NOP CYC(2) break; // invalid
case 0x83: NOP CYC(1) break; // invalid
case 0x84: ZPG STY CYC(3) break;
case 0x85: ZPG STA CYC(3) break;
case 0x86: ZPG STX CYC(3) break;
case 0x87: NOP CYC(1) break; // invalid
case 0x88: DEY CYC(2) break;
case 0x89: IMM BITI CYC(2) break;
case 0x8A: TXA CYC(2) break;
case 0x8B: NOP CYC(1) break; // invalid
case 0x8C: ABS STY CYC(4) break;
case 0x8D: ABS STA CYC(4) break;
case 0x8E: ABS STX CYC(4) break;
case 0x8F: NOP CYC(1) break; // invalid
case 0x90: REL BCC CYC(2) break;
case 0x91: INDY_CONST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: NOP CYC(1) break; // invalid
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: NOP CYC(1) break; // invalid
case 0x98: TYA CYC(2) break;
case 0x99: ABSY_CONST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: NOP CYC(1) break; // invalid
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: ABSX_CONST STA CYC(5) break;
case 0x9E: ABSX_CONST STZ CYC(5) break;
case 0x9F: NOP CYC(1) break; // invalid
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
case 0xA3: NOP CYC(1) break; // invalid
case 0xA4: ZPG LDY CYC(3) break;
case 0xA5: ZPG LDA CYC(3) break;
case 0xA6: ZPG LDX CYC(3) break;
case 0xA7: NOP CYC(1) break; // invalid
case 0xA8: TAY CYC(2) break;
case 0xA9: IMM LDA CYC(2) break;
case 0xAA: TAX CYC(2) break;
case 0xAB: NOP CYC(1) break; // invalid
case 0xAC: ABS LDY CYC(4) break;
case 0xAD: ABS LDA CYC(4) break;
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: NOP CYC(1) break; // invalid
case 0xB0: REL BCS CYC(2) break;
case 0xB1: INDY_OPT LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: NOP CYC(1) break; // invalid
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: NOP CYC(1) break; // invalid
case 0xB8: CLV CYC(2) break;
case 0xB9: ABSY_OPT LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: NOP CYC(1) break; // invalid
case 0xBC: ABSX_OPT LDY CYC(4) break;
case 0xBD: ABSX_OPT LDA CYC(4) break;
case 0xBE: ABSY_OPT LDX CYC(4) break;
case 0xBF: NOP CYC(1) break; // invalid
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: IMM NOP CYC(2) break; // invalid
case 0xC3: NOP CYC(1) break; // invalid
case 0xC4: ZPG CPY CYC(3) break;
case 0xC5: ZPG CMP CYC(3) break;
case 0xC6: ZPG DEC CYC(5) break;
case 0xC7: NOP CYC(1) break; // invalid
case 0xC8: INY CYC(2) break;
case 0xC9: IMM CMP CYC(2) break;
case 0xCA: DEX CYC(2) break;
case 0xCB: NOP CYC(1) break; // invalid
case 0xCC: ABS CPY CYC(4) break;
case 0xCD: ABS CMP CYC(4) break;
case 0xCE: ABS DEC CYC(6) break;
case 0xCF: NOP CYC(1) break; // invalid
case 0xD0: REL BNE CYC(2) break;
case 0xD1: INDY_OPT CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: NOP CYC(1) break; // invalid
case 0xD4: zpx NOP CYC(4) break; // invalid
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DEC CYC(6) break;
case 0xD7: NOP CYC(1) break; // invalid
case 0xD8: CLD CYC(2) break;
case 0xD9: ABSY_OPT CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: NOP CYC(1) break; // invalid
case 0xDC: ABS LDD CYC(4) break; // invalid
case 0xDD: ABSX_OPT CMP CYC(4) break;
case 0xDE: ABSX_CONST DEC CYC(7) break;
case 0xDF: NOP CYC(1) break; // invalid
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCc CYC(6) break;
case 0xE2: IMM NOP CYC(2) break; // invalid
case 0xE3: NOP CYC(1) break; // invalid
case 0xE4: ZPG CPX CYC(3) break;
case 0xE5: ZPG SBCc CYC(3) break;
case 0xE6: ZPG INC CYC(5) break;
case 0xE7: NOP CYC(1) break; // invalid
case 0xE8: INX CYC(2) break;
case 0xE9: IMM SBCc CYC(2) break;
case 0xEA: NOP CYC(2) break;
case 0xEB: NOP CYC(1) break; // invalid
case 0xEC: ABS CPX CYC(4) break;
case 0xED: ABS SBCc CYC(4) break;
case 0xEE: ABS INC CYC(6) break;
case 0xEF: NOP CYC(1) break; // invalid
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: INDY_OPT SBCc CYC(5) break;
case 0xF2: izp SBCc CYC(5) break;
case 0xF3: NOP CYC(1) break; // invalid
case 0xF4: zpx NOP CYC(4) break; // invalid
case 0xF5: zpx SBCc CYC(4) break;
case 0xF6: zpx INC CYC(6) break;
case 0xF7: NOP CYC(1) break; // invalid
case 0xF8: SED CYC(2) break;
case 0xF9: ABSY_OPT SBCc CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: NOP CYC(1) break; // invalid
case 0xFC: ABS LDD CYC(4) break; // invalid
case 0xFD: ABSX_OPT SBCc CYC(4) break;
case 0xFE: ABSX_CONST INC CYC(7) break;
case 0xFF: NOP CYC(1) break; // invalid
}
#undef $
}
CheckInterruptSources(uExecutedCycles, bVideoUpdate);

426
source/CPU/cpu65d02.h
View File

@ -1,426 +0,0 @@
/*
AppleWin : An Apple //e emulator for Windows
Copyright (C) 2010-2011, Tom Charlesworth, Michael Pohoreski
AppleWin is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
AppleWin is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with AppleWin; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
typedef unsigned char u8; // TODO: change to <stdint.h> uint8_t
typedef unsigned short u16; // TODO: change to <stdint.h> uint16_t
// return (x < 255) ? (x+1) : 255;
inline u8 IncClamp8( u8 x )
{
u16 c = (~((x + 1) >> 8) & 1);
u8 r = x + c;
return r;
}
// return (x > 0) ? (x-1) : 0;
inline u8 DecClamp8( u8 x )
{
u16 c = (~((x - 1) >> 8) & 1);
u8 r = x - c;
return r;
}
// TODO: Verify: RGBA or BGRA (.bmp format)
// 0 A n/a
// 1 B Exec
// 2 G Read
// 3 R Write
//
// 0xAARRGGBB
// [0] B Exec
// [1] G Load
// [2] R Store
// [3] A n/a
// RGBA r = write, g = read, b = Program Counter
const int HEATMAP_W_MASK = 0x00FF0000; // Red Store
const int HEATMAP_R_MASK = 0x0000FF00; // Green Load
const int HEATMAP_X_MASK = 0x000000FF; // Blue Exec
// This is a memory heatmap
// FF = accessed on this clock cycle
// FE = accessed 1 clock cycles ago
// FD = accessed 2 clock cycles ago
// etc.
// Displayed as 256x256 64K memory access
int g_aMemoryHeatmap[ 65536 ]; // TODO: Change to <stdint.h> int32_t
#define HEATMAP_W(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_W_MASK
#define HEATMAP_R(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_R_MASK
#define HEATMAP_X(addr) g_aMemoryHeatmap[ addr ] |= HEATMAP_X_MASK
#undef READ
#define READ ReadByte( addr, uExecutedCycles )
inline u8 ReadByte( u16 addr, int uExecutedCycles )
{
// TODO: We should have a single g_bDebuggerActive so we can have a single implementation across ][+ //e
HEATMAP_R(addr);
return ((addr & 0xF000) == 0xC000)
? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles)
: *(mem+addr);
}
#undef WRITE
#define WRITE(a) \
HEATMAP_W(addr); \
{ \
memdirty[addr >> 8] = 0xFF; \
LPBYTE page = memwrite[addr >> 8]; \
if (page) \
*(page+(addr & 0xFF)) = (BYTE)(a); \
else if ((addr & 0xF000) == 0xC000) \
IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
}
#include "CPU/cpu_instructions.inl"
//===========================================================================
// Michael's Real-Time Debugger/Visualizer CPU
// Based on Modified 65C02
static DWORD Cpu65D02(DWORD uTotalCycles, const bool bVideoUpdate)
{
// Optimisation:
// . Copy the global /regs/ vars to stack-based local vars
// (Oliver Schmidt says this gives a performance gain, see email - The real deal: "1.10.5")
WORD addr;
BOOL flagc; // must always be 0 or 1, no other values allowed
BOOL flagn; // must always be 0 or 0x80.
BOOL flagv; // any value allowed
BOOL flagz; // any value allowed
WORD temp;
WORD temp2;
WORD val;
AF_TO_EF
ULONG uExecutedCycles = 0;
WORD base;
do
{
UINT uExtraCycles = 0;
BYTE iOpcode;
// NTSC_BEGIN
ULONG uPreviousCycles = uExecutedCycles;
// NTSC_END
if (GetActiveCpu() == CPU_Z80)
{
const UINT uZ80Cycles = z80_mainloop(uTotalCycles, uExecutedCycles); CYC(uZ80Cycles)
}
else
HEATMAP_X( regs.pc );
Fetch(iOpcode, uExecutedCycles);
// INV = Invalid -> Debugger Break
// MSVC C PreProcessor is BROKEN... #define @ INV
//#define # INV
//#define @ Read()
//#define $ Store()
//#define $ INV // INV = Invalid -> Debugger Break
#define $
switch (iOpcode)
{
// TODO Optimization Note: ?? Move CYC(#) to array ??
// Version 2 opcode: $ AM Instruction // $=DebugBreak AM=AddressingMode
//! ! ! ! ! ! // Tab-Stops
case 0x00: BRK CYC(7) break;
case 0x01: idx ORA CYC(6) break;
case 0x02: $ IMM NOP CYC(2) break;
case 0x03: $ NOP CYC(2) break;
case 0x04: ZPG TSB CYC(5) break;
case 0x05: ZPG ORA CYC(3) break;
case 0x06: ZPG ASLc CYC(5) break;
case 0x07: $ NOP CYC(2) break;
case 0x08: PHP CYC(3) break;
case 0x09: IMM ORA CYC(2) break;
case 0x0A: asl CYC(2) break;
case 0x0B: $ NOP CYC(2) break;
case 0x0C: ABS TSB CYC(6) break;
case 0x0D: ABS ORA CYC(4) break;
case 0x0E: ABS ASLc CYC(6) break;
case 0x0F: $ NOP CYC(2) break;
case 0x10: REL BPL CYC(2) break;
case 0x11: INDY_OPT ORA CYC(5) break;
case 0x12: izp ORA CYC(5) break;
case 0x13: $ NOP CYC(2) break;
case 0x14: ZPG TRB CYC(5) break;
case 0x15: zpx ORA CYC(4) break;
case 0x16: zpx ASLc CYC(6) break;
case 0x17: $ NOP CYC(2) break;
case 0x18: CLC CYC(2) break;
case 0x19: ABSY_OPT ORA CYC(4) break;
case 0x1A: INA CYC(2) break;
case 0x1B: $ NOP CYC(2) break;
case 0x1C: ABS TRB CYC(6) break;
case 0x1D: ABSX_OPT ORA CYC(4) break;
case 0x1E: ABSX_OPT ASLc CYC(6) break;
case 0x1F: $ NOP CYC(2) break;
case 0x20: ABS JSR CYC(6) break;
case 0x21: idx AND CYC(6) break;
case 0x22: $ IMM NOP CYC(2) break;
case 0x23: $ NOP CYC(2) break;
case 0x24: ZPG BIT CYC(3) break;
case 0x25: ZPG AND CYC(3) break;
case 0x26: ZPG ROLc CYC(5) break;
case 0x27: $ NOP CYC(2) break;
case 0x28: PLP CYC(4) break;
case 0x29: IMM AND CYC(2) break;
case 0x2A: rol CYC(2) break;
case 0x2B: $ NOP CYC(2) break;
case 0x2C: ABS BIT CYC(4) break;
case 0x2D: ABS AND CYC(2) break;
case 0x2E: ABS ROLc CYC(6) break;
case 0x2F: $ NOP CYC(2) break;
case 0x30: REL BMI CYC(2) break;
case 0x31: INDY_OPT AND CYC(5) break;
case 0x32: izp AND CYC(5) break;
case 0x33: $ NOP CYC(2) break;
case 0x34: zpx BIT CYC(4) break;
case 0x35: zpx AND CYC(4) break;
case 0x36: zpx ROLc CYC(6) break;
case 0x37: $ NOP CYC(2) break;
case 0x38: SEC CYC(2) break;
case 0x39: ABSY_OPT AND CYC(4) break;
case 0x3A: DEA CYC(2) break;
case 0x3B: $ NOP CYC(2) break;
case 0x3C: ABSX_OPT BIT CYC(4) break;
case 0x3D: ABSX_OPT AND CYC(4) break;
case 0x3E: ABSX_OPT ROLc CYC(6) break;
case 0x3F: $ NOP CYC(2) break;
case 0x40: RTI CYC(6) DoIrqProfiling(uExecutedCycles); break;
case 0x41: idx EOR CYC(6) break;
case 0x42: $ IMM NOP CYC(2) break;
case 0x43: $ NOP CYC(2) break;
case 0x44: $ ZPG NOP CYC(3) break;
case 0x45: ZPG EOR CYC(3) break;
case 0x46: ZPG LSRc CYC(5) break;
case 0x47: $ NOP CYC(2) break;
case 0x48: PHA CYC(3) break;
case 0x49: IMM EOR CYC(2) break;
case 0x4A: lsr CYC(2) break;
case 0x4B: $ NOP CYC(2) break;
case 0x4C: ABS JMP CYC(3) break;
case 0x4D: ABS EOR CYC(4) break;
case 0x4E: ABS LSRc CYC(6) break;
case 0x4F: $ NOP CYC(2) break;
case 0x50: REL BVC CYC(2) break;
case 0x51: INDY_OPT EOR CYC(5) break;
case 0x52: izp EOR CYC(5) break;
case 0x53: $ NOP CYC(2) break;
case 0x54: $ zpx NOP CYC(4) break;
case 0x55: zpx EOR CYC(4) break;
case 0x56: zpx LSRc CYC(6) break;
case 0x57: $ NOP CYC(2) break;
case 0x58: CLI CYC(2) break;
case 0x59: ABSY_OPT EOR CYC(4) break;
case 0x5A: PHY CYC(3) break;
case 0x5B: $ NOP CYC(2) break;
case 0x5C: $ ABSX_OPT NOP CYC(8) break;
case 0x5D: ABSX_OPT EOR CYC(4) break;
case 0x5E: ABSX_OPT LSRc CYC(6) break;
case 0x5F: $ NOP CYC(2) break;
case 0x60: RTS CYC(6) break;
case 0x61: idx ADCc CYC(6) break;
case 0x62: $ IMM NOP CYC(2) break;
case 0x63: $ NOP CYC(2) break;
case 0x64: ZPG STZ CYC(3) break;
case 0x65: ZPG ADCc CYC(3) break;
case 0x66: ZPG RORc CYC(5) break;
case 0x67: $ NOP CYC(2) break;
case 0x68: PLA CYC(4) break;
case 0x69: IMM ADCc CYC(2) break;
case 0x6A: ror CYC(2) break;
case 0x6B: $ NOP CYC(2) break;
case 0x6C: IABS_CMOS JMP CYC(6) break;
case 0x6D: ABS ADCc CYC(4) break;
case 0x6E: ABS RORc CYC(6) break;
case 0x6F: $ NOP CYC(2) break;
case 0x70: REL BVS CYC(2) break;
case 0x71: INDY_OPT ADCc CYC(5) break;
case 0x72: izp ADCc CYC(5) break;
case 0x73: $ NOP CYC(2) break;
case 0x74: zpx STZ CYC(4) break;
case 0x75: zpx ADCc CYC(4) break;
case 0x76: zpx RORc CYC(6) break;
case 0x77: $ NOP CYC(2) break;
case 0x78: SEI CYC(2) break;
case 0x79: ABSY_OPT ADCc CYC(4) break;
case 0x7A: PLY CYC(4) break;
case 0x7B: $ NOP CYC(2) break;
case 0x7C: IABSX JMP CYC(6) break;
case 0x7D: ABSX_OPT ADCc CYC(4) break;
case 0x7E: ABSX_OPT RORc CYC(6) break;
case 0x7F: $ NOP CYC(2) break;
case 0x80: REL BRA CYC(2) break;
case 0x81: idx STA CYC(6) break;
case 0x82: $ IMM NOP CYC(2) break;
case 0x83: $ NOP CYC(2) break;
case 0x84: ZPG STY CYC(3) break;
case 0x85: ZPG STA CYC(3) break;
case 0x86: ZPG STX CYC(3) break;
case 0x87: $ NOP CYC(2) break;
case 0x88: DEY CYC(2) break;
case 0x89: IMM BITI CYC(2) break;
case 0x8A: TXA CYC(2) break;
case 0x8B: $ NOP CYC(2) break;
case 0x8C: ABS STY CYC(4) break;
case 0x8D: ABS STA CYC(4) break;
case 0x8E: ABS STX CYC(4) break;
case 0x8F: $ NOP CYC(2) break;
case 0x90: REL BCC CYC(2) break;
case 0x91: INDY_CONST STA CYC(6) break;
case 0x92: izp STA CYC(5) break;
case 0x93: $ NOP CYC(2) break;
case 0x94: zpx STY CYC(4) break;
case 0x95: zpx STA CYC(4) break;
case 0x96: zpy STX CYC(4) break;
case 0x97: $ NOP CYC(2) break;
case 0x98: TYA CYC(2) break;
case 0x99: ABSY_CONST STA CYC(5) break;
case 0x9A: TXS CYC(2) break;
case 0x9B: $ NOP CYC(2) break;
case 0x9C: ABS STZ CYC(4) break;
case 0x9D: ABSX_CONST STA CYC(5) break;
case 0x9E: ABSX_CONST STZ CYC(5) break;
case 0x9F: $ NOP CYC(2) break;
case 0xA0: IMM LDY CYC(2) break;
case 0xA1: idx LDA CYC(6) break;
case 0xA2: IMM LDX CYC(2) break;
case 0xA3: $ NOP CYC(2) break;
case 0xA4: ZPG LDY CYC(3) break;
case 0xA5: ZPG LDA CYC(3) break;
case 0xA6: ZPG LDX CYC(3) break;
case 0xA7: $ NOP CYC(2) break;
case 0xA8: TAY CYC(2) break;
case 0xA9: IMM LDA CYC(2) break;
case 0xAA: TAX CYC(2) break;
case 0xAB: $ NOP CYC(2) break;
case 0xAC: ABS LDY CYC(4) break;
case 0xAD: ABS LDA CYC(4) break;
case 0xAE: ABS LDX CYC(4) break;
case 0xAF: $ NOP CYC(2) break;
case 0xB0: REL BCS CYC(2) break;
case 0xB1: INDY_OPT LDA CYC(5) break;
case 0xB2: izp LDA CYC(5) break;
case 0xB3: $ NOP CYC(2) break;
case 0xB4: zpx LDY CYC(4) break;
case 0xB5: zpx LDA CYC(4) break;
case 0xB6: zpy LDX CYC(4) break;
case 0xB7: $ NOP CYC(2) break;
case 0xB8: CLV CYC(2) break;
case 0xB9: ABSY_OPT LDA CYC(4) break;
case 0xBA: TSX CYC(2) break;
case 0xBB: $ NOP CYC(2) break;
case 0xBC: ABSX_OPT LDY CYC(4) break;
case 0xBD: ABSX_OPT LDA CYC(4) break;
case 0xBE: ABSY_OPT LDX CYC(4) break;
case 0xBF: $ NOP CYC(2) break;
case 0xC0: IMM CPY CYC(2) break;
case 0xC1: idx CMP CYC(6) break;
case 0xC2: $ IMM NOP CYC(2) break;
case 0xC3: $ NOP CYC(2) break;
case 0xC4: ZPG CPY CYC(3) break;
case 0xC5: ZPG CMP CYC(3) break;
case 0xC6: ZPG DEC CYC(5) break;
case 0xC7: $ NOP CYC(2) break;
case 0xC8: INY CYC(2) break;
case 0xC9: IMM CMP CYC(2) break;
case 0xCA: DEX CYC(2) break;
case 0xCB: $ NOP CYC(2) break;
case 0xCC: ABS CPY CYC(4) break;
case 0xCD: ABS CMP CYC(4) break;
case 0xCE: ABS DEC CYC(6) break;
case 0xCF: $ NOP CYC(2) break;
case 0xD0: REL BNE CYC(2) break;
case 0xD1: INDY_OPT CMP CYC(5) break;
case 0xD2: izp CMP CYC(5) break;
case 0xD3: $ NOP CYC(2) break;
case 0xD4: $ zpx NOP CYC(4) break;
case 0xD5: zpx CMP CYC(4) break;
case 0xD6: zpx DEC CYC(6) break;
case 0xD7: $ NOP CYC(2) break;
case 0xD8: CLD CYC(2) break;
case 0xD9: ABSY_OPT CMP CYC(4) break;
case 0xDA: PHX CYC(3) break;
case 0xDB: $ NOP CYC(2) break;
case 0xDC: $ ABSX_OPT NOP CYC(4) break;
case 0xDD: ABSX_OPT CMP CYC(4) break;
case 0xDE: ABSX_CONST DEC CYC(7) break;
case 0xDF: $ NOP CYC(2) break;
case 0xE0: IMM CPX CYC(2) break;
case 0xE1: idx SBCc CYC(6) break;
case 0xE2: $ IMM NOP CYC(2) break;
case 0xE3: $ NOP CYC(2) break;
case 0xE4: ZPG CPX CYC(3) break;
case 0xE5: ZPG SBCc CYC(3) break;
case 0xE6: ZPG INC CYC(5) break;
case 0xE7: $ NOP CYC(2) break;
case 0xE8: INX CYC(2) break;
case 0xE9: IMM SBCc CYC(2) break;
case 0xEA: NOP CYC(2) break;
case 0xEB: $ NOP CYC(2) break;
case 0xEC: ABS CPX CYC(4) break;
case 0xED: ABS SBCc CYC(4) break;
case 0xEE: ABS INC CYC(6) break;
case 0xEF: $ NOP CYC(2) break;
case 0xF0: REL BEQ CYC(2) break;
case 0xF1: INDY_OPT SBCc CYC(5) break;
case 0xF2: izp SBCc CYC(5) break;
case 0xF3: $ NOP CYC(2) break;
case 0xF4: $ zpx NOP CYC(4) break;
case 0xF5: zpx SBCc CYC(4) break;
case 0xF6: zpx INC CYC(6) break;
case 0xF7: $ NOP CYC(2) break;
case 0xF8: SED CYC(2) break;
case 0xF9: ABSY_OPT SBCc CYC(4) break;
case 0xFA: PLX CYC(4) break;
case 0xFB: $ NOP CYC(2) break;
case 0xFC: $ ABSX_OPT NOP CYC(4) break;
case 0xFD: ABSX_OPT SBCc CYC(4) break;
case 0xFE: ABSX_CONST INC CYC(7) break;
case 0xFF: $ NOP CYC(2) break;
}
#undef $
CheckInterruptSources(uExecutedCycles, bVideoUpdate);
NMI(uExecutedCycles, flagc, flagn, flagv, flagz);
IRQ(uExecutedCycles, flagc, flagn, flagv, flagz);
// NTSC_BEGIN
if (bVideoUpdate)
{
ULONG uElapsedCycles = uExecutedCycles - uPreviousCycles;
NTSC_VideoUpdateCycles( uElapsedCycles );
}
// NTSC_END
} while (uExecutedCycles < uTotalCycles);
EF_TO_AF // Emulator Flags to Apple Flags
return uExecutedCycles;
}

4
source/CPU/cpu_general.inl
View File

@ -54,7 +54,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define PUSH(a) *(mem+regs.sp--) = (a); \
if (regs.sp < 0x100) \
regs.sp = 0x1FF;
#define READ ( \
#define _READ ( \
((addr & 0xF000) == 0xC000) \
? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles) \
: *(mem+addr) \
@ -64,7 +64,7 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
flagz = !((a) & 0xFF); \
}
#define SETZ(a) flagz = !((a) & 0xFF);
#define WRITE(a) { \
#define _WRITE(a) { \
memdirty[addr >> 8] = 0xFF; \
LPBYTE page = memwrite[addr >> 8]; \
if (page) \

60
source/CPU/cpu_heatmap.inl Normal file
View File

@ -0,0 +1,60 @@
/*
AppleWin : An Apple //e emulator for Windows
Copyright (C) 1994-1996, Michael O'Brien
Copyright (C) 1999-2001, Oliver Schmidt
Copyright (C) 2002-2005, Tom Charlesworth
Copyright (C) 2006-2020, Tom Charlesworth, Michael Pohoreski
AppleWin is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
AppleWin is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with AppleWin; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* Description: 6502/65C02 emulation
*
* Author: Various
*/
/****************************************************************************
*
* RAM ACCESS MACROS (built-in debugger mode)
*
***/
inline void Heatmap_R(uint16_t address)
{
// todo
}
inline void Heatmap_W(uint16_t address)
{
// todo
}
inline void Heatmap_X(uint16_t address)
{
// todo
}
inline uint8_t Heatmap_ReadByte(uint16_t addr, int uExecutedCycles)
{
Heatmap_R(addr);
return _READ;
}
inline void Heatmap_WriteByte(uint16_t addr, uint16_t value, int uExecutedCycles)
{
Heatmap_W(addr);
_WRITE(value);
}

4
source/Common.h
View File

@ -52,7 +52,6 @@ enum AppMode_e
#define TITLE_APPLE_2E TEXT("Apple //e Emulator")
#define TITLE_APPLE_2E_ENHANCED TEXT("Enhanced Apple //e Emulator")
#define TITLE_APPLE_2C TEXT("Apple //e Emulator")
#define TITLE_APPLE_2D TEXT("Apple )(d Virtual Debug Hardware")
#define TITLE_PRAVETS_82 TEXT("Pravets 82 Emulator")
#define TITLE_PRAVETS_8M TEXT("Pravets 8M Emulator")
#define TITLE_PRAVETS_8A TEXT("Pravets 8A Emulator")
@ -154,11 +153,9 @@ enum eIRQSRC {IS_6522=0, IS_SPEECH, IS_SSC, IS_MOUSE};
//e 10
//e+ 11
//c 20
//d 40
*/
#define APPLE2E_MASK 0x10
#define APPLE2C_MASK 0x20
#define APPLE2D_MASK 0x40
#define APPLECLONE_MASK 0x100
#define IS_APPLE2 ((g_Apple2Type & (APPLE2E_MASK|APPLE2C_MASK)) == 0)
@ -175,7 +172,6 @@ enum eApple2Type {
A2TYPE_APPLE2EENHANCED,
A2TYPE_UNDEFINED,
A2TYPE_APPLE2C=APPLE2C_MASK,
A2TYPE_APPLE2D=APPLE2D_MASK,
// ][ clones start here:
A2TYPE_CLONE=APPLECLONE_MASK,

11
test/TestCPU6502/TestCPU6502.cpp
View File

@ -81,9 +81,20 @@ void NTSC_VideoUpdateCycles( long cycles6502 )
#include "../../source/CPU/cpu_general.inl"
#include "../../source/CPU/cpu_instructions.inl"
#define READ _READ
#define WRITE(a) _WRITE(a)
#define HEATMAP_X(pc)
#include "../../source/CPU/cpu6502.h" // MOS 6502
#include "../../source/CPU/cpu65C02.h" // WDC 65C02
#undef READ
#undef WRITE
#undef HEATMAP_X
//-------------------------------------
void init(void)
{
mem = (LPBYTE)VirtualAlloc(NULL,64*1024,MEM_COMMIT,PAGE_READWRITE);

10
test/TestCPU6502/stdafx.h
View File

@ -10,4 +10,14 @@
#include <windows.h>
#if _MSC_VER >= 1600 // <stdint.h> supported from VS2010 (cl.exe v16.00)
#include <stdint.h> // cleanup WORD DWORD -> uint16_t uint32_t
#else
#include <BaseTsd.h>
typedef UINT8 uint8_t;
typedef UINT16 uint16_t;
typedef UINT32 uint32_t;
typedef UINT64 uint64_t;
#endif
#include <string>