104 lines
3.5 KiB
Plaintext
104 lines
3.5 KiB
Plaintext
Key Super Serial Card (SSC) Memory Locations for Programmers
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------------------------------------------------------------
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All addresses are of the form '$C0sx', where 's' is the Slot number
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of the SSC plus $8 and 'x' is the final digit ($0 - $F) of the
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address.
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Control Register
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The 6551 Control Register is mapped to $C0sB
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($C09B for Slot 1, $C0AB
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for Slot 2, etc.).
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Its format is ...
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bit 7 : stop bit number [0= 1 stop bit, 1= 2 stop bits for most
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settings, except: 1.5 stop bits for word length 5 and no parity,
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and 1 for word length 8 and parity]
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bits 6 and 5 : word length
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[00= 8 bits, 01= 7 bits, 10= 6 bits, 11= 5 bits]
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bit 4 : receiver clock source [0= external, 1= internal]
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bits 3, 2, 1, 0 : baud rate, as follows:
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0000= 16x external clock
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0001= 50 bps
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0010= 75 bps
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0011= 109.92 bps
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0100= 134.58 bps
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0101= 150 bps
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0110= 300 bps
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0111= 600 bps
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1000= 1200 bps
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1001= 1800 bps
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1010= 2400 bps
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1011= 3600 bps
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1100= 4800 bps
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1101= 7200 bps
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1110= 9600 bps
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1111= 19200 bps
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Note that 1 MHz Apples (everything other than the Apple IIgs and //c
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Plus running in "fast" mode) cannot handle 19.2 kbps, and even 9600
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bps on these machines requires either some highly optimised code or
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a decent buffer in the device being accessed. The faster Apples
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have no difficulty with this speed, however.
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Command Register
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The 6551 Command Register is mapped to $C0sA, and is essentially an
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extension of the Control Register.
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Its format is ...
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bits 7 and 6 : parity mode control [00= odd parity, 01= even parity,
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10= mark parity (parity bit always set),
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11= space parity
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(parity bit always cleared)]
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bit 5 : parity mode enable [0=no parity used, 1=parity used]
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bit 4 : receiver mode echo [0=no echo, 1=echo]
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bits 3 and 2 : transmitter interrupt control
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[00= set RTS high and transmit no interrupts,
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01= set RTS low and transmit interrupts,
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10= set RTS low and transmit no interrupts,
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11= set RTS low and
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transmit break signals instead of interrupts]
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bit 1 : interrupt request disable
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[0=enable receiver interrupts,
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1=disable receiver interrupts]
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bit 0 : Data Terminal Ready (DTR) setting
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[0=set DTR high (indicates 'not ready'),
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1=set DTR low (indicates 'ready')]
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Note that, although the DTR is generally not used in the SSC
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(it may actually not be connected!), it must be set to 'low' in order for the
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6551 to function correctly. Also, the RTS signal must be set 'low'
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in order to receive any incoming data from the serial device.
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Note also that both the Command and Control registers are write-only,
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which means that reading them will not necessarily yield valid data
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on the device's settings. If there is any doubt as to the current
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settings of the 6551, you should (re)initialise them.
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Status register
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The 6551 Status register is mapped to $C0s9. It is a read-only register
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and its format is ...
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bit 7 : interrupt [0=no interrupt, 1=interrupt]
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bit 6 : Data Set Ready (DSR) [0=DSR low (ready), 1=DSR high (not ready)]
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bit 5 : Data Carrier Detect (DCD) [0=DCD low (detected), 1=DCD high (not detected)]
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bit 4 : transmitter data register empty [0=not empty, 1=empty]
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bit 3 : receiver data register full [0=not full, 1=full]
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bit 2 : overrun error [0=no error, 1=error]
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bit 1 : framing error [0=no error, 1=error]
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bit 0 : parity error [0=no error, 1=error]
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Data Register
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The Data Register at $C0s8 is used both for outgoing and incoming data.
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Whether the data has been sent or received can be determined by checking
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bits 4 and 3 (respectively) of the Status register.
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I hope that this is the SSC programming information that you are looking for.
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Aaron Heiss |