mirror of
https://github.com/AppleWin/AppleWin.git
synced 2024-08-30 22:29:36 +00:00
727 lines
20 KiB
C++
727 lines
20 KiB
C++
/*
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AppleWin : An Apple //e emulator for Windows
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Copyright (C) 1994-1996, Michael O'Brien
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Copyright (C) 1999-2001, Oliver Schmidt
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Copyright (C) 2002-2005, Tom Charlesworth
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Copyright (C) 2006-2010, Tom Charlesworth, Michael Pohoreski
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AppleWin is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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AppleWin is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with AppleWin; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Description: 6502/65C02 emulation
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*
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* Author: Various
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*/
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// TO DO:
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// . All these CPP macros need to be converted to inline funcs
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// TeaRex's Note about illegal opcodes:
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// ------------------------------------
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// . I've followed the names and descriptions given in
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// . "Extra Instructions Of The 65XX Series CPU"
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// . by Adam Vardy, dated Sept 27, 1996.
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// . The exception is, what he calls "SKB" and "SKW" I call "NOP",
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// . for consistency's sake. Several other naming conventions exist.
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// . Of course, only the 6502 has illegal opcodes, the 65C02 doesn't.
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// . Thus they're not emulated in Enhanced //e mode. Games relying on them
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// . don't run on a real Enhanced //e either. The old mixture of 65C02
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// . emulation and skipping the right number of bytes for illegal 6502
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// . opcodes, while working surprisingly well in practice, was IMHO
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// . ill-founded in theory and has thus been removed.
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// Note about bSlowerOnPagecross:
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// -------------------
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// . This is used to determine if a cycle needs to be added for a page-crossing.
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//
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// Modes that are affected:
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// . ABS,X; ABS,Y; (IND),Y
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//
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// The following opcodes (when indexed) add a cycle if page is crossed:
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// . ADC, AND, Bxx, CMP, EOR, LDA, LDX, LDY, ORA, SBC
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// . NB. Those opcode that DO NOT write to memory.
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// . 65C02: JMP (ABS-INDIRECT): 65C02 fixes JMP ($xxFF) bug but needs extra cycle in that case
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// . 65C02: JMP (ABS-INDIRECT,X): Probably. Currently unimplemented.
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//
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// The following opcodes (when indexed) DO NOT add a cycle if page is crossed:
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// . ASL, DEC, INC, LSR, ROL, ROR, STA, STX, STY
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// . NB. Those opcode that DO write to memory.
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//
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// What about these:
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// . 65C02: STZ?, TRB?, TSB?
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// . Answer: TRB & TSB don't have affected addressing modes
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// . STZ probably doesn't add a cycle since otherwise it would be slower than STA which doesn't make sense.
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//
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// NB. 'Zero-page indexed' opcodes wrap back to zero-page.
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// . The same goes for all the zero-page indirect modes.
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//
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// NB2. bSlowerOnPagecross can't be used for r/w detection, as these
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// . opcodes don't init this flag:
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// . $EC CPX ABS (since there's no addressing mode of CPY which has variable cycle number)
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// . $CC CPY ABS (same)
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//
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// 65C02 info:
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// . Read-modify-write instructions abs indexed in same page take 6 cycles (cf. 7 cycles for 6502)
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// . ASL, DEC, INC, LSR, ROL, ROR
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// . This should work now (but makes bSlowerOnPagecross even less useful for r/w detection)
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//
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// . Thanks to Scott Hemphill for the verified CMOS ADC and SBC algorithm! You rock.
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// . And thanks to the VICE team for the NMOS ADC and SBC algorithms as well as the
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// . algorithms for those illops which involve ADC or SBC. You rock too.
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#include "StdAfx.h"
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#include "Applewin.h"
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#include "CPU.h"
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#include "Frame.h"
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#include "Memory.h"
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#include "Mockingboard.h"
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#include "MouseInterface.h"
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#ifdef USE_SPEECH_API
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#include "Speech.h"
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#endif
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#include "Video.h"
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#include "NTSC.h"
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#include "z80emu.h"
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#include "Z80VICE/z80.h"
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#include "Z80VICE/z80mem.h"
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#include "YamlHelper.h"
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// 6502 Accumulator Bit Flags
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#define AF_SIGN 0x80
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#define AF_OVERFLOW 0x40
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#define AF_RESERVED 0x20
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#define AF_BREAK 0x10
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#define AF_DECIMAL 0x08
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#define AF_INTERRUPT 0x04
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#define AF_ZERO 0x02
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#define AF_CARRY 0x01
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#define SHORTOPCODES 22
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#define BENCHOPCODES 33
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// What is this 6502 code? Compressed 6502 code -- see: CpuSetupBenchmark()
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static BYTE benchopcode[BENCHOPCODES] = {
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0x06,0x16,0x24,0x45,0x48,0x65,0x68,0x76,
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0x84,0x85,0x86,0x91,0x94,0xA4,0xA5,0xA6,
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0xB1,0xB4,0xC0,0xC4,0xC5,0xE6,
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0x19,0x6D,0x8D,0x99,0x9D,0xAD,0xB9,0xBD,
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0xDD,0xED,0xEE
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};
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regsrec regs;
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unsigned __int64 g_nCumulativeCycles = 0;
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static ULONG g_nCyclesExecuted; // # of cycles executed up to last IO access
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//static signed long g_uInternalExecutedCycles;
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//
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// Assume all interrupt sources assert until the device is told to stop:
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// - eg by r/w to device's register or a machine reset
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static bool g_bCritSectionValid = false; // Deleting CritialSection when not valid causes crash on Win98
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static CRITICAL_SECTION g_CriticalSection; // To guard /g_bmIRQ/ & /g_bmNMI/
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static volatile UINT32 g_bmIRQ = 0;
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static volatile UINT32 g_bmNMI = 0;
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static volatile BOOL g_bNmiFlank = FALSE; // Positive going flank on NMI line
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//
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static eCpuType g_MainCPU = CPU_65C02;
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static eCpuType g_ActiveCPU = CPU_65C02;
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eCpuType GetMainCpu(void)
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{
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return g_MainCPU;
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}
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void SetMainCpu(eCpuType cpu)
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{
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_ASSERT(cpu != CPU_Z80);
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if (cpu == CPU_Z80)
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return;
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g_MainCPU = cpu;
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}
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static bool IsCpu65C02(eApple2Type apple2Type)
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{
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// NB. All Pravets clones are 6502 (GH#307)
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return (apple2Type == A2TYPE_APPLE2EENHANCED) || (apple2Type == A2TYPE_TK30002E) || (apple2Type & A2TYPE_APPLE2C);
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}
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eCpuType ProbeMainCpuDefault(eApple2Type apple2Type)
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{
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return IsCpu65C02(apple2Type) ? CPU_65C02 : CPU_6502;
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}
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void SetMainCpuDefault(eApple2Type apple2Type)
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{
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SetMainCpu( ProbeMainCpuDefault(apple2Type) );
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}
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eCpuType GetActiveCpu(void)
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{
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return g_ActiveCPU;
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}
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void SetActiveCpu(eCpuType cpu)
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{
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g_ActiveCPU = cpu;
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}
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bool Is6502InterruptEnabled(void)
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{
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return !(regs.ps & AF_INTERRUPT);
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}
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//
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#include "CPU/cpu_general.inl"
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#include "CPU/cpu_instructions.inl"
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// Break into debugger on invalid opcodes
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//#define INV IsDebugBreakOnInvalid(AM_1);
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#define INV
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/****************************************************************************
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*
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* OPCODE TABLE
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*
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***/
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#ifdef _DEBUG
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static unsigned __int64 g_nCycleIrqStart;
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static unsigned __int64 g_nCycleIrqEnd;
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static UINT g_nCycleIrqTime;
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static UINT g_nIdx = 0;
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static const UINT BUFFER_SIZE = 4096; // 80 secs
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static UINT g_nBuffer[BUFFER_SIZE];
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static UINT g_nMean = 0;
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static UINT g_nMin = 0xFFFFFFFF;
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static UINT g_nMax = 0;
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#endif
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static __forceinline void DoIrqProfiling(DWORD uCycles)
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{
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#ifdef _DEBUG
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if(regs.ps & AF_INTERRUPT)
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return; // Still in Apple's ROM
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g_nCycleIrqEnd = g_nCumulativeCycles + uCycles;
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g_nCycleIrqTime = (UINT) (g_nCycleIrqEnd - g_nCycleIrqStart);
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if(g_nCycleIrqTime > g_nMax) g_nMax = g_nCycleIrqTime;
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if(g_nCycleIrqTime < g_nMin) g_nMin = g_nCycleIrqTime;
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if(g_nIdx == BUFFER_SIZE)
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return;
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g_nBuffer[g_nIdx] = g_nCycleIrqTime;
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g_nIdx++;
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if(g_nIdx == BUFFER_SIZE)
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{
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UINT nTotal = 0;
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for(UINT i=0; i<BUFFER_SIZE; i++)
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nTotal += g_nBuffer[i];
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g_nMean = nTotal / BUFFER_SIZE;
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}
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#endif
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}
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//===========================================================================
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BYTE CpuRead(USHORT addr, ULONG uExecutedCycles)
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{
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return READ;
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}
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void CpuWrite(USHORT addr, BYTE a, ULONG uExecutedCycles)
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{
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WRITE(a);
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}
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//===========================================================================
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#ifdef USE_SPEECH_API
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const USHORT COUT = 0xFDED;
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const UINT OUTPUT_BUFFER_SIZE = 256;
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char g_OutputBuffer[OUTPUT_BUFFER_SIZE+1+1]; // +1 for EOL, +1 for NULL
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UINT OutputBufferIdx = 0;
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bool bEscMode = false;
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void CaptureCOUT(void)
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{
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const char ch = regs.a & 0x7f;
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if (ch == 0x07) // Bell
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{
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// Ignore
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}
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else if (ch == 0x08) // Backspace
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{
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if (OutputBufferIdx)
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OutputBufferIdx--;
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}
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else if (ch == 0x0A) // LF
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{
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// Ignore
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}
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else if (ch == 0x0D) // CR
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{
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if (bEscMode)
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{
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bEscMode = false;
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}
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else if (OutputBufferIdx)
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{
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g_OutputBuffer[OutputBufferIdx] = 0;
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g_Speech.Speak(g_OutputBuffer);
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#ifdef _DEBUG
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g_OutputBuffer[OutputBufferIdx] = '\n';
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g_OutputBuffer[OutputBufferIdx+1] = 0;
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OutputDebugString(g_OutputBuffer);
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#endif
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OutputBufferIdx = 0;
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}
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}
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else if (ch == 0x1B) // Escape
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{
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bEscMode = bEscMode ? false : true; // Toggle mode
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}
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else if (ch >= ' ' && ch <= '~')
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{
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if (OutputBufferIdx < OUTPUT_BUFFER_SIZE && !bEscMode)
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g_OutputBuffer[OutputBufferIdx++] = ch;
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}
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}
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#endif
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//===========================================================================
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//#define DBG_HDD_ENTRYPOINT
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#if defined(_DEBUG) && defined(DBG_HDD_ENTRYPOINT)
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// Output a debug msg whenever the HDD f/w is called or jump to.
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static void DebugHddEntrypoint(const USHORT PC)
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{
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static bool bOldPCAtC7xx = false;
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static WORD OldPC = 0;
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static UINT Count = 0;
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if ((PC >> 8) == 0xC7)
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{
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if (!bOldPCAtC7xx /*&& PC != 0xc70a*/)
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{
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Count++;
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char szDebug[100];
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sprintf(szDebug, "HDD Entrypoint: $%04X\n", PC);
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OutputDebugString(szDebug);
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}
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bOldPCAtC7xx = true;
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}
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else
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{
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bOldPCAtC7xx = false;
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}
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OldPC = PC;
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}
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#endif
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static __forceinline void Fetch(BYTE& iOpcode, ULONG uExecutedCycles)
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{
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const USHORT PC = regs.pc;
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#if defined(_DEBUG) && defined(DBG_HDD_ENTRYPOINT)
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DebugHddEntrypoint(PC);
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#endif
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iOpcode = ((PC & 0xF000) == 0xC000)
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? IORead[(PC>>4) & 0xFF](PC,PC,0,0,uExecutedCycles) // Fetch opcode from I/O memory, but params are still from mem[]
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: *(mem+PC);
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#ifdef USE_SPEECH_API
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if (PC == COUT && g_Speech.IsEnabled() && !g_bFullSpeed)
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CaptureCOUT();
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#endif
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regs.pc++;
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}
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//#define ENABLE_NMI_SUPPORT // Not used - so don't enable
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static __forceinline void NMI(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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#ifdef ENABLE_NMI_SUPPORT
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if(g_bNmiFlank)
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{
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// NMI signals are only serviced once
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g_bNmiFlank = FALSE;
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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#endif
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PUSH(regs.pc >> 8)
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PUSH(regs.pc & 0xFF)
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EF_TO_AF
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PUSH(regs.ps & ~AF_BREAK)
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regs.ps = regs.ps | AF_INTERRUPT & ~AF_DECIMAL;
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regs.pc = * (WORD*) (mem+0xFFFA);
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UINT uExtraCycles = 0; // Needed for CYC(a) macro
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CYC(7)
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}
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#endif
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}
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static __forceinline void IRQ(ULONG& uExecutedCycles, BOOL& flagc, BOOL& flagn, BOOL& flagv, BOOL& flagz)
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{
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if(g_bmIRQ && !(regs.ps & AF_INTERRUPT))
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{
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// IRQ signals are deasserted when a specific r/w operation is done on device
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#ifdef _DEBUG
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g_nCycleIrqStart = g_nCumulativeCycles + uExecutedCycles;
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#endif
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PUSH(regs.pc >> 8)
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PUSH(regs.pc & 0xFF)
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EF_TO_AF
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PUSH(regs.ps & ~AF_BREAK)
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regs.ps = regs.ps | AF_INTERRUPT & ~AF_DECIMAL;
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regs.pc = * (WORD*) (mem+0xFFFE);
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UINT uExtraCycles = 0; // Needed for CYC(a) macro
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CYC(7)
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}
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}
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const int IRQ_CHECK_OPCODE_FULL_SPEED = 40; // ~128 cycles (assume 3 cycles per opcode)
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static int g_fullSpeedOpcodeCount = IRQ_CHECK_OPCODE_FULL_SPEED;
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static __forceinline void CheckInterruptSources(ULONG uExecutedCycles, const bool bVideoUpdate)
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{
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if (!bVideoUpdate)
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{
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g_fullSpeedOpcodeCount--;
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if (g_fullSpeedOpcodeCount >= 0)
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return;
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g_fullSpeedOpcodeCount = IRQ_CHECK_OPCODE_FULL_SPEED;
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}
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MB_UpdateCycles(uExecutedCycles);
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if (sg_Mouse.IsActive())
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sg_Mouse.SetVBlank( !VideoGetVblBar(uExecutedCycles) );
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}
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// GH#608: IRQ needs to occur within 17 cycles (6 opcodes) of configuring the timer interrupt
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void CpuAdjustIrqCheck(UINT uCyclesUntilInterrupt)
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{
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const UINT opcodesUntilInterrupt = uCyclesUntilInterrupt/3; // assume 3 cycles per opcode
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if (g_bFullSpeed && opcodesUntilInterrupt < IRQ_CHECK_OPCODE_FULL_SPEED)
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g_fullSpeedOpcodeCount = opcodesUntilInterrupt;
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}
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//===========================================================================
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#include "CPU/cpu6502.h" // MOS 6502
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#include "CPU/cpu65C02.h" // WDC 65C02
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#include "CPU/cpu65d02.h" // Debug CPU Memory Visualizer
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//===========================================================================
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static DWORD InternalCpuExecute(const DWORD uTotalCycles, const bool bVideoUpdate)
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{
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if (GetMainCpu() == CPU_6502)
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return Cpu6502(uTotalCycles, bVideoUpdate); // Apple ][, ][+, //e, Clones
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else
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return Cpu65C02(uTotalCycles, bVideoUpdate); // Enhanced Apple //e
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}
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//
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// ----- ALL GLOBALLY ACCESSIBLE FUNCTIONS ARE BELOW THIS LINE -----
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//
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//===========================================================================
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void CpuDestroy ()
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{
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if (g_bCritSectionValid)
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{
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DeleteCriticalSection(&g_CriticalSection);
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g_bCritSectionValid = false;
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}
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}
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//===========================================================================
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// Description:
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// Call this when an IO-reg is accessed & accurate cycle info is needed
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// NB. Safe to call multiple times from the same IO function handler (as 'nExecutedCycles - g_nCyclesExecuted' will be zero the 2nd time)
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// Pre:
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// nExecutedCycles = # of cycles executed by Cpu6502() or Cpu65C02() for this iteration of ContinueExecution()
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// Post:
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// g_nCyclesExecuted
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// g_nCumulativeCycles
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//
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void CpuCalcCycles(const ULONG nExecutedCycles)
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{
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// Calc # of cycles executed since this func was last called
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const ULONG nCycles = nExecutedCycles - g_nCyclesExecuted;
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_ASSERT( (LONG)nCycles >= 0 );
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g_nCumulativeCycles += nCycles;
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g_nCyclesExecuted = nExecutedCycles;
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}
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//===========================================================================
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// Old method with g_uInternalExecutedCycles runs faster!
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// Old vs New
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// - 68.0,69.0MHz vs 66.7, 67.2MHz (with check for VBL IRQ every opcode)
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// - 89.6,88.9MHz vs 87.2, 87.9MHz (without check for VBL IRQ)
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// - 75.9, 78.5MHz (with check for VBL IRQ every 128 cycles)
|
|
// - 137.9,135.6MHz (with check for VBL IRQ & MB_Update every 128 cycles)
|
|
|
|
#if 0 // TODO: Measure perf increase by using this new method
|
|
ULONG CpuGetCyclesThisVideoFrame(ULONG) // Old func using g_uInternalExecutedCycles
|
|
{
|
|
CpuCalcCycles(g_uInternalExecutedCycles);
|
|
return g_dwCyclesThisFrame + g_nCyclesExecuted;
|
|
}
|
|
#else
|
|
ULONG CpuGetCyclesThisVideoFrame(const ULONG nExecutedCycles)
|
|
{
|
|
CpuCalcCycles(nExecutedCycles);
|
|
return g_dwCyclesThisFrame + g_nCyclesExecuted;
|
|
}
|
|
#endif
|
|
|
|
//===========================================================================
|
|
|
|
DWORD CpuExecute(const DWORD uCycles, const bool bVideoUpdate)
|
|
{
|
|
g_nCyclesExecuted = 0;
|
|
|
|
MB_StartOfCpuExecute();
|
|
|
|
// uCycles:
|
|
// =0 : Do single step
|
|
// >0 : Do multi-opcode emulation
|
|
const DWORD uExecutedCycles = InternalCpuExecute(uCycles, bVideoUpdate);
|
|
|
|
MB_UpdateCycles(uExecutedCycles); // Update 6522s (NB. Do this before updating g_nCumulativeCycles below)
|
|
// NB. Ensures that 6522 regs are up-to-date for any potential save-state
|
|
|
|
//
|
|
|
|
const UINT nRemainingCycles = uExecutedCycles - g_nCyclesExecuted;
|
|
g_nCumulativeCycles += nRemainingCycles;
|
|
|
|
return uExecutedCycles;
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
void CpuInitialize ()
|
|
{
|
|
CpuDestroy();
|
|
regs.a = regs.x = regs.y = regs.ps = 0xFF;
|
|
regs.sp = 0x01FF;
|
|
CpuReset(); // Init's ps & pc. Updates sp
|
|
|
|
InitializeCriticalSection(&g_CriticalSection);
|
|
g_bCritSectionValid = true;
|
|
CpuIrqReset();
|
|
CpuNmiReset();
|
|
|
|
z80mem_initialize();
|
|
z80_reset();
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
void CpuSetupBenchmark ()
|
|
{
|
|
regs.a = 0;
|
|
regs.x = 0;
|
|
regs.y = 0;
|
|
regs.pc = 0x300;
|
|
regs.sp = 0x1FF;
|
|
|
|
// CREATE CODE SEGMENTS CONSISTING OF GROUPS OF COMMONLY-USED OPCODES
|
|
{
|
|
int addr = 0x300;
|
|
int opcode = 0;
|
|
do
|
|
{
|
|
*(mem+addr++) = benchopcode[opcode];
|
|
*(mem+addr++) = benchopcode[opcode];
|
|
|
|
if (opcode >= SHORTOPCODES)
|
|
*(mem+addr++) = 0;
|
|
|
|
if ((++opcode >= BENCHOPCODES) || ((addr & 0x0F) >= 0x0B))
|
|
{
|
|
*(mem+addr++) = 0x4C;
|
|
*(mem+addr++) = (opcode >= BENCHOPCODES) ? 0x00 : ((addr >> 4)+1) << 4;
|
|
*(mem+addr++) = 0x03;
|
|
while (addr & 0x0F)
|
|
++addr;
|
|
}
|
|
} while (opcode < BENCHOPCODES);
|
|
}
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
void CpuIrqReset()
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
g_bmIRQ = 0;
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
void CpuIrqAssert(eIRQSRC Device)
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
g_bmIRQ |= 1<<Device;
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
void CpuIrqDeassert(eIRQSRC Device)
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
g_bmIRQ &= ~(1<<Device);
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
void CpuNmiReset()
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
g_bmNMI = 0;
|
|
g_bNmiFlank = FALSE;
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
void CpuNmiAssert(eIRQSRC Device)
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
if (g_bmNMI == 0) // NMI line is just becoming active
|
|
g_bNmiFlank = TRUE;
|
|
g_bmNMI |= 1<<Device;
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
void CpuNmiDeassert(eIRQSRC Device)
|
|
{
|
|
_ASSERT(g_bCritSectionValid);
|
|
if (g_bCritSectionValid) EnterCriticalSection(&g_CriticalSection);
|
|
g_bmNMI &= ~(1<<Device);
|
|
if (g_bCritSectionValid) LeaveCriticalSection(&g_CriticalSection);
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
void CpuReset()
|
|
{
|
|
// 7 cycles
|
|
regs.ps = (regs.ps | AF_INTERRUPT) & ~AF_DECIMAL;
|
|
regs.pc = * (WORD*) (mem+0xFFFC);
|
|
regs.sp = 0x0100 | ((regs.sp - 3) & 0xFF);
|
|
|
|
regs.bJammed = 0;
|
|
|
|
SetActiveCpu( GetMainCpu() );
|
|
z80_reset();
|
|
}
|
|
|
|
//===========================================================================
|
|
|
|
#define SS_YAML_KEY_CPU_TYPE "Type"
|
|
#define SS_YAML_KEY_REGA "A"
|
|
#define SS_YAML_KEY_REGX "X"
|
|
#define SS_YAML_KEY_REGY "Y"
|
|
#define SS_YAML_KEY_REGP "P"
|
|
#define SS_YAML_KEY_REGS "S"
|
|
#define SS_YAML_KEY_REGPC "PC"
|
|
#define SS_YAML_KEY_CUMULATIVECYCLES "Cumulative Cycles"
|
|
|
|
#define SS_YAML_VALUE_6502 "6502"
|
|
#define SS_YAML_VALUE_65C02 "65C02"
|
|
|
|
static std::string CpuGetSnapshotStructName(void)
|
|
{
|
|
static const std::string name("CPU");
|
|
return name;
|
|
}
|
|
|
|
void CpuSaveSnapshot(YamlSaveHelper& yamlSaveHelper)
|
|
{
|
|
regs.ps |= (AF_RESERVED | AF_BREAK);
|
|
|
|
YamlSaveHelper::Label state(yamlSaveHelper, "%s:\n", CpuGetSnapshotStructName().c_str());
|
|
yamlSaveHelper.SaveString(SS_YAML_KEY_CPU_TYPE, GetMainCpu() == CPU_6502 ? SS_YAML_VALUE_6502 : SS_YAML_VALUE_65C02);
|
|
yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGA, regs.a);
|
|
yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGX, regs.x);
|
|
yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGY, regs.y);
|
|
yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGP, regs.ps);
|
|
yamlSaveHelper.SaveHexUint8(SS_YAML_KEY_REGS, (BYTE) regs.sp);
|
|
yamlSaveHelper.SaveHexUint16(SS_YAML_KEY_REGPC, regs.pc);
|
|
yamlSaveHelper.SaveHexUint64(SS_YAML_KEY_CUMULATIVECYCLES, g_nCumulativeCycles);
|
|
}
|
|
|
|
void CpuLoadSnapshot(YamlLoadHelper& yamlLoadHelper)
|
|
{
|
|
if (!yamlLoadHelper.GetSubMap(CpuGetSnapshotStructName()))
|
|
return;
|
|
|
|
std::string cpuType = yamlLoadHelper.LoadString(SS_YAML_KEY_CPU_TYPE);
|
|
eCpuType cpu;
|
|
if (cpuType == SS_YAML_VALUE_6502) cpu = CPU_6502;
|
|
else if (cpuType == SS_YAML_VALUE_65C02) cpu = CPU_65C02;
|
|
else throw std::string("Load: Unknown main CPU type");
|
|
SetMainCpu(cpu);
|
|
|
|
regs.a = (BYTE) yamlLoadHelper.LoadUint(SS_YAML_KEY_REGA);
|
|
regs.x = (BYTE) yamlLoadHelper.LoadUint(SS_YAML_KEY_REGX);
|
|
regs.y = (BYTE) yamlLoadHelper.LoadUint(SS_YAML_KEY_REGY);
|
|
regs.ps = (BYTE) yamlLoadHelper.LoadUint(SS_YAML_KEY_REGP) | (AF_RESERVED | AF_BREAK);
|
|
regs.sp = (USHORT) ((yamlLoadHelper.LoadUint(SS_YAML_KEY_REGS) & 0xff) | 0x100);
|
|
regs.pc = (USHORT) yamlLoadHelper.LoadUint(SS_YAML_KEY_REGPC);
|
|
|
|
CpuIrqReset();
|
|
CpuNmiReset();
|
|
g_nCumulativeCycles = yamlLoadHelper.LoadUint64(SS_YAML_KEY_CUMULATIVECYCLES);
|
|
|
|
yamlLoadHelper.PopMap();
|
|
}
|