666 lines
20 KiB
C++
666 lines
20 KiB
C++
/*
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AppleWin : An Apple //e emulator for Windows
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Copyright (C) 1994-1996, Michael O'Brien
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Copyright (C) 1999-2001, Oliver Schmidt
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Copyright (C) 2002-2005, Tom Charlesworth
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Copyright (C) 2006-2010, Tom Charlesworth, Michael Pohoreski
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AppleWin is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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AppleWin is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with AppleWin; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Description: 6502/65C02 emulation
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*
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* Author: Various
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*/
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// TO DO:
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// . All these CPP macros need to be converted to inline funcs
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/****************************************************************************
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*
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* INSTRUCTION MACROS
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*
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***/
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#undef ADC_NMOS
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#undef ADC_CMOS
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#undef ALR
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#undef AND
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#undef ANC
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#undef ARR
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#undef ASL_NMOS
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#undef ASL_CMOS
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#undef ASLA
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#undef ASO
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#undef AXA
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#undef AXS
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#undef BCC
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#undef BCS
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#undef BEQ
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#undef BIT
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#undef BITI
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#undef BMI
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#undef BNE
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#undef BPL
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#undef BRA
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#undef BRK_NMOS
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#undef BRK_CMOS
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#undef BVC
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#undef BVS
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#undef CLC
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#undef CLD
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#undef CLI
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#undef CLV
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#undef CMP
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#undef CPX
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#undef CPY
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#undef DCM
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#undef DEA
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#undef DEC
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#undef DEX
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#undef DEY
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#undef EOR
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#undef HLT
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#undef INA
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#undef INC
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#undef INS
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#undef INX
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#undef INY
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#undef JMP
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#undef JSR
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#undef LAS
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#undef LAX
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#undef LDA
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#undef LDX
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#undef LDY
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#undef LSE
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#undef LSR_NMOS
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#undef LSR_CMOS
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#undef LSRA
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#undef NOP
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#undef OAL
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#undef ORA
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#undef PHA
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#undef PHP
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#undef PHX
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#undef PHY
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#undef PLA
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#undef PLP
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#undef PLX
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#undef PLY
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#undef RLA
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#undef ROL_NMOS
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#undef ROL_CMOS
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#undef ROLA
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#undef ROR_NMOS
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#undef ROR_CMOS
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#undef RORA
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#undef RRA
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#undef RTI
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#undef RTS
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#undef SAX
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#undef SAY
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#undef SBC_NMOS
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#undef SBC_CMOS
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#undef SEC
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#undef SED
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#undef SEI
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#undef STA
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#undef STX
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#undef STY
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#undef STZ
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#undef TAS
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#undef TAX
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#undef TAY
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#undef TRB
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#undef TSB
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#undef TSX
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#undef TXA
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#undef TXS
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#undef TYA
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#undef XAA
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#undef XAS
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// ==========
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#undef ADCn
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#undef ASLn
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#undef BRKn
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#undef LSRn
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#undef ROLn
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#undef RORn
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#undef SBCn
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#define ADCn ADC_NMOS
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#define ASLn ASL_NMOS
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#define BRKn BRK_NMOS
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#define LSRn LSR_NMOS
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#define ROLn ROL_NMOS
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#define RORn ROR_NMOS
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#define SBCn SBC_NMOS
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// ==========
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#undef ADCc
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#undef ASLc
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#undef BRKC
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#undef LSRc
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#undef ROLc
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#undef RORc
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#undef SBCc
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#define ADCc ADC_CMOS
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#define ASLc ASL_CMOS
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#define BRKc BRK_CMOS
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#define LSRc LSR_CMOS
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#define ROLc ROL_CMOS
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#define RORc ROR_CMOS
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#define SBCc SBC_CMOS
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// ==========
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#define ADC_NMOS /*bSlowerOnPagecross = 1;*/ \
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temp = READ; \
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if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
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if (val > 0x09) \
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val += 0x06; \
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if (val <= 0x0F) \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0); \
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else \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0) + 0x10;\
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flagz = !((regs.a + temp + flagc) & 0xFF); \
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flagn = (val & 0x80); \
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flagv = ((regs.a ^ val) & 0x80) && !((regs.a ^ temp) & 0x80);\
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if ((val & 0x1F0) > 0x90) \
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val += 0x60; \
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flagc = ((val & 0xFF0) > 0xF0); \
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regs.a = val & 0xFF; \
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} \
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else { \
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val = regs.a + temp + flagc; \
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flagc = (val > 0xFF); \
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flagv = (((regs.a & 0x80) == (temp & 0x80)) && \
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((regs.a & 0x80) != (val & 0x80))); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a); \
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}
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#define ADC_CMOS /*bSlowerOnPagecross = 1*/; \
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temp = READ; \
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flagv = !((regs.a ^ temp) & 0x80); \
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if (regs.ps & AF_DECIMAL) { \
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uExtraCycles++; \
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val = (regs.a & 0x0f) + (temp & 0x0f) + flagc; \
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if (val >= 0x0A) \
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val = 0x10 | ((val + 6) & 0x0f); \
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val += (regs.a & 0xf0) + (temp & 0xf0); \
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if (val >= 0xA0) { \
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flagc = 1; \
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if (val >= 0x180) \
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flagv = 0; \
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val += 0x60; \
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} \
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else { \
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flagc = 0; \
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if (val < 0x80) \
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flagv = 0; \
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} \
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} \
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else { \
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val = regs.a + temp + flagc; \
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if (val >= 0x100) { \
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flagc = 1; \
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if (val >= 0x180) flagv = 0; \
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} \
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else { \
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flagc = 0; \
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if (val < 0x80) flagv = 0; \
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} \
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} \
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regs.a = val & 0xFF; \
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SETNZ(regs.a)
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#define ALR regs.a &= READ; \
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flagc = (regs.a & 1); \
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flagn = 0; \
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regs.a >>= 1; \
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SETZ(regs.a)
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#define AND /*bSlowerOnPagecross = 1;*/ \
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regs.a &= READ; \
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SETNZ(regs.a)
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#define ANC regs.a &= READ; \
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SETNZ(regs.a) \
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flagc = !!flagn;
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#define ARR temp = regs.a & READ; /* Yes, this is sick */ \
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if (regs.ps & AF_DECIMAL) { \
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val = temp; \
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val |= (flagc ? 0x100 : 0); \
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val >>= 1; \
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flagn = (flagc ? 0x80 : 0); \
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SETZ(val) \
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flagv = ((val ^ temp) & 0x40); \
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if (((val & 0x0F) + (val & 0x01)) > 0x05) \
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val = (val & 0xF0) | ((val + 0x06) & 0x0F); \
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if (((val & 0xF0) + (val & 0x10)) > 0x50) { \
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val = (val & 0x0F) | ((val + 0x60) & 0xF0); \
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flagc = 1; \
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} \
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else \
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flagc = 0; \
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regs.a = (val & 0xFF); \
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} \
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else { \
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val = temp | (flagc ? 0x100 : 0); \
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val >>= 1; \
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SETNZ(val) \
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flagc = !!(val & 0x40); \
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flagv = ((val & 0x40) ^ ((val & 0x20) << 1)); \
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regs.a = (val & 0xFF); \
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}
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#define ASL_NMOS /*bSlowerOnPagecross = 0;*/ \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ASL_CMOS /*bSlowerOnPagecross = 1*/; \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ASLA val = regs.a << 1; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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regs.a = (BYTE)val;
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#define ASO /*bSlowerOnPagecross = 0;*/ \
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val = READ << 1; \
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flagc = (val > 0xFF); \
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WRITE(val) \
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regs.a |= val; \
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SETNZ(regs.a)
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#define AXA /*bSlowerOnPagecross = 0;*/ \
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val = regs.a & regs.x & (((base >> 8) + 1) & 0xFF); \
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ON_PAGECROSS_REPLACE_HI_ADDR \
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WRITE(val)
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#define AXS /*bSlowerOnPagecross = 0;*/ \
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WRITE(regs.a & regs.x)
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#define BCC if (!flagc) BRANCH_TAKEN;
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#define BCS if ( flagc) BRANCH_TAKEN;
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#define BEQ if ( flagz) BRANCH_TAKEN;
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#define BIT /*bSlowerOnPagecross = 1;*/ \
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val = READ; \
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flagz = !(regs.a & val); \
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flagn = val & 0x80; \
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flagv = val & 0x40;
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#define BITI flagz = !(regs.a & READ);
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#define BMI if ( flagn) BRANCH_TAKEN;
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#define BNE if (!flagz) BRANCH_TAKEN;
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#define BPL if (!flagn) BRANCH_TAKEN;
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#define BRA BRANCH_TAKEN;
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#define BRK_NMOS regs.pc++; \
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PUSH(regs.pc >> 8) \
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PUSH(regs.pc & 0xFF) \
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EF_TO_AF \
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PUSH(regs.ps); \
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regs.ps |= AF_INTERRUPT; \
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regs.pc = *(LPWORD)(mem+0xFFFE);
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#define BRK_CMOS regs.pc++; \
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PUSH(regs.pc >> 8) \
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PUSH(regs.pc & 0xFF) \
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EF_TO_AF \
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PUSH(regs.ps); \
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regs.ps |= AF_INTERRUPT; \
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regs.ps &= ~AF_DECIMAL; /*CMOS clears D flag*/ \
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regs.pc = *(LPWORD)(mem+0xFFFE);
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#define BVC if (!flagv) BRANCH_TAKEN;
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#define BVS if ( flagv) BRANCH_TAKEN;
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#define CLC flagc = 0;
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#define CLD regs.ps &= ~AF_DECIMAL;
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#define CLI regs.ps &= ~AF_INTERRUPT;
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#define CLV flagv = 0;
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#define CMP /*bSlowerOnPagecross = 1;*/ \
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val = READ; \
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flagc = (regs.a >= val); \
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val = regs.a-val; \
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SETNZ(val)
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#define CPX val = READ; \
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flagc = (regs.x >= val); \
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val = regs.x-val; \
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SETNZ(val)
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#define CPY val = READ; \
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flagc = (regs.y >= val); \
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val = regs.y-val; \
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SETNZ(val)
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#define DCM /*bSlowerOnPagecross = 0;*/ \
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val = READ-1; \
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WRITE(val) \
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flagc = (regs.a >= val); \
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val = regs.a-val; \
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SETNZ(val)
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#define DEA --regs.a; \
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SETNZ(regs.a)
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#define DEC /*bSlowerOnPagecross = 0;*/ \
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val = READ-1; \
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SETNZ(val) \
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WRITE(val)
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#define DEX --regs.x; \
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SETNZ(regs.x)
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#define DEY --regs.y; \
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SETNZ(regs.y)
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#define EOR /*bSlowerOnPagecross = 1;*/ \
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regs.a ^= READ; \
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SETNZ(regs.a)
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#define HLT regs.bJammed = 1; \
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--regs.pc;
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#define INA ++regs.a; \
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SETNZ(regs.a)
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#define INC /*bSlowerOnPagecross = 0;*/ \
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val = READ+1; \
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SETNZ(val) \
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WRITE(val)
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#define INS /*bSlowerOnPagecross = 0;*/ \
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val = READ+1; \
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WRITE(val) \
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temp = val; \
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temp2 = regs.a - temp - !flagc; \
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if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) - (temp & 0x0F) - !flagc; \
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if (val & 0x10) \
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val = ((val - 0x06) & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0) - 0x10);\
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else \
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val = (val & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0));\
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if (val & 0x100) \
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val -= 0x60; \
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flagc = (temp2 < 0x100); \
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SETNZ(temp2 & 0xFF); \
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flagv = ((regs.a ^ temp2) & 0x80) && ((regs.a ^ temp) & 0x80);\
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regs.a = val & 0xFF; \
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} \
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else { \
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val = temp2; \
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flagc = (val < 0x100); \
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flagv = (((regs.a & 0x80) != (temp & 0x80)) && \
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((regs.a & 0x80) != (val & 0x80))); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a); \
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}
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#define INX ++regs.x; \
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SETNZ(regs.x)
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#define INY ++regs.y; \
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SETNZ(regs.y)
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#define JMP regs.pc = addr;
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#define JSR addr = *(LPBYTE)(mem+regs.pc); regs.pc++; \
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PUSH(regs.pc >> 8) \
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PUSH(regs.pc & 0xFF) \
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regs.pc = addr | (*(LPBYTE)(mem+regs.pc)) << 8; /* GH#1257 */
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#define LAS /*bSlowerOnPagecross = 1*/; \
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val = (BYTE)(READ & regs.sp); \
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regs.a = regs.x = (BYTE) val; \
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regs.sp = val | 0x100; \
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SETNZ(val)
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#define LAX /*bSlowerOnPagecross = 1;*/ \
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regs.a = regs.x = READ; \
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SETNZ(regs.a)
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#define LDA /*bSlowerOnPagecross = 1;*/ \
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regs.a = READ; \
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SETNZ(regs.a)
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#define LDD /*Undocumented 65C02: LoaD and Discard*/ \
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READ;
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#define LDX /*bSlowerOnPagecross = 1;*/ \
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regs.x = READ; \
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SETNZ(regs.x)
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#define LDY /*bSlowerOnPagecross = 1;*/ \
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regs.y = READ; \
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SETNZ(regs.y)
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#define LSE /*bSlowerOnPagecross = 0;*/ \
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val = READ; \
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flagc = (val & 1); \
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val >>= 1; \
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WRITE(val) \
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regs.a ^= val; \
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SETNZ(regs.a)
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#define LSR_NMOS /*bSlowerOnPagecross = 0;*/ \
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val = READ; \
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flagc = (val & 1); \
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flagn = 0; \
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val >>= 1; \
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SETZ(val) \
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WRITE(val)
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#define LSR_CMOS /*bSlowerOnPagecross = 1;*/ \
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val = READ; \
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flagc = (val & 1); \
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flagn = 0; \
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val >>= 1; \
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SETZ(val) \
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WRITE(val)
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#define LSRA flagc = (regs.a & 1); \
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flagn = 0; \
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regs.a >>= 1; \
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SETZ(regs.a)
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#define NOP /*bSlowerOnPagecross = 1;*/
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#define OAL regs.a |= 0xEE; \
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regs.a &= READ; \
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regs.x = regs.a; \
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SETNZ(regs.a)
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#define ORA /*bSlowerOnPagecross = 1;*/ \
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regs.a |= READ; \
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SETNZ(regs.a)
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#define PHA PUSH(regs.a)
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#define PHP EF_TO_AF \
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PUSH(regs.ps)
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#define PHX PUSH(regs.x)
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#define PHY PUSH(regs.y)
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#define PLA regs.a = POP; \
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SETNZ(regs.a)
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#define PLP regs.ps = POP | AF_RESERVED | AF_BREAK; \
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AF_TO_EF
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#define PLX regs.x = POP; \
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SETNZ(regs.x)
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#define PLY regs.y = POP; \
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SETNZ(regs.y)
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#define RLA /*bSlowerOnPagecross = 0;*/ \
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val = (READ << 1) | flagc; \
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flagc = (val > 0xFF); \
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WRITE(val) \
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regs.a &= val; \
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SETNZ(regs.a)
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#define ROL_NMOS /*bSlowerOnPagecross = 0;*/ \
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val = (READ << 1) | flagc; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ROL_CMOS /*bSlowerOnPagecross = 1;*/ \
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val = (READ << 1) | flagc; \
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flagc = (val > 0xFF); \
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SETNZ(val) \
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WRITE(val)
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#define ROLA val = (((WORD)regs.a) << 1) | flagc; \
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flagc = (val > 0xFF); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a);
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#define ROR_NMOS /*bSlowerOnPagecross = 0;*/ \
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temp = READ; \
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val = (temp >> 1) | (flagc ? 0x80 : 0); \
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flagc = (temp & 1); \
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SETNZ(val) \
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WRITE(val)
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#define ROR_CMOS /*bSlowerOnPagecross = 1;*/ \
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temp = READ; \
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val = (temp >> 1) | (flagc ? 0x80 : 0); \
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flagc = (temp & 1); \
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SETNZ(val) \
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WRITE(val)
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#define RORA val = (((WORD)regs.a) >> 1) | (flagc ? 0x80 : 0); \
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flagc = (regs.a & 1); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a)
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#define RRA /*bSlowerOnPagecross = 0;*/ \
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temp = READ; \
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val = (temp >> 1) | (flagc ? 0x80 : 0); \
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flagc = (temp & 1); \
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WRITE(val) \
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temp = val; \
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if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) + (temp & 0x0F) + flagc; \
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if (val > 0x09) \
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val += 0x06; \
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if (val <= 0x0F) \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0); \
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else \
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val = (val & 0x0F) + (regs.a & 0xF0) + (temp & 0xF0) + 0x10;\
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flagz = !((regs.a + temp + flagc) & 0xFF); \
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flagn = (val & 0x80); \
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flagv = ((regs.a ^ val) & 0x80) && !((regs.a ^ temp) & 0x80);\
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if ((val & 0x1F0) > 0x90) \
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val += 0x60; \
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flagc = ((val & 0xFF0) > 0xF0); \
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regs.a = val & 0xFF; \
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} \
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else { \
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val = regs.a + temp + flagc; \
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flagc = (val > 0xFF); \
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flagv = (((regs.a & 0x80) == (temp & 0x80)) && \
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((regs.a & 0x80) != (val & 0x80))); \
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regs.a = val & 0xFF; \
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SETNZ(regs.a); \
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}
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#define RTI regs.ps = POP | AF_RESERVED | AF_BREAK; \
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AF_TO_EF \
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regs.pc = POP; \
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regs.pc |= (((WORD)POP) << 8);
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#define RTS regs.pc = POP; \
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|
regs.pc |= (((WORD)POP) << 8); \
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++regs.pc;
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#define SAX temp = regs.a & regs.x; \
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val = READ; \
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flagc = (temp >= val); \
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regs.x = temp-val; \
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SETNZ(regs.x)
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#define SAY /*bSlowerOnPagecross = 0;*/ \
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val = regs.y & (((base >> 8) + 1) & 0xFF); \
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ON_PAGECROSS_REPLACE_HI_ADDR \
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WRITE(val)
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#define SBC_NMOS /*bSlowerOnPagecross = 1;*/ \
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|
temp = READ; \
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temp2 = regs.a - temp - !flagc; \
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|
if (regs.ps & AF_DECIMAL) { \
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val = (regs.a & 0x0F) - (temp & 0x0F) - !flagc; \
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if (val & 0x10) \
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val = ((val - 0x06) & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0) - 0x10);\
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else \
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val = (val & 0x0F) | ((regs.a & 0xF0) - (temp & 0xF0));\
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|
if (val & 0x100) \
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|
val -= 0x60; \
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|
flagc = (temp2 < 0x100); \
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|
SETNZ(temp2 & 0xFF); \
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|
flagv = ((regs.a ^ temp2) & 0x80) && ((regs.a ^ temp) & 0x80);\
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|
regs.a = val & 0xFF; \
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|
} \
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|
else { \
|
|
val = temp2; \
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|
flagc = (val < 0x100); \
|
|
flagv = (((regs.a & 0x80) != (temp & 0x80)) && \
|
|
((regs.a & 0x80) != (val & 0x80))); \
|
|
regs.a = val & 0xFF; \
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|
SETNZ(regs.a); \
|
|
}
|
|
#define SBC_CMOS /*bSlowerOnPagecross = 1;*/ \
|
|
temp = READ; \
|
|
flagv = ((regs.a ^ temp) & 0x80); \
|
|
if (regs.ps & AF_DECIMAL) { \
|
|
uExtraCycles++; \
|
|
temp2 = 0x0F + (regs.a & 0x0F) - (temp & 0x0F) + flagc; \
|
|
if (temp2 < 0x10) { \
|
|
val = 0; \
|
|
temp2 -= 0x06; \
|
|
} \
|
|
else { \
|
|
val = 0x10; \
|
|
temp2 -= 0x10; \
|
|
} \
|
|
val += 0xF0 + (regs.a & 0xF0) - (temp & 0xF0); \
|
|
if (val < 0x100) { \
|
|
flagc = 0; \
|
|
if (val < 0x80) \
|
|
flagv = 0; \
|
|
val -= 0x60; \
|
|
} \
|
|
else { \
|
|
flagc = 1; \
|
|
if (val >= 0x180) \
|
|
flagv = 0; \
|
|
} \
|
|
val += temp2; \
|
|
} \
|
|
else { \
|
|
val = 0xff + regs.a - temp + flagc; \
|
|
if (val < 0x100) { \
|
|
flagc = 0; \
|
|
if (val < 0x80) \
|
|
flagv = 0; \
|
|
} \
|
|
else { \
|
|
flagc = 1; \
|
|
if (val >= 0x180) \
|
|
flagv = 0; \
|
|
} \
|
|
} \
|
|
regs.a = val & 0xFF; \
|
|
SETNZ(regs.a)
|
|
#define SEC flagc = 1;
|
|
#define SED regs.ps |= AF_DECIMAL;
|
|
#define SEI regs.ps |= AF_INTERRUPT;
|
|
#define STA /*bSlowerOnPagecross = 0;*/ \
|
|
WRITE(regs.a)
|
|
#define STX /*bSlowerOnPagecross = 0;*/ \
|
|
WRITE(regs.x)
|
|
#define STY /*bSlowerOnPagecross = 0;*/ \
|
|
WRITE(regs.y)
|
|
#define STZ /*bSlowerOnPagecross = 0;*/ \
|
|
WRITE(0)
|
|
#define TAS /*bSlowerOnPagecross = 0;*/ \
|
|
val = regs.a & regs.x; \
|
|
regs.sp = 0x100 | val; \
|
|
val &= (((base >> 8) + 1) & 0xFF); \
|
|
ON_PAGECROSS_REPLACE_HI_ADDR \
|
|
WRITE(val)
|
|
#define TAX regs.x = regs.a; \
|
|
SETNZ(regs.x)
|
|
#define TAY regs.y = regs.a; \
|
|
SETNZ(regs.y)
|
|
#define TRB /*bSlowerOnPagecross = 0;*/ \
|
|
val = READ; \
|
|
flagz = !(regs.a & val); \
|
|
val &= ~regs.a; \
|
|
WRITE(val)
|
|
#define TSB /*bSlowerOnPagecross = 0;*/ \
|
|
val = READ; \
|
|
flagz = !(regs.a & val); \
|
|
val |= regs.a; \
|
|
WRITE(val)
|
|
#define TSX regs.x = regs.sp & 0xFF; \
|
|
SETNZ(regs.x)
|
|
#define TXA regs.a = regs.x; \
|
|
SETNZ(regs.a)
|
|
#define TXS regs.sp = 0x100 | regs.x;
|
|
#define TYA regs.a = regs.y; \
|
|
SETNZ(regs.a)
|
|
#define XAA regs.a = regs.x; \
|
|
regs.a &= READ; \
|
|
SETNZ(regs.a)
|
|
#define XAS /*bSlowerOnPagecross = 0;*/ \
|
|
val = regs.x & (((base >> 8) + 1) & 0xFF); \
|
|
ON_PAGECROSS_REPLACE_HI_ADDR \
|
|
WRITE(val)
|