729 lines
16 KiB
C++
729 lines
16 KiB
C++
#include "stdafx.h"
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#include "../../source/Windows/AppleWin.h"
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#include "../../source/CPU.h"
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#include "../../source/Debugger/Debugger_Types.h"
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#include "../../source/Debugger/Debugger_Assembler.h" // Pull in default args for _6502_GetTargets()
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// NB. DebugDefs.h must come after Debugger_Types.h which declares these as extern
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#include "../../source/Debugger/DebugDefs.h"
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// From FrameBase
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class FrameBase
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{
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public:
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FrameBase() { g_hFrameWindow = (HWND)0; }
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HWND g_hFrameWindow;
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};
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// From Win32Frame
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class Win32Frame : public FrameBase
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{
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};
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// From AppleWin.cpp
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FrameBase& GetFrame()
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{
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static Win32Frame sg_Win32Frame;
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return sg_Win32Frame;
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}
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// From CPU.cpp
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regsrec regs;
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static eCpuType g_MainCPU = CPU_65C02;
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eCpuType GetMainCpu(void)
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{
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return g_MainCPU;
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}
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// From Memory.cpp
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LPBYTE mem = NULL; // TODO: Init
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LPBYTE memdirty = NULL; // TODO: Init
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//-------------------------------------
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// From Debugger_Console.cpp
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char g_aConsolePrompt[] = ">!"; // input, assembler // NUM_PROMPTS
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char g_sConsolePrompt[] = ">"; // No, NOT Integer Basic! The nostalgic '*' "Monitor" doesn't look as good, IMHO. :-(
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Update_t ConsoleUpdate ()
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{
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return 0;
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}
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void ConsoleBufferPush ( const char * pText )
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{
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}
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// From Debugger_DisassemblerData.cpp
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DisasmData_t* Disassembly_IsDataAddress ( WORD nAddress )
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{
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return NULL;
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}
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// From Debugger_Parser.cpp
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int g_nArgRaw;
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Arg_t g_aArgRaw[ MAX_ARGS ]; // pre-processing
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Arg_t g_aArgs [ MAX_ARGS ]; // post-processing (cooked)
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bool ArgsGetValue ( Arg_t *pArg, WORD * pAddressValue_, const int nBase )
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{
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return false;
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}
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// From Debugger_Symbols.cpp
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bool FindAddressFromSymbol ( const char* pSymbol, WORD * pAddress_, int * iTable_ )
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{
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return false;
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}
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//-------------------------------------
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void init(void)
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{
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mem = (LPBYTE)VirtualAlloc(NULL,128*1024,MEM_COMMIT,PAGE_READWRITE); // alloc >64K to test wrap-around at 64K boundary
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}
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void reset(void)
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{
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regs.a = 0;
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regs.x = 0;
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regs.y = 0;
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regs.pc = 0x300;
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regs.sp = 0x1FF;
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regs.ps = 0;
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regs.bJammed = 0;
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}
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//-------------------------------------
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int GH445_test_PHn(BYTE op)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = op;
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regs.sp = 0x1FE;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != regs.sp) return 1;
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regs.sp = 0x1FF;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != regs.sp) return 1;
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regs.sp = 0x100;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != regs.sp) return 1;
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return 0;
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}
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int GH445_test_PLn(BYTE op)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = op;
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regs.sp = 0x1FE;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != (regs.sp+1)) return 1;
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regs.sp = 0x1FF;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != 0x100) return 1;
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regs.sp = 0x100;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != (regs.sp+1)) return 1;
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return 0;
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}
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int GH445_test_abs(BYTE op)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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const WORD target2 = 0x1234;
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mem[regs.pc] = op;
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mem[(regs.pc+1)&0xFFFF] = (BYTE) (target2&0xff);
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mem[(regs.pc+2)&0xFFFF] = (BYTE) ((target2>>8)&0xff);
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[2] != target2) return 1;
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return 0;
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}
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int GH445_test_jsr(void)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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WORD target2 = 0x1234;
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mem[regs.pc] = OPCODE_JSR;
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mem[(regs.pc+1)&0xFFFF] = (BYTE) (target2&0xff);
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mem[(regs.pc+2)&0xFFFF] = (BYTE) ((target2>>8)&0xff);
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regs.sp = 0x1FF;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != target2) return 1;
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regs.sp = 0x100;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != 0x1FF || TargetAddr[2] != target2) return 1;
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regs.sp = 0x101;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != target2) return 1;
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return 0;
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}
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int GH445_test_brk(void)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = OPCODE_BRK;
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regs.sp = 0x1FF;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1) return 1;
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regs.sp = 0x100;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != 0x1FF) return 1;
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regs.sp = 0x101;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1) return 1;
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return 0;
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}
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int GH445_test_rti_rts(WORD sp, const bool isRTI)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = isRTI ? OPCODE_RTI : OPCODE_RTS;
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regs.sp = sp;
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WORD sp_addr_p=0, sp_addr_l=0, sp_addr_h=0;
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if (isRTI)
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{
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sp_addr_p = 0x100 + ((regs.sp+1)&0xFF);
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sp_addr_l = 0x100 + ((regs.sp+2)&0xFF);
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sp_addr_h = 0x100 + ((regs.sp+3)&0xFF);
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mem[sp_addr_p] = 0xEA;
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}
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else
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{
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sp_addr_l = 0x100 + ((regs.sp+1)&0xFF);
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sp_addr_h = 0x100 + ((regs.sp+2)&0xFF);
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}
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WORD ret_addr = 0x1234;
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mem[sp_addr_l] = (BYTE) (ret_addr&0xFF);
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mem[sp_addr_h] = (BYTE) ((ret_addr>>8)&0xFF);
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if (!isRTI)
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ret_addr++; // NB. return addr from stack is incremented before being transferred to PC
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != sp_addr_l || TargetAddr[1] != sp_addr_h || TargetAddr[2] != ret_addr) return 1;
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return 0;
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}
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int GH445_test_jmp(BYTE op)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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const WORD target16 = 0x1234;
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int target0=0, target1=0, target2=0;
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if (op == OPCODE_JMP_A)
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{
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target0 = NO_6502_TARGET;
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target1 = NO_6502_TARGET;
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target2 = target16;
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}
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else if (op == OPCODE_JMP_NA)
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{
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target0 = target16;
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target1 = (target16+1)&0xffff;
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target2 = 0x5678;
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mem[target0] = target2 & 0xff;
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mem[target1] = (target2>>8) & 0xff;
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}
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else if (op == OPCODE_JMP_IAX)
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{
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target0 = (target16+regs.x)&0xffff;
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target1 = (target16+regs.x+1)&0xffff;
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target2 = 0xABCD;
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mem[target0] = target2 & 0xff;
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mem[target1] = (target2>>8) & 0xff;
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}
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else
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{
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_ASSERT(0);
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}
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mem[regs.pc] = op;
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mem[(regs.pc+1)&0xFFFF] = (BYTE) (target16&0xff);
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mem[(regs.pc+2)&0xFFFF] = (BYTE) ((target16>>8)&0xff);
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != target0 || TargetAddr[1] != target1 || TargetAddr[2] != target2) return 1;
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return 0;
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}
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// bIgnoreBranch == true (default)
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int GH445_test_Bcc(void)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = 0x10; // BPL next-op
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mem[regs.pc+1] = 0;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != NO_6502_TARGET || TargetAddr[1] != NO_6502_TARGET || TargetAddr[2] != NO_6502_TARGET) return 1;
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mem[regs.pc] = 0x10; // BPL this-op
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mem[regs.pc+1] = 0xfe;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes);
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if (!bRes || TargetAddr[0] != NO_6502_TARGET || TargetAddr[1] != NO_6502_TARGET || TargetAddr[2] != NO_6502_TARGET) return 1;
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return 0;
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}
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int GH445_test_sub(bool bIs65C02)
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{
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int res;
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mem[0x10000] = 0xDD; // Bad data if 64K wrap not working
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mem[0x10001] = 0xDD;
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mem[0x200] = 0xDD; // Bad data if SP wrap not working
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mem[0x201] = 0xDD;
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regs.pc = 0x300;
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//
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// PHn/PLn
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res = GH445_test_PHn(0x08); // PHP
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if (res) return res;
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res = GH445_test_PHn(0x48); // PHA
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if (res) return res;
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if (bIs65C02)
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{
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res = GH445_test_PHn(0x5A); // PHY
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if (res) return res;
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res = GH445_test_PHn(0xDA); // PHX
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if (res) return res;
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}
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//
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res = GH445_test_PLn(0x28); // PLP
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if (res) return res;
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res = GH445_test_PLn(0x68); // PLA
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if (res) return res;
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if (bIs65C02)
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{
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res = GH445_test_PLn(0x7A); // PLY
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if (res) return res;
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res = GH445_test_PLn(0xFA); // PLX
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if (res) return res;
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}
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//
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// LDA abs
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regs.pc = 0xFFFD;
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res = GH445_test_abs(OPCODE_LDA_A); // LDA ABS
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if (res) return res;
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regs.pc = 0xFFFE;
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res = GH445_test_abs(OPCODE_LDA_A); // LDA ABS
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if (res) return res;
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regs.pc = 0xFFFF;
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res = GH445_test_abs(OPCODE_LDA_A); // LDA ABS
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if (res) return res;
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//
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// JSR abs
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res = GH445_test_jsr();
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if (res) return res;
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//
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// BRK
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mem[_6502_BRK_VECTOR+0] = 0x40; // BRK vector: $FA40
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mem[_6502_BRK_VECTOR+1] = 0xFA;
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regs.pc = 0x300;
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res = GH445_test_brk();
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if (res) return res;
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//
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// RTI
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res = GH445_test_rti_rts(0x1FE, true);
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if (res) return res;
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res = GH445_test_rti_rts(0x1FF, true);
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if (res) return res;
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res = GH445_test_rti_rts(0x100, true);
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if (res) return res;
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//
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// RTS
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res = GH445_test_rti_rts(0x1FE, false);
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if (res) return res;
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res = GH445_test_rti_rts(0x1FF, false);
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if (res) return res;
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res = GH445_test_rti_rts(0x100, false);
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if (res) return res;
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//
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// JMP
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res = GH445_test_jmp(OPCODE_JMP_A); // JMP abs
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if (res) return res;
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res = GH445_test_jmp(OPCODE_JMP_NA); // JMP (abs)
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if (res) return res;
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if (bIs65C02)
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{
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regs.x = 0xff;
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res = GH445_test_jmp(OPCODE_JMP_IAX); // JMP (abs,x)
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if (res) return res;
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}
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//
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// Bcc
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res = GH445_test_Bcc();
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if (res) return res;
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return 0;
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}
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int GH445_test(void)
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{
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int res;
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g_aOpcodes = g_aOpcodes65C02;
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res = GH445_test_sub(true);
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if (res) return res;
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g_aOpcodes = g_aOpcodes6502;
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res = GH445_test_sub(false);
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return res;
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}
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//-------------------------------------
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//
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// bIncludeNextOpcodeAddress == false, check that:
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// . TargetAddr[2] gets set, eg. for LDA abs
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// . TargetAddr[2] == NO_6502_TARGET for control flow instructions, eg. BRK,RTI,RTS,JSR,JMP,Bcc
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//
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int GH451_test_abs(BYTE op)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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const WORD target2 = 0x1234;
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mem[regs.pc] = op;
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mem[(regs.pc+1)&0xFFFF] = (BYTE) (target2&0xff);
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mem[(regs.pc+2)&0xFFFF] = (BYTE) ((target2>>8)&0xff);
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
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if (!bRes || TargetAddr[2] != target2) return 1;
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return 0;
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}
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int GH451_test_jsr(void)
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{
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bool bRes;
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int TargetAddr[3];
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int TargetBytes;
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mem[regs.pc] = OPCODE_JSR;
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regs.sp = 0x1FF;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != NO_6502_TARGET) return 1;
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regs.sp = 0x100;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != 0x1FF || TargetAddr[2] != NO_6502_TARGET) return 1;
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regs.sp = 0x101;
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bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
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if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != NO_6502_TARGET) return 1;
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return 0;
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}
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int GH451_test_brk(void)
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{
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bool bRes;
|
|
int TargetAddr[3];
|
|
int TargetBytes;
|
|
|
|
mem[regs.pc] = OPCODE_BRK;
|
|
|
|
regs.sp = 0x1FF;
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
regs.sp = 0x100;
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != 0x1FF || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
regs.sp = 0x101;
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != regs.sp || TargetAddr[1] != regs.sp-1 || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH451_test_rti_rts(WORD sp, const bool isRTI)
|
|
{
|
|
bool bRes;
|
|
int TargetAddr[3];
|
|
int TargetBytes;
|
|
|
|
mem[regs.pc] = isRTI ? OPCODE_RTI : OPCODE_RTS;
|
|
regs.sp = sp;
|
|
|
|
WORD sp_addr_p=0, sp_addr_l=0, sp_addr_h=0;
|
|
if (isRTI)
|
|
{
|
|
sp_addr_p = 0x100 + ((regs.sp+1)&0xFF);
|
|
sp_addr_l = 0x100 + ((regs.sp+2)&0xFF);
|
|
sp_addr_h = 0x100 + ((regs.sp+3)&0xFF);
|
|
mem[sp_addr_p] = 0xEA;
|
|
}
|
|
else
|
|
{
|
|
sp_addr_l = 0x100 + ((regs.sp+1)&0xFF);
|
|
sp_addr_h = 0x100 + ((regs.sp+2)&0xFF);
|
|
}
|
|
|
|
WORD ret_addr = 0x1234;
|
|
mem[sp_addr_l] = (BYTE) (ret_addr&0xFF);
|
|
mem[sp_addr_h] = (BYTE) ((ret_addr>>8)&0xFF);
|
|
|
|
if (!isRTI)
|
|
ret_addr++; // NB. return addr from stack is incremented before being transferred to PC
|
|
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != sp_addr_l || TargetAddr[1] != sp_addr_h || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH451_test_jmp(BYTE op)
|
|
{
|
|
bool bRes;
|
|
int TargetAddr[3];
|
|
int TargetBytes;
|
|
|
|
const WORD target16 = 0x1234;
|
|
|
|
int target0=0, target1=0;
|
|
if (op == OPCODE_JMP_A)
|
|
{
|
|
target0 = NO_6502_TARGET;
|
|
target1 = NO_6502_TARGET;
|
|
}
|
|
else if (op == OPCODE_JMP_NA)
|
|
{
|
|
target0 = target16;
|
|
target1 = (target16+1)&0xffff;
|
|
}
|
|
else if (op == OPCODE_JMP_IAX)
|
|
{
|
|
target0 = (target16+regs.x)&0xffff;
|
|
target1 = (target16+regs.x+1)&0xffff;
|
|
}
|
|
else
|
|
{
|
|
_ASSERT(0);
|
|
}
|
|
|
|
mem[regs.pc] = op;
|
|
mem[(regs.pc+1)&0xFFFF] = (BYTE) (target16&0xff);
|
|
mem[(regs.pc+2)&0xFFFF] = (BYTE) ((target16>>8)&0xff);
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != target0 || TargetAddr[1] != target1 || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
// bIgnoreBranch == true
|
|
int GH451_test_Bcc(void)
|
|
{
|
|
bool bRes;
|
|
int TargetAddr[3];
|
|
int TargetBytes;
|
|
|
|
mem[regs.pc] = 0x10; // BPL next-op
|
|
mem[regs.pc+1] = 0;
|
|
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != NO_6502_TARGET || TargetAddr[1] != NO_6502_TARGET || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
mem[regs.pc] = 0x10; // BPL this-op
|
|
mem[regs.pc+1] = 0xfe;
|
|
|
|
bRes = _6502_GetTargets(regs.pc, &TargetAddr[0], &TargetAddr[1], &TargetAddr[2], &TargetBytes, true, false);
|
|
if (!bRes || TargetAddr[0] != NO_6502_TARGET || TargetAddr[1] != NO_6502_TARGET || TargetAddr[2] != NO_6502_TARGET) return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int GH451_test_sub(bool bIs65C02)
|
|
{
|
|
int res;
|
|
|
|
mem[0x10000] = 0xDD; // Bad data if 64K wrap not working
|
|
mem[0x10001] = 0xDD;
|
|
|
|
mem[0x200] = 0xDD; // Bad data if SP wrap not working
|
|
mem[0x201] = 0xDD;
|
|
|
|
regs.pc = 0x300;
|
|
|
|
//
|
|
// LDA abs
|
|
|
|
res = GH451_test_abs(OPCODE_LDA_A);
|
|
if (res) return res;
|
|
|
|
//
|
|
// JSR abs
|
|
|
|
res = GH451_test_jsr();
|
|
if (res) return res;
|
|
|
|
//
|
|
// BRK
|
|
|
|
mem[_6502_BRK_VECTOR+0] = 0x40; // BRK vector: $FA40
|
|
mem[_6502_BRK_VECTOR+1] = 0xFA;
|
|
|
|
res = GH451_test_brk();
|
|
if (res) return res;
|
|
|
|
//
|
|
// RTI
|
|
|
|
res = GH451_test_rti_rts(0x1FE, true);
|
|
if (res) return res;
|
|
res = GH451_test_rti_rts(0x1FF, true);
|
|
if (res) return res;
|
|
res = GH451_test_rti_rts(0x100, true);
|
|
if (res) return res;
|
|
|
|
//
|
|
// RTS
|
|
|
|
res = GH451_test_rti_rts(0x1FE, false);
|
|
if (res) return res;
|
|
res = GH451_test_rti_rts(0x1FF, false);
|
|
if (res) return res;
|
|
res = GH451_test_rti_rts(0x100, false);
|
|
if (res) return res;
|
|
|
|
//
|
|
// JMP
|
|
|
|
res = GH451_test_jmp(OPCODE_JMP_A); // JMP abs
|
|
if (res) return res;
|
|
|
|
res = GH451_test_jmp(OPCODE_JMP_NA); // JMP (abs)
|
|
if (res) return res;
|
|
|
|
if (bIs65C02)
|
|
{
|
|
regs.x = 0xff;
|
|
res = GH451_test_jmp(OPCODE_JMP_IAX); // JMP (abs),x
|
|
if (res) return res;
|
|
}
|
|
|
|
//
|
|
// Bcc
|
|
|
|
res = GH451_test_Bcc();
|
|
if (res) return res;
|
|
|
|
return 0;
|
|
}
|
|
|
|
// debugger command 'bpm[r|w] addr16': JSR abs should not trigger a breakpoint at addr16
|
|
// . similarly for all other control flow opcodes (eg. Bcc, BRK, JMP, RTI, RTS)
|
|
int GH451_test(void)
|
|
{
|
|
int res;
|
|
|
|
g_aOpcodes = g_aOpcodes65C02;
|
|
res = GH451_test_sub(true);
|
|
if (res) return res;
|
|
|
|
g_aOpcodes = g_aOpcodes6502;
|
|
res = GH451_test_sub(false);
|
|
|
|
return res;
|
|
}
|
|
|
|
//-------------------------------------
|
|
|
|
int _tmain(int argc, _TCHAR* argv[])
|
|
{
|
|
int res = 1;
|
|
init();
|
|
reset();
|
|
|
|
res = GH445_test();
|
|
if (res) return res;
|
|
|
|
res = GH451_test();
|
|
if (res) return res;
|
|
|
|
return 0;
|
|
}
|