mirror of https://github.com/trudnai/Steve2.git
Page Table removed
This commit is contained in:
tudnai
parent
7e6ea1dc32
commit
1b2cf4d74e
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@ -888,8 +888,6 @@ void rom_loadFile( const char * bundlePath, const char * filename ) {
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else if ( flen == 16 * KB ) {
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read_rom( bundlePath, filename, Apple2_16K_ROM, 0);
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memcpy(Apple2_64K_MEM + 0xC000, Apple2_16K_ROM, 16 * KB);
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// SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
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}
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else if ( flen == 12 * KB ) {
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@ -18,8 +18,6 @@ INLINE void PUSH( uint8_t src ) {
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}
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INLINE uint8_t POP() {
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// return RAM[ stack_base_addr | ++m6502.SP ];
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// return *( RAM_PG_RD_TBL[ stack_base_addr >> 8 ] + ++m6502.SP );
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return RDLOMEM[ stack_base_addr | ++m6502.SP ];
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}
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@ -188,72 +188,6 @@ uint8_t * const WRHIMEM = Apple2_Dummy_RAM; // Pointer to the Shadow Memory
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NULL, \
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NULL
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uint8_t * RAM_PG_RD_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xB0),
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// I/O Addresses
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xC0),
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// Reading from the ROM
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x10), // D0
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x20), // E0
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x30) // F0
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};
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uint8_t * RAM_PG_WR_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xB0),
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// I/O Addresses
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// DEF_RAM_DUMMY16,
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xC0),
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// DEF_RAM_PAGE(Apple2_64K_RAM, 0xC0),
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// // SLOT ROM is non-writeable
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 01
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 02
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 03
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 04
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 05
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 06
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 07
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 08
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 09
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0A
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0B
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0C
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0D
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0E
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0F
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// NO Writing to the ROM
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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};
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enum slot {
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SLOT0 = 0x00,
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@ -362,46 +296,8 @@ enum mmio {
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void resetMemory() {
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// 48K main memory
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x00, Apple2_64K_MEM, 0x00)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x10, Apple2_64K_MEM, 0x10)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x20, Apple2_64K_MEM, 0x20)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x30, Apple2_64K_MEM, 0x30)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x40, Apple2_64K_MEM, 0x40)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x50, Apple2_64K_MEM, 0x50)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x60, Apple2_64K_MEM, 0x60)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x70, Apple2_64K_MEM, 0x70)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x80, Apple2_64K_MEM, 0x80)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x90, Apple2_64K_MEM, 0x90)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xA0, Apple2_64K_MEM, 0xA0)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xB0, Apple2_64K_MEM, 0xB0)
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// I/O Addresses
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xC0, Apple2_64K_MEM, 0xC0)
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// Reading from the ROM
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_16K_ROM, 0x10) // D0
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_ROM, 0x20) // E0
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_ROM, 0x30) // F0
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// 48K main memory
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x00, Apple2_64K_MEM, 0x00)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x10, Apple2_64K_MEM, 0x10)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x20, Apple2_64K_MEM, 0x20)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x30, Apple2_64K_MEM, 0x30)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x40, Apple2_64K_MEM, 0x40)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x50, Apple2_64K_MEM, 0x50)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x60, Apple2_64K_MEM, 0x60)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x70, Apple2_64K_MEM, 0x70)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x80, Apple2_64K_MEM, 0x80)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x90, Apple2_64K_MEM, 0x90)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xA0, Apple2_64K_MEM, 0xA0)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xB0, Apple2_64K_MEM, 0xB0)
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// I/O Addresses
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xC0, Apple2_64K_MEM, 0xC0)
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// NO Writing to the ROM
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
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// Reset memory configuration
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MEMcfg.RAM_16K = 0;
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MEMcfg.RAM_128K = 1;
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MEMcfg.RD_RAM = 0;
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@ -442,8 +338,6 @@ void textPageSelect() {
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// load the content of Video Page 2
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memcpy(shadow, Apple2_64K_AUX, 0x400);
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SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_MEM, 0x04)
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SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_MEM, 0x04)
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}
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else {
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// save the content of Shadow Memory
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@ -452,8 +346,6 @@ void textPageSelect() {
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// load the content of Video Page 2
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memcpy(shadow, Apple2_64K_RAM, 0x400);
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SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_MEM, 0x04)
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SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_MEM, 0x04)
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}
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}
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@ -473,8 +365,6 @@ void auxMemorySelect() {
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// load the content of Aux Memory
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memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_AUX, 0xA00);
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SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
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}
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else {
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memory = Apple2_64K_RAM + 0x200;
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@ -484,20 +374,17 @@ void auxMemorySelect() {
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// load the content of Int Memory
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memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_RAM, 0xA00);
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SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
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}
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if ( MEMcfg.WR_AUX_MEM ) {
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SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
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// TODO: set write table for AUX
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}
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else {
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SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
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// TODO: set write table for RAM
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}
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}
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else {
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SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
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SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
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// TODO: set read table for RAM
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}
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// load new content to shadow memory
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@ -649,9 +536,6 @@ INLINE uint8_t ioRead( uint16_t addr ) {
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memcpy(Apple2_64K_MEM + 0xD000, Apple2_64K_AUX, 0x3000);
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// set the RAM extension to read on the upper memory area
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, RAM_BANK, 0x00 );
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_64K_AUX, 0xE0 );
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_64K_AUX, 0xF0 );
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break;
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default:
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@ -664,9 +548,6 @@ INLINE uint8_t ioRead( uint16_t addr ) {
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memcpy(Apple2_64K_MEM + 0xD000, Apple2_16K_ROM + 0x1000, 0x3000);
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// set the ROM to read on the upper memory area
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_16K_ROM, 0x10 );
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_ROM, 0x20 );
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_ROM, 0x30 );
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break;
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}
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@ -678,17 +559,11 @@ INLINE uint8_t ioRead( uint16_t addr ) {
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case io_MEM_RDRAM_WRAM_1:
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MEMcfg.WR_RAM = 1;
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// set the RAM extension to read from the upper memory area
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, RAM_BANK, 0x00 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_64K_AUX, 0xE0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_64K_AUX, 0xF0 );
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break;
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default:
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MEMcfg.WR_RAM = 0;
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// set the ROM to read on the upper memory area
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
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break;
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}
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@ -826,38 +701,36 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
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case io_SETSTDZP:
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MEMcfg.ALT_ZP = 0;
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SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_RAM);
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SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_RAM);
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// TODO: set zero page table to RAM
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break;
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case io_SETALTZP:
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MEMcfg.ALT_ZP = 1;
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SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_AUX);
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SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_AUX);
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// TODO: set zero page table to AUX
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break;
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case io_SETSLOTCXROM:
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// printf("io_SETSLOTCXROM\n");
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MEMcfg.int_Cx_ROM = 0;
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SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_64K_RAM, 0xC0);
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// TODO: set Cx00 ROM area table to SLOT
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break;
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case io_SETINTCXROM:
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// printf("io_SETINTCXROM\n");
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MEMcfg.int_Cx_ROM = 1;
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SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
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// TODO: set Cx00 ROM area table to INT
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break;
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case io_SETSLOTC3ROM:
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// printf("io_SETSLOTC3ROM\n");
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MEMcfg.slot_C3_ROM = 1;
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SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_64K_RAM, 0xC3);
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// TODO: set C300 ROM area table to SLOT
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break;
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case io_SETINTC3ROM:
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// printf("io_SETINTC3ROM\n");
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MEMcfg.slot_C3_ROM = 0;
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SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_16K_ROM, 0x03);
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// TODO: set C300 ROM area table to INT
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break;
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case io_VID_CLR80VID:
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@ -914,10 +787,6 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
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/**
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Naive implementation of RAM read from address
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**/
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INLINE uint8_t memread8_paged( uint16_t addr ) {
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return * ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
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// return RAM[addr];
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}
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INLINE uint8_t memread8_low( uint16_t addr ) {
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return RDLOMEM[addr];
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}
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@ -997,7 +866,6 @@ INLINE void memwrite( uint16_t addr, uint8_t data ) {
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ioWrite(addr, data);
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}
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else {
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// *(RAM_PG_WR_TBL[ addr >> 8 ] + (addr & 0xFF)) = data;
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memwrite8_high(addr, data);
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}
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}
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@ -1005,15 +873,6 @@ INLINE void memwrite( uint16_t addr, uint8_t data ) {
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memwrite8_low(addr, data);
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}
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// // I/O or ROM or RAM EXP
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// if ( ( addr >= 0xC000 ) && ( addr < 0xC100 ) ) {
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// return ioWrite( addr, src );
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// }
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//
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// // DO NOT MAKE IT NICER! faster this way!
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// *(RAM_PG_WR_TBL[ addr >> 8 ] + (addr & 0xFF)) = src;
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//// RAM[addr] = src;
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//
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}
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/**
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