Merge branch 'speedbump'

This commit is contained in:
tudnai 2020-05-01 19:54:40 -07:00
commit 5ee910b681
61 changed files with 1962834 additions and 286 deletions

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#!/usr/bin/perl
my $state = 'begin';
my $trk = 0;
my $sec = 0;
my @sectorData = ();
my $reLDA_C08C = qr/LDA\s+\$C08C,X\t0x([8-9A-Fa-f][0-9A-Fa-f])/;
my $reLDY_C08C = qr/LDY\s+\$C08C,X\t0x([0-9A-Fa-f]{2})\t0x([0-9A-Fa-f]{2})\t0x([8-9A-Fa-f][0-9A-F])/;
my $reSTA_0300 = qr/STA\s+\$0300,Y\t0x([0-9A-F]{2})\t0x([0-9A-F]{2})\t0x([0-9A-F]{2})/;
my $reSTA_26Y = qr/STA\s+\(\$26\),Y\t0x([0-9A-F]{2})\t0x([0-9A-F]{2})\t0x([0-9A-F]{2})/;
sub hexdump {
my ($arr) = @_;
for($i = 0; $i < scalar(@{$arr}); $i++) {
if ( $i % 16 == 0 ) {
printf("\n%04X: ", $i);
}
printf("%02X ", @{$arr}[$i]);
}
print "\n";
}
while (<>) {
chomp;
s/[\n\r]+//;
print;
{ # for the redo to avoid print input twice
if ( $state eq 'begin' ) {
if ( /LDA\s+\$C08C,X\t0xD5/ ) {
print "\t marker D5";
$state = 'loaded_D5';
}
}
elsif ( $state eq 'loaded_D5' ) {
if ( /LDA\s+\$C08C,X\t0xAA/ ) {
print "\t marker AA";
$state = 'loaded_AA';
}
elsif ( /$reLDA_C08C/ ) {
$state = 'begin';
redo;
}
}
elsif ( $state eq 'loaded_AA' ) {
if ( /LDA\s+\$C08C,X\t0x96/ ) {
print "\t marker 96";
$state = 'loaded_96';
print "\t; sector marker";
}
elsif ( /$reLDA_C08C/ ) {
$state = 'begin';
redo;
}
}
elsif ( $state eq 'loaded_96' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker v1";
$state = 'loaded_v1';
}
}
elsif ( $state eq 'loaded_v1' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker v2";
$state = 'loaded_v2';
}
}
elsif ( $state eq 'loaded_v2' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker t1:$1";
$trk = hex($1) << 1;
$trk |= 1;
$state = 'loaded_t1';
}
}
elsif ( $state eq 'loaded_t1' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker t2:$1";
$trk &= hex($1);
print "\t; trk:$trk";
$state = 'loaded_t2';
}
}
elsif ( $state eq 'loaded_t2' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker s1:$1";
$sec = hex($1) << 1;
$sec |= 1;
$state = 'loaded_s1';
}
}
elsif ( $state eq 'loaded_s1' ) {
if ( /$reLDA_C08C/ ) {
print "\t marker s2:$1";
$sec &= hex($1);
print "\t; sec:$sec";
$state = 'loaded_s2';
}
}
elsif ( $state eq 'loaded_s2' ) {
if ( /LDA\s+\$C08C,X\t0xD5/ ) {
print "\t marker D5";
$state = 'waitingfor_AA';
}
elsif ( /EOR\s+#\$D5/ ) {
$state = 'begin';
redo;
}
}
elsif ( $state eq 'waitingfor_AA' ) {
if ( /LDA\s+\$C08C,X\t0xAA/ ) {
print "\t marker AA 2";
$state = 'waitingfor_AD';
}
elsif ( /$reLDA_C08C/ ) {
$state = 'begin';
redo;
}
}
elsif ( $state eq 'waitingfor_AD' ) {
if ( /LDA\s+\$C08C,X\t0xAD/ ) {
print "\t marker AD";
$state = 'loaded_AD';
print "\t; sector data marker";
}
elsif ( /EOR\s+#\$D5/ ) {
$state = 'begin';
redo;
}
}
elsif ( $state eq 'loaded_AD' ) {
if ( /$reLDY_C08C/ ) {
print "\t byte read: $3 (t:$trk s:$sec)";
}
elsif ( /$reSTA_0300/ ) {
printf( "\t byte to mem: \$%04X:$1\n", 0x300 + hex($3) );
}
elsif ( /$reSTA_26Y/ ) {
my $y = hex($3);
printf( "\t byte to mem ind: (\$26)+\$%02X:$1\n", $y );
if ($y >= 255) {
$state = 'sector_decode';
}
}
}
elsif ( $state eq 'sector_decode' ) {
if ( /$reSTA_26Y/ ) {
$i = hex($1);
$y = hex($3);
printf( "\t byte to mem ind: (\$26)+\$%02X:$1\n", $y );
$sectorData[$y] = $i;
if ($y >= 255) {
$state = 'sector_decode';
print "\nHEXDUMP track: $trk sector: $sec\n";
hexdump(\@sectorData);
}
}
elsif ( /$reLDA_C08C/ ) {
$state = 'begin';
redo;
}
}
} # for the redo to avoid print input twice
print "\n";
}

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6502_functional_test.lst Normal file

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<array/>
</plist>

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<?xml version="1.0" encoding="UTF-8"?>
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version = "1.0">
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contextName = "AND:6502_instr_logic.h">
</ContextState>
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<PersistentStrings>
<PersistentString
value = "test">
</PersistentString>
</PersistentStrings>
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</ContextState>
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contextName = "read_rom:6502.c">
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value = "Apple2_64K_AUX + 0xC600">
</PersistentString>
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value = "Apple2_64K_RAM + 0xC600">
</PersistentString>
<PersistentString
value = "(void*)rom">
</PersistentString>
<PersistentString
value = "strlen(fullPath)">
</PersistentString>
<PersistentString
value = "(void*)Apple2_64K_RAM">
</PersistentString>
</PersistentStrings>
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<ContextState
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<PersistentString
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<PersistentString
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</PersistentString>
<PersistentString
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</PersistentString>
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</PersistentString>
<PersistentString
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</PersistentString>
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</PersistentString>
<PersistentString
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@ -811,7 +811,7 @@
<constraint firstAttribute="width" constant="1120" id="uez-Mi-0Sh"/>
<constraint firstAttribute="height" constant="768" id="zl6-au-oZj"/>
</constraints>
<textFieldCell key="cell" scrollable="YES" lineBreakMode="clipping" refusesFirstResponder="YES" allowsUndo="NO" sendsActionOnEndEditing="YES" state="on" baseWritingDirection="leftToRight" id="pIk-RC-s5g">
<textFieldCell key="cell" scrollable="YES" lineBreakMode="clipping" selectable="YES" refusesFirstResponder="YES" allowsUndo="NO" sendsActionOnEndEditing="YES" state="on" baseWritingDirection="leftToRight" id="pIk-RC-s5g">
<font key="font" size="32" name="PrintChar21"/>
<string key="title">1234567890123456789012345678901234567890
@@@@@@@@@1@@@@@@@@@2@@@@@@@@@3@@@@@@@@@4

View File

@ -25,9 +25,9 @@ class HiRes: NSView {
static let blockWidth = PixelWidth / blockCols
static let blockHeight = PixelHeight / blockRows
let HiResBuffer1 = UnsafeRawBufferPointer(start: RAM + Page1Addr, count: PageSize * 2)
let HiResBuffer2 = UnsafeRawBufferPointer(start: RAM + Page2Addr, count: PageSize * 2)
var HiResBufferPointer = UnsafeRawBufferPointer(start: RAM + Page1Addr, count: PageSize * 2)
let HiResBuffer1 = UnsafeRawBufferPointer(start: MEM + Page1Addr, count: PageSize * 2)
let HiResBuffer2 = UnsafeRawBufferPointer(start: MEM + Page2Addr, count: PageSize * 2)
var HiResBufferPointer = UnsafeRawBufferPointer(start: MEM + Page1Addr, count: PageSize * 2)
let HiResRawPointer = UnsafeRawPointer(RAM + Page1Addr)

View File

@ -164,8 +164,8 @@ class ViewController: NSViewController {
// static let blockChar : Character = ""
// static var flashingSpace : Character = " "
let ramBufferPointer = UnsafeRawBufferPointer(start: RAM, count: 64 * 1024)
let textBufferPointer = UnsafeRawBufferPointer(start: RAM + textBaseAddr, count: textBufferSize * 2)
let ramBufferPointer = UnsafeRawBufferPointer(start: MEM, count: 64 * 1024)
let textBufferPointer = UnsafeRawBufferPointer(start: MEM + textBaseAddr, count: textBufferSize * 2)
let textAuxBufferPointer = UnsafeRawBufferPointer(start: AUX + textBaseAddr, count: textBufferSize)
static let textArraySize = textLines * (textCols + lineEndChars) + textCols * 2
@ -382,9 +382,11 @@ class ViewController: NSViewController {
var halted = true;
func Update() {
clk_6502_per_frm_max = 0
// clk_6502_per_frm_max = 0
clkCounter += Double(clkfrm)
// we start a new frame from here, so CPU is running even while rendering
clkfrm = 0
frameCounter += 1
@ -403,6 +405,7 @@ class ViewController: NSViewController {
// return
frameCnt += 1
if ( frameCnt == fps / 2 ) {
// flashingSpace = blockChar
ViewController.charConvTbl = ViewController.charConvTblFlashOn
@ -413,65 +416,68 @@ class ViewController: NSViewController {
frameCnt = 0
}
var txt : String = ""
var fromLines = 0
var toLines = textLines
// Rendering is happening in the main thread, which has two implications:
// 1. We can update UI elements
// 2. it is independent of the simulation, de that is running in the background thread while we are busy with rendering...
DispatchQueue.main.async {
var txt : String = ""
var fromLines = 0
var toLines = self.textLines
if videoMode.text == 0 {
if videoMode.mixed == 1 {
fromLines = toLines - 4
}
else {
toLines = 0
}
}
txtArr = txtClear
// render an empty space to eiminate displaying text portion of the screen covered by graphics
for y in 0 ..< fromLines {
if videoMode.col80 == 0 {
txtArr[ y * (textCols + lineEndChars) + textCols ] = "\n"
}
else {
txtArr[ y * (textCols * 2 + lineEndChars) + textCols * 2] = "\n"
}
}
// render the rest of the text screen
for y in fromLines ..< toLines {
for x in 0 ..< textCols {
let byte = textBufferPointer[ textLineOfs[y] + x ]
let idx = Int(byte);
let chr = ViewController.charConvTbl[idx]
if videoMode.col80 == 0 {
txtArr[ y * (textCols + lineEndChars) + x ] = chr
if videoMode.text == 0 {
if videoMode.mixed == 1 {
fromLines = toLines - 4
}
else {
txtArr[ y * (textCols * 2 + lineEndChars) + x * 2 + 1] = chr
toLines = 0
}
}
let byte = textAuxBufferPointer[ textLineOfs[y] + x ]
self.txtArr = self.txtClear
// render an empty space to eiminate displaying text portion of the screen covered by graphics
for y in 0 ..< fromLines {
if videoMode.col80 == 0 {
self.txtArr[ y * (self.textCols + self.lineEndChars) + self.textCols ] = "\n"
}
else {
self.txtArr[ y * (self.textCols * 2 + self.lineEndChars) + self.textCols * 2] = "\n"
}
}
// render the rest of the text screen
for y in fromLines ..< toLines {
for x in 0 ..< self.textCols {
let byte = self.textBufferPointer[ self.textLineOfs[y] + x ]
let idx = Int(byte);
let chr = ViewController.charConvTbl[idx]
txtArr[ y * (textCols * 2 + lineEndChars) + x * 2] = chr
if videoMode.col80 == 0 {
self.txtArr[ y * (self.textCols + self.lineEndChars) + x ] = chr
}
else {
self.txtArr[ y * (self.textCols * 2 + self.lineEndChars) + x * 2 + 1] = chr
let byte = self.textAuxBufferPointer[ self.textLineOfs[y] + x ]
let idx = Int(byte);
let chr = ViewController.charConvTbl[idx]
self.txtArr[ y * (self.textCols * 2 + self.lineEndChars) + x * 2] = chr
}
}
if videoMode.col80 == 0 {
self.txtArr[ y * (self.textCols + self.lineEndChars) + self.textCols ] = "\n"
}
else {
self.txtArr[ y * (self.textCols * 2 + self.lineEndChars) + self.textCols * 2] = "\n"
}
}
if videoMode.col80 == 0 {
txtArr[ y * (textCols + lineEndChars) + textCols ] = "\n"
}
else {
txtArr[ y * (textCols * 2 + lineEndChars) + textCols * 2] = "\n"
}
}
txt = String(txtArr)
txt = String(self.txtArr)
DispatchQueue.main.async {
if videoMode.col80 != self.currentVideoMode.col80 {
self.currentVideoMode.col80 = videoMode.col80

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<?xml version="1.0" encoding="UTF-8"?>
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<plist version="1.0">
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<string>18F132</string>
<key>CFBundleDevelopmentRegion</key>
<string>en</string>
<key>CFBundleExecutable</key>
<string>A2Mac</string>
<key>CFBundleIdentifier</key>
<string>com.gamealloy.A2Mac</string>
<key>CFBundleInfoDictionaryVersion</key>
<string>6.0</string>
<key>CFBundleName</key>
<string>A2Mac</string>
<key>CFBundlePackageType</key>
<string>APPL</string>
<key>CFBundleShortVersionString</key>
<string>1.0</string>
<key>CFBundleSupportedPlatforms</key>
<array>
<string>MacOSX</string>
</array>
<key>CFBundleVersion</key>
<string>1</string>
<key>DTCompiler</key>
<string>com.apple.compilers.llvm.clang.1_0</string>
<key>DTPlatformBuild</key>
<string>10G8</string>
<key>DTPlatformVersion</key>
<string>GM</string>
<key>DTSDKBuild</key>
<string>18G74</string>
<key>DTSDKName</key>
<string>macosx10.14</string>
<key>DTXcode</key>
<string>1030</string>
<key>DTXcodeBuild</key>
<string>10G8</string>
<key>LSApplicationCategoryType</key>
<string>public.app-category.education</string>
<key>LSMinimumSystemVersion</key>
<string>10.14</string>
<key>NSHumanReadableCopyright</key>
<string>Copyright © 2019 GameAlloy. All rights reserved.</string>
<key>NSMainStoryboardFile</key>
<string>Main</string>
<key>NSPrincipalClass</key>
<string>NSApplication</string>
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@ -0,0 +1 @@
APPL????

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<?xml version="1.0" encoding="UTF-8"?>
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<key>cdhash</key>
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AI3dcMnYeote388+0kD9cxzrbMs=
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<key>requirement</key>
<string>identifier "com.apple.dt.runtime.swiftXPC" and anchor apple generic and certificate leaf[subject.CN] = "Mac Developer: Tamas Rudnai (Z7ST5Z9Q8J)" and certificate 1[field.1.2.840.113635.100.6.2.1] /* exists */</string>
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import Cocoa
var str = "Hello, playground"

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<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<playground version='5.0' target-platform='macos' executeOnSourceChanges='false'>
<timeline fileName='timeline.xctimeline'/>
</playground>

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39 100973 44567542 C674: 10 FB BPL $C671 0x2B 0x60 0x00 0x35 0xFE
40 100974 44567545 C671: BD 8C C0 LDA $C08C,X 0x56 0x60 0x00 0x35 0xFE
41 100975 44567549 C674: 10 FB BPL $C671 0x56 0x60 0x00 0x35 0xFE
42 100976 44567552 C671: BD 8C C0 LDA $C08C,X 0xAD 0x60 0x00 0xB5 0xFE
43 100977 44567556 C674: 10 FB BPL $C671 0xAD 0x60 0x00 0xB5 0xFE
44 100978 44567558 C676: C9 96 CMP #$96 0xAD 0x60 0x00 0x35 0xFE
45 100979 44567560 C678: F0 09 BEQ $C683 0xAD 0x60 0x00 0x35 0xFE
46 100980 44567562 C67A: 28 PLP 0xAD 0x60 0x00 0x37 0xFF
47 100981 44567566 C67B: 90 DF BCC $C65C 0xAD 0x60 0x00 0x37 0xFF
48 100982 44567568 C67D: 49 AD EOR #$AD 0x00 0x60 0x00 0x37 0xFF
49 100983 44567570 C67F: F0 25 BEQ $C6A6 0x00 0x60 0x00 0x37 0xFF
50 100984 44567573 C6A6: A0 56 LDY #$56 0x00 0x60 0x56 0x35 0xFF
51 100985 44567575 C6A8: 84 3C STY $3C 0x00 0x60 0x56 0x35 0xFF
52 100986 44567578 C6AA: BC 8C C0 LDY $C08C,X 0x00 0x60 0xB6 0xB5 0xFF
53 100987 44567582 C6AD: 10 FB BPL $C6AA 0x00 0x60 0xB6 0xB5 0xFF
54 100988 44567584 C6AF: 59 D6 02 EOR $02D6,Y 0x12 0x60 0xB6 0x35 0xFF
55 100989 44567589 C6B2: A4 3C LDY $3C 0x12 0x60 0x56 0x35 0xFF
56 100990 44567592 C6B4: 88 DEY 0x12 0x60 0x55 0x35 0xFF
57 100991 44567594 C6B5: 99 00 03 STA $0300,Y 0x12 0x60 0x55 0x35 0xFF
58 100992 44567599 C6B8: D0 EE BNE $C6A8 0x12 0x60 0x55 0x35 0xFF
59 100993 44567602 C6A8: 84 3C STY $3C 0x12 0x60 0x55 0x35 0xFF
60 100994 44567605 C6AA: BC 8C C0 LDY $C08C,X 0x12 0x60 0x36 0x35 0xFF
61 100995 44567609 C6AD: 10 FB BPL $C6AA 0x12 0x60 0x36 0x35 0xFF
62 100996 44567612 C6AA: BC 8C C0 LDY $C08C,X 0x12 0x60 0xDB 0xB5 0xFF
63 100997 44567616 C6AD: 10 FB BPL $C6AA 0x12 0x60 0xDB 0xB5 0xFF
64 100998 44567618 C6AF: 59 D6 02 EOR $02D6,Y 0x36 0x60 0xDB 0x35 0xFF
65 100999 44567623 C6B2: A4 3C LDY $3C 0x36 0x60 0x55 0x35 0xFF
66 101000 44567626 C6B4: 88 DEY 0x36 0x60 0x54 0x35 0xFF
67 101001 44567628 C6B5: 99 00 03 STA $0300,Y 0x36 0x60 0x54 0x35 0xFF
68 101002 44567633 C6B8: D0 EE BNE $C6A8 0x36 0x60 0x54 0x35 0xFF
69 101003 44567636 C6A8: 84 3C STY $3C 0x36 0x60 0x54 0x35 0xFF
70 101004 44567639 C6AA: BC 8C C0 LDY $C08C,X 0x36 0x60 0x6E 0x35 0xFF
71 101005 44567643 C6AD: 10 FB BPL $C6AA 0x36 0x60 0x6E 0x35 0xFF
72 101006 44567646 C6AA: BC 8C C0 LDY $C08C,X 0x36 0x60 0xDC 0xB5 0xFF
73 101007 44567650 C6AD: 10 FB BPL $C6AA 0x36 0x60 0xDC 0xB5 0xFF
74 101008 44567652 C6AF: 59 D6 02 EOR $02D6,Y 0x13 0x60 0xDC 0x35 0xFF
75 101009 44567657 C6B2: A4 3C LDY $3C 0x13 0x60 0x54 0x35 0xFF
76 101010 44567660 C6B4: 88 DEY 0x13 0x60 0x53 0x35 0xFF
77 101011 44567662 C6B5: 99 00 03 STA $0300,Y 0x13 0x60 0x53 0x35 0xFF
78 101012 44567667 C6B8: D0 EE BNE $C6A8 0x13 0x60 0x53 0x35 0xFF
79 101013 44567670 C6A8: 84 3C STY $3C 0x13 0x60 0x53 0x35 0xFF
80 101014 44567673 C6AA: BC 8C C0 LDY $C08C,X 0x13 0x60 0x7A 0x35 0xFF
81 101015 44567677 C6AD: 10 FB BPL $C6AA 0x13 0x60 0x7A 0x35 0xFF
82 101016 44567680 C6AA: BC 8C C0 LDY $C08C,X 0x13 0x60 0xF4 0xB5 0xFF
83 101017 44567684 C6AD: 10 FB BPL $C6AA 0x13 0x60 0xF4 0xB5 0xFF
84 101018 44567686 C6AF: 59 D6 02 EOR $02D6,Y 0x26 0x60 0xF4 0x35 0xFF
85 101019 44567691 C6B2: A4 3C LDY $3C 0x26 0x60 0x53 0x35 0xFF
86 101020 44567694 C6B4: 88 DEY 0x26 0x60 0x52 0x35 0xFF
87 101021 44567696 C6B5: 99 00 03 STA $0300,Y 0x26 0x60 0x52 0x35 0xFF
88 101022 44567701 C6B8: D0 EE BNE $C6A8 0x26 0x60 0x52 0x35 0xFF
89 101023 44567704 C6A8: 84 3C STY $3C 0x26 0x60 0x52 0x35 0xFF
90 101024 44567707 C6AA: BC 8C C0 LDY $C08C,X 0x26 0x60 0xF3 0xB5 0xFF
91 101025 44567711 C6AD: 10 FB BPL $C6AA 0x26 0x60 0xF3 0xB5 0xFF
92 101026 44567713 C6AF: 59 D6 02 EOR $02D6,Y 0x12 0x60 0xF3 0x35 0xFF
93 101027 44567718 C6B2: A4 3C LDY $3C 0x12 0x60 0x52 0x35 0xFF
94 101028 44567721 C6B4: 88 DEY 0x12 0x60 0x51 0x35 0xFF
95 101029 44567723 C6B5: 99 00 03 STA $0300,Y 0x12 0x60 0x51 0x35 0xFF
96 101030 44567728 C6B8: D0 EE BNE $C6A8 0x12 0x60 0x51 0x35 0xFF
97 101031 44567731 C6A8: 84 3C STY $3C 0x12 0x60 0x51 0x35 0xFF
98 101032 44567734 C6AA: BC 8C C0 LDY $C08C,X 0x12 0x60 0x5D 0x35 0xFF
99 101033 44567738 C6AD: 10 FB BPL $C6AA 0x12 0x60 0x5D 0x35 0xFF
100 101034 44567741 C6AA: BC 8C C0 LDY $C08C,X 0x12 0x60 0xBB 0xB5 0xFF
101 101035 44567745 C6AD: 10 FB BPL $C6AA 0x12 0x60 0xBB 0xB5 0xFF
102 101036 44567747 C6AF: 59 D6 02 EOR $02D6,Y 0x04 0x60 0xBB 0x35 0xFF
103 101037 44567752 C6B2: A4 3C LDY $3C 0x04 0x60 0x51 0x35 0xFF
104 101038 44567755 C6B4: 88 DEY 0x04 0x60 0x50 0x35 0xFF
105 101039 44567757 C6B5: 99 00 03 STA $0300,Y 0x04 0x60 0x50 0x35 0xFF
106 101040 44567762 C6B8: D0 EE BNE $C6A8 0x04 0x60 0x50 0x35 0xFF
107 101041 44567765 C6A8: 84 3C STY $3C 0x04 0x60 0x50 0x35 0xFF
108 101042 44567768 C6AA: BC 8C C0 LDY $C08C,X 0x04 0x60 0x5E 0x35 0xFF
109 101043 44567772 C6AD: 10 FB BPL $C6AA 0x04 0x60 0x5E 0x35 0xFF
110 101044 44567775 C6AA: BC 8C C0 LDY $C08C,X 0x04 0x60 0xBD 0xB5 0xFF
111 101045 44567779 C6AD: 10 FB BPL $C6AA 0x04 0x60 0xBD 0xB5 0xFF
112 101046 44567781 C6AF: 59 D6 02 EOR $02D6,Y 0x1C 0x60 0xBD 0x35 0xFF
113 101047 44567786 C6B2: A4 3C LDY $3C 0x1C 0x60 0x50 0x35 0xFF
114 101048 44567789 C6B4: 88 DEY 0x1C 0x60 0x4F 0x35 0xFF
115 101049 44567791 C6B5: 99 00 03 STA $0300,Y 0x1C 0x60 0x4F 0x35 0xFF
116 101050 44567796 C6B8: D0 EE BNE $C6A8 0x1C 0x60 0x4F 0x35 0xFF
117 101051 44567799 C6A8: 84 3C STY $3C 0x1C 0x60 0x4F 0x35 0xFF
118 101052 44567802 C6AA: BC 8C C0 LDY $C08C,X 0x1C 0x60 0xCF 0xB5 0xFF
119 101053 44567806 C6AD: 10 FB BPL $C6AA 0x1C 0x60 0xCF 0xB5 0xFF
120 101054 44567808 C6AF: 59 D6 02 EOR $02D6,Y 0x02 0x60 0xCF 0x35 0xFF
121 101055 44567813 C6B2: A4 3C LDY $3C 0x02 0x60 0x4F 0x35 0xFF
122 101056 44567816 C6B4: 88 DEY 0x02 0x60 0x4E 0x35 0xFF
123 101057 44567818 C6B5: 99 00 03 STA $0300,Y 0x02 0x60 0x4E 0x35 0xFF
124 101058 44567823 C6B8: D0 EE BNE $C6A8 0x02 0x60 0x4E 0x35 0xFF
125 101059 44567826 C6A8: 84 3C STY $3C 0x02 0x60 0x4E 0x35 0xFF

93
logfltr.pl Executable file
View File

@ -0,0 +1,93 @@
#!/usr/bin/perl
my $addr = "";
my $status = 0;
my @buf = ();
my $max = 5000;
while(<>) {
if ($status == 0) {
if (/([0-9A-F]{4}):( [0-9A-F]{2}){3}\s*LDA \$C08C,X/) {
# print("DEBUG: 0 LDA\n");
$status = 1;
push(@buf, $_);
$addr = $1;
}
else {
# print("DEBUG: 0 no LDA\n");
print;
}
}
elsif ($status == 1) {
if (/BPL \$$addr/) {
# print("DEBUG: 1 BPL\n");
$status = 2;
push(@buf, $_);
}
else {
# print("DEBUG: 1 no BPL\n");
$status = 0;
print @buf;
@buf = ();
print;
}
}
elsif ($status == 2) {
if (/EOR #\$D5/) {
# print("DEBUG: 2 EOR\n");
$status = 3;
push(@buf, $_);
}
else {
# print("DEBUG: 2 no EOR\n");
$status = 0;
print @buf;
@buf = ();
print;
}
}
elsif ($status == 3) {
if (/BNE \$$addr/) {
# print("DEBUG: 3 BNE\n");
$status = 4;
push(@buf, $_);
}
else {
# print("DEBUG: 3 no BNE\n");
$status = 0;
print @buf;
@buf = ();
print;
}
}
elsif ($status == 4) {
if (/$addr:( [0-9A-F]{2}){3}\s*LDA \$C08C,X/) {
# print("DEBUG: 4 LDA\n");
$status = 1;
@buf = ();
push(@buf, $_);
}
else {
# print("DEBUG: 4 no LDA\n");
$status = 0;
print @buf, "\n";
@buf = ();
print;
}
}
else {
# print("DEBUG: else\n");
$status = 0;
print @buf;
@buf = ();
print;
}
# if( -- $max <= 0 ) {
# last;
# }
}

View File

@ -713,7 +713,8 @@ void m6502_Run() {
#ifdef SPEEDTEST
for ( inst_cnt = 0; inst_cnt < iterations ; inst_cnt++ )
#elif defined( CLK_WAIT )
for ( clkfrm = 0; clkfrm < clk_6502_per_frm_max ; clkfrm += clk )
// we clear the clkfrm from ViewController Update()
for ( ; clkfrm < clk_6502_per_frm_max ; clkfrm += clk )
#else
// for ( ; m6502.pc ; )
for ( ; ; )
@ -886,28 +887,14 @@ void rom_loadFile( const char * bundlePath, const char * filename ) {
else if ( flen == 16 * KB ) {
read_rom( bundlePath, filename, Apple2_16K_ROM, 0);
memcpy(Apple2_12K_ROM + 0x0000, Apple2_16K_ROM + 0x1000, sizeof(Apple2_12K_ROM));
// memcpy(Apple2_64K_RAM + 0xC000, Apple2_16K_ROM, 0x1000);
// SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
memcpy(Apple2_64K_MEM + 0xC000, Apple2_16K_ROM, 16 * KB);
}
else if ( flen == 12 * KB ) {
read_rom( bundlePath, filename, Apple2_12K_ROM, 0);
// memcpy(Apple2_64K_RAM + 0xD000, Apple2_12K_ROM, sizeof(Apple2_12K_ROM));
read_rom( bundlePath, filename, Apple2_16K_ROM, 0x1000);
memcpy(Apple2_64K_MEM + 0xD000, Apple2_16K_ROM + 0x1000, 12 * KB);
}
// read_rom( bundlePath, "Apple2Plus.rom", Apple2_12K_ROM, 0);
// read_rom( bundlePath, "Apple2e.rom", Apple2_16K_ROM, 0);
// read_rom( bundlePath, "Apple2e_Enhanced.rom", Apple2_16K_ROM, 0);
// read_rom( "/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/", "Apple2Plus.rom", Apple2_12K_ROM, 0);
// read_rom("/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/Apple2Plus.rom", Apple2_12K_ROM, 0);
// memcpy(Apple2_64K_RAM + 0xD000, Apple2_12K_ROM, sizeof(Apple2_12K_ROM));
// memcpy(Apple2_12K_ROM + 0x0000, Apple2_16K_ROM + 0x1000, sizeof(Apple2_12K_ROM));
// memcpy(Apple2_64K_RAM + 0xC000, Apple2_16K_ROM, sizeof(Apple2_16K_ROM));
}
@ -957,7 +944,9 @@ void m6502_ColdReset( const char * bundlePath, const char * romFileName ) {
// Disk ][ ROM in Slot 6
read_rom( bundlePath, "DISK_II_C600.ROM", Apple2_64K_RAM, 0xC600);
// read_rom( "/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/", "DISK_II_C600.ROM", Apple2_64K_RAM, 0xC600);
memcpy(Apple2_64K_MEM + 0xC600, Apple2_64K_RAM + 0xC600, 0x100);
// read_rom( "/Users/trudnai/Library/Containers/com.gamealloy.A2Mac/Data/", "DISK_II_C600.ROM", Apple2_64K_MEM, 0xC600);
m6502.A = m6502.X = m6502.Y = 0xFF;
// reset vector

View File

@ -129,7 +129,7 @@ extern MEMcfg_t MEMcfg;
extern m6502_t m6502;
extern uint8_t * const AUX; // Pointer to the auxiliary memory so we can use this from Swift
extern uint8_t * const RAM;
//extern uint8_t * AUX_VID_RAM;
extern uint8_t * const MEM; // Pointer to the Shadow Memory Map so we can use this from Swift//extern uint8_t * AUX_VID_RAM;
extern uint32_t * videoMemPtr;
extern void hires_Update(void);

View File

@ -92,15 +92,7 @@ char * charConv =
**/
INLINE void STR( uint16_t addr, uint8_t src ) {
dbgPrintf("STR [%04X], %02X ", addr, src );
// I/O or ROM or RAM EXP
if ( ( addr >= 0xC000 ) && ( addr < 0xC100 ) ) {
return ioWrite( addr, src );
}
// DO NOT MAKE IT NICER! faster this way!
*(RAM_PG_WR_TBL[ addr >> 8 ] + (addr & 0xFF)) = src;
// RAM[addr] = src;
memwrite(addr, src);
}
/**

View File

@ -13,14 +13,12 @@ static const uint16_t stack_base_addr = 0x100;
INLINE void PUSH( uint8_t src ) {
// RAM[ stack_base_addr | m6502.SP-- ] = src;
// DO NOT MAKE IT NICER! faster this way!
*( RAM_PG_WR_TBL[ stack_base_addr >> 8 ] + m6502.SP-- ) = src;
WRLOMEM[ stack_base_addr | m6502.SP-- ] = src;
}
INLINE uint8_t POP() {
// return RAM[ stack_base_addr | ++m6502.SP ];
return *( RAM_PG_WR_TBL[ stack_base_addr >> 8 ] + ++m6502.SP );
return RDLOMEM[ stack_base_addr | ++m6502.SP ];
}

View File

@ -17,7 +17,7 @@ disk_t disk = {
0, // clk_since_last_read
};
const int diskAccelerator_frames = 5;
const int diskAccelerator_frames = 3;
int diskAccelerator_count = 10;
int diskAccelerator_speed = 25; // less than actual CPU speed means no acceleration
//const unsigned long long clk_6502_per_frm_diskAccelerator = 25 * M / fps; // disk acceleration bumps up CPU clock to 25 MHz

View File

@ -27,17 +27,25 @@ typedef union address16_u {
videoMode_t videoMode = { 1 }; // 40 col text, page 1
uint8_t Apple2_Dummy_Page[ 1 * PG ]; // Dummy Page for discarding data
uint8_t Apple2_Dummy_RAM[ 4 * KB ]; // Dummy RAM for discarding data
uint8_t Apple2_12K_ROM[ 12 * KB ] = {0}; // ROM D0, D8, E0, E8, F0, F8
uint8_t Apple2_16K_ROM[ 16 * KB ] = {0}; // ROM C0, C8, D0, D8, E0, E8, F0, F8
uint8_t Apple2_16K_RAM[ 16 * KB ] = {0}; // 16K Memory Expansion Card
uint8_t Apple2_64K_AUX[ 64 * KB ] = {0}; // 64K Expansion Memory
uint8_t Apple2_64K_RAM[ 64 * KB ] = {0}; // Main Memory
uint8_t Apple2_Dummy_Page[ 1 * PG ]; // Dummy Page to discard data
uint8_t Apple2_Dummy_RAM[ 64 * KB ]; // Dummy RAM to discard data
uint8_t Apple2_16K_ROM[ 16 * KB ] = {0}; // ROM C0, C8, D0, D8, E0, E8, F0, F8
uint8_t Apple2_64K_AUX[ 64 * KB ] = {0}; // 64K Expansion Memory
uint8_t Apple2_64K_RAM[ 64 * KB ] = {0}; // Main Memory
uint8_t Apple2_64K_MEM[ 64 * KB ] = {0}; // Shadow Copy of Memory (or current memory content)
//uint8_t * AUX_VID_RAM = Apple2_VID_AUX; // Pointer to Auxiliary Video Memory
uint8_t * const AUX = Apple2_64K_AUX; // Pointer to the Auxiliary Memory so we can use this from Swift
uint8_t * const RAM = Apple2_64K_RAM; // Pointer to the Main Memory so we can use this from Swift
uint8_t * const MEM = Apple2_64K_MEM; // Pointer to the Shadow Memory Map so we can use this from Swift
uint8_t * const RDLOMEM = Apple2_64K_MEM; // Pointer to the Shadow Memory Map so we can use this from Swift
uint8_t * const WRLOMEM = Apple2_64K_MEM; // Pointer to the Shadow Memory Map so we can use this from Swift
uint8_t * const RDHIMEM = Apple2_64K_MEM; // Pointer to the Shadow Memory Map so we can use this from Swift
uint8_t * const WRHIMEM = Apple2_Dummy_RAM; // Pointer to the Shadow Memory Map so we can use this from Swift
//uint8_t * AUX_VID_RAM = Apple2_VID_AUX; // Pointer to Auxiliary Video Memory
uint8_t * const AUX = Apple2_64K_AUX; // Pointer to the auxiliary memory so we can use this from Swift
uint8_t * const RAM = Apple2_64K_RAM; // Pointer to the main memory so we can use this from Swift
#define DEF_RAM_PAGE(mem,pg) \
@ -180,72 +188,6 @@ uint8_t * const RAM = Apple2_64K_RAM; // Pointer to the main memory
NULL, \
NULL
uint8_t * RAM_PG_RD_TBL[256] = {
// 48K main memory
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x00),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x10),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x20),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x30),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x40),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x50),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x60),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x70),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x80),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x90),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xA0),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xB0),
// I/O Addresses
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xC0),
// Reading from the ROM
DEF_RAM_PAGE16( Apple2_12K_ROM, 0x00), // D0
DEF_RAM_PAGE16( Apple2_12K_ROM, 0x10), // E0
DEF_RAM_PAGE16( Apple2_12K_ROM, 0x20) // F0
};
uint8_t * RAM_PG_WR_TBL[256] = {
// 48K main memory
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x00),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x10),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x20),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x30),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x40),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x50),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x60),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x70),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x80),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0x90),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xA0),
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xB0),
// I/O Addresses
// DEF_RAM_DUMMY16,
DEF_RAM_PAGE16( Apple2_64K_RAM, 0xC0),
// DEF_RAM_PAGE(Apple2_64K_RAM, 0xC0),
// // SLOT ROM is non-writeable
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 01
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 02
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 03
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 04
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 05
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 06
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 07
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 08
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 09
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0A
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0B
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0C
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0D
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0E
// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0F
// NO Writing to the ROM
DEF_RAM_DUMMY16,
DEF_RAM_DUMMY16,
DEF_RAM_DUMMY16,
};
enum slot {
SLOT0 = 0x00,
@ -354,46 +296,8 @@ enum mmio {
void resetMemory() {
// 48K main memory
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x00, Apple2_64K_RAM, 0x00)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x10, Apple2_64K_RAM, 0x10)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x20, Apple2_64K_RAM, 0x20)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x30, Apple2_64K_RAM, 0x30)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x40, Apple2_64K_RAM, 0x40)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x50, Apple2_64K_RAM, 0x50)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x60, Apple2_64K_RAM, 0x60)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x70, Apple2_64K_RAM, 0x70)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x80, Apple2_64K_RAM, 0x80)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x90, Apple2_64K_RAM, 0x90)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xA0, Apple2_64K_RAM, 0xA0)
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xB0, Apple2_64K_RAM, 0xB0)
// I/O Addresses
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xC0, Apple2_64K_RAM, 0xC0)
// Reading from the ROM
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_12K_ROM, 0x00) // D0
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_12K_ROM, 0x10) // E0
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_12K_ROM, 0x20) // F0
// 48K main memory
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x00, Apple2_64K_RAM, 0x00)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x10, Apple2_64K_RAM, 0x10)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x20, Apple2_64K_RAM, 0x20)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x30, Apple2_64K_RAM, 0x30)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x40, Apple2_64K_RAM, 0x40)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x50, Apple2_64K_RAM, 0x50)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x60, Apple2_64K_RAM, 0x60)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x70, Apple2_64K_RAM, 0x70)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x80, Apple2_64K_RAM, 0x80)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x90, Apple2_64K_RAM, 0x90)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xA0, Apple2_64K_RAM, 0xA0)
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xB0, Apple2_64K_RAM, 0xB0)
// I/O Addresses
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xC0, Apple2_64K_RAM, 0xC0)
// NO Writing to the ROM
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
// Reset memory configuration
MEMcfg.RAM_16K = 0;
MEMcfg.RAM_128K = 1;
MEMcfg.RD_RAM = 0;
@ -404,9 +308,8 @@ void resetMemory() {
MEMcfg.RD_AUX_MEM = 0;
MEMcfg.WR_AUX_MEM = 0;
MEMcfg.int_Cx_ROM = 0;
MEMcfg.slot_C3_ROM = 0;
MEMcfg.ALT_ZP = 0;
MEMcfg.RD_AUX_MEM = 0;
MEMcfg.WR_AUX_MEM = 0;
MEMcfg.txt_page_2 = 0;
@ -414,46 +317,78 @@ void resetMemory() {
memset( Apple2_64K_AUX, 0, sizeof(Apple2_64K_AUX) );
// 64K Main Memory Area
memset( Apple2_64K_RAM, 0, sizeof(Apple2_64K_RAM) );
// 16K Memory Expansion
memset( Apple2_16K_RAM, 0, sizeof(Apple2_16K_RAM) );
memset( Apple2_64K_MEM, 0, sizeof(Apple2_64K_MEM) );
// I/O area should be 0 -- just in case we decide to init RAM with a different pattern...
memset( Apple2_64K_RAM + 0xC000, 0, 0x1000 );
}
static uint8_t page2 = 0;
void textPageSelect() {
uint8_t * shadow = Apple2_64K_MEM + 0x400;
if ( page2 != MEMcfg.txt_page_2 ) {
page2 = MEMcfg.txt_page_2;
if ( MEMcfg.is_80STORE && MEMcfg.txt_page_2 ) {
// save the content of Shadow Memory
memcpy(Apple2_64K_RAM + 0x400, shadow, 0x400);
// load the content of Video Page 2
memcpy(shadow, Apple2_64K_AUX, 0x400);
}
else {
// save the content of Shadow Memory
memcpy(Apple2_64K_AUX + 0x400, shadow, 0x400);
// load the content of Video Page 2
memcpy(shadow, Apple2_64K_RAM, 0x400);
}
}
}
void textPageSelect() {
if ( MEMcfg.is_80STORE && MEMcfg.txt_page_2 ) {
SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_AUX, 0x04)
SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_AUX, 0x04)
}
else {
SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_RAM, 0x04)
SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_RAM, 0x04)
}
}
void auxMemorySelect() {
uint8_t * shadow = Apple2_64K_MEM + 0x200;
uint8_t * memory;
if ( MEMcfg.is_80STORE ) {
if ( MEMcfg.RD_AUX_MEM ) {
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_AUX );
memory = Apple2_64K_AUX + 0x200;
// save the content of Shadow Memory
memcpy(Apple2_64K_RAM + 0x200, shadow, 0xA00);
// load the content of Aux Memory
memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_AUX, 0xA00);
}
else {
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_RAM );
memory = Apple2_64K_RAM + 0x200;
// save the content of Shadow Memory
memcpy(Apple2_64K_AUX + 0x200, shadow, 0xA00);
// load the content of Int Memory
memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_RAM, 0xA00);
}
if ( MEMcfg.WR_AUX_MEM ) {
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_AUX );
// TODO: set write table for AUX
}
else {
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_RAM );
// TODO: set write table for RAM
}
}
else {
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_RAM );
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_RAM );
// TODO: set read table for RAM
}
// load new content to shadow memory
memcpy(shadow, memory, 0xA00);
}
@ -568,7 +503,7 @@ INLINE uint8_t ioRead( uint16_t addr ) {
case io_MEM_RDROM_NOWR_1:
case io_MEM_RDRAM_WRAM_1:
if ( MEMcfg.RAM_16K || MEMcfg.RAM_128K ) {
uint8_t * RAM_BANK = Apple2_16K_RAM;
uint8_t * RAM_BANK = Apple2_64K_AUX + 0xC000;
// RAM Bank 1 or 2?
switch (addr) {
@ -577,12 +512,12 @@ INLINE uint8_t ioRead( uint16_t addr ) {
case io_MEM_RDROM_NOWR_2:
case io_MEM_RDRAM_WRAM_2:
MEMcfg.RAM_BANK_2 = 1;
RAM_BANK = Apple2_16K_RAM + 0x30;
RAM_BANK = Apple2_64K_AUX + 0xD000;
break;
default:
MEMcfg.RAM_BANK_2 = 0;
RAM_BANK = Apple2_16K_RAM;
RAM_BANK = Apple2_64K_AUX + 0xC000;
break;
}
@ -593,18 +528,26 @@ INLINE uint8_t ioRead( uint16_t addr ) {
case io_MEM_RDRAM_NOWR_1:
case io_MEM_RDRAM_WRAM_1:
MEMcfg.RD_RAM = 1;
uint8_t * shadow = Apple2_64K_MEM + 0xD000;
// save the content of Shadow Memory
memcpy(Apple2_64K_RAM + 0xD000, shadow, 0x3000);
// load the content of Aux Memory
memcpy(Apple2_64K_MEM + 0xD000, Apple2_64K_AUX, 0x3000);
// set the RAM extension to read on the upper memory area
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, RAM_BANK, 0x00 );
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_RAM, 0x10 );
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_RAM, 0x20 );
break;
default:
MEMcfg.RD_RAM = 0;
shadow = Apple2_64K_MEM + 0xD000;
// save the content of Shadow Memory
memcpy(Apple2_64K_AUX + 0xD000, shadow, 0x3000);
// load the content of ROM Memory
memcpy(Apple2_64K_MEM + 0xD000, Apple2_16K_ROM + 0x1000, 0x3000);
// set the ROM to read on the upper memory area
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_12K_ROM, 0x00 );
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_12K_ROM, 0x10 );
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_12K_ROM, 0x20 );
break;
}
@ -616,17 +559,11 @@ INLINE uint8_t ioRead( uint16_t addr ) {
case io_MEM_RDRAM_WRAM_1:
MEMcfg.WR_RAM = 1;
// set the RAM extension to read from the upper memory area
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, RAM_BANK, 0x00 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_16K_RAM, 0x10 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_16K_RAM, 0x20 );
break;
default:
MEMcfg.WR_RAM = 0;
// set the ROM to read on the upper memory area
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
break;
}
@ -764,38 +701,36 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
case io_SETSTDZP:
MEMcfg.ALT_ZP = 0;
SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_RAM);
SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_RAM);
// TODO: set zero page table to RAM
break;
case io_SETALTZP:
MEMcfg.ALT_ZP = 1;
SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_AUX);
SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_AUX);
// TODO: set zero page table to AUX
break;
case io_SETSLOTCXROM:
// printf("io_SETSLOTCXROM\n");
MEMcfg.int_Cx_ROM = 0;
SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_64K_RAM, 0xC0);
// TODO: set Cx00 ROM area table to SLOT
break;
case io_SETINTCXROM:
// printf("io_SETINTCXROM\n");
MEMcfg.int_Cx_ROM = 1;
SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
// TODO: set Cx00 ROM area table to INT
break;
case io_SETSLOTC3ROM:
// printf("io_SETSLOTC3ROM\n");
MEMcfg.slot_C3_ROM = 1;
SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_64K_RAM, 0xC3);
// TODO: set C300 ROM area table to SLOT
break;
case io_SETINTC3ROM:
// printf("io_SETINTC3ROM\n");
MEMcfg.slot_C3_ROM = 0;
SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_16K_ROM, 0x03);
// TODO: set C300 ROM area table to INT
break;
case io_VID_CLR80VID:
@ -852,24 +787,51 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
/**
Naive implementation of RAM read from address
**/
INLINE uint8_t memread8_low( uint16_t addr ) {
return RDLOMEM[addr];
}
INLINE uint8_t memread8_high( uint16_t addr ) {
return RDHIMEM[addr];
}
INLINE uint8_t memread8( uint16_t addr ) {
return * ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
// return RAM[addr];
if (addr >= 0xC000) {
return memread8_high(addr);
}
return memread8_low(addr);
}
/**
Naive implementation of RAM read from address
**/
INLINE uint16_t memread16_low( uint16_t addr ) {
return * (uint16_t*) ( RDLOMEM + addr );
}
INLINE uint16_t memread16_high( uint16_t addr ) {
return * (uint16_t*) ( RDHIMEM + addr );
}
INLINE uint16_t memread16( uint16_t addr ) {
return * (uint16_t*) ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
// return * (uint16_t*) (RAM + addr);
if (addr >= 0xC000) {
return memread16_high(addr);
}
return memread16_low(addr);
}
INLINE uint8_t memread( uint16_t addr ) {
if ( (addr >= 0xC000) && (addr <= 0xC0FF) ) {
return ioRead(addr);
if (addr >= 0xC000) {
if (addr < 0xC100) {
return ioRead(addr);
}
// return memread8_paged(addr);
return memread8_high(addr);
}
return memread8(addr);
// return memread8_paged(addr);
return memread8_low(addr);
// return memread8(addr);
}
/**
@ -891,19 +853,27 @@ INLINE uint8_t memread( uint16_t addr ) {
/**
Naive implementation of RAM write to address
**/
static void memwrite( uint16_t addr, uint8_t byte ) {
// if ( addr >= 0xD000 ) {
// // ROM
// return;
// }
// if ( addr >= 0xC000 ) {
// return mmioWrite(addr);
// }
//
RAM[ addr ] = byte;
}
INLINE void memwrite8_low( uint16_t addr, uint8_t data ) {
WRLOMEM[addr] = data;
}
INLINE void memwrite8_high( uint16_t addr, uint8_t data ) {
WRHIMEM[addr] = data;
}
INLINE void memwrite( uint16_t addr, uint8_t data ) {
if (addr >= 0xC000) {
if (addr < 0xC100) {
ioWrite(addr, data);
}
else {
memwrite8_high(addr, data);
}
}
else {
memwrite8_low(addr, data);
}
}
/**
Fetching 1 byte from memory address pc (program counter)
@ -949,8 +919,7 @@ INLINE uint8_t src_abs() {
return memread( addr_abs() );
}
INLINE uint8_t * dest_abs() {
uint16_t addr = addr_abs();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_abs();
}
@ -981,8 +950,7 @@ INLINE uint8_t src_abs_X() {
return memread( addr_abs_X() );
}
INLINE uint8_t * dest_abs_X() {
uint16_t addr = addr_abs_X();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_abs_X();
}
@ -999,8 +967,7 @@ INLINE uint8_t src_abs_Y() {
return memread(addr_abs_Y());
}
INLINE uint8_t * dest_abs_Y() {
uint16_t addr = addr_abs_Y();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_abs_Y();
}
INLINE uint16_t imm() {
@ -1022,8 +989,7 @@ INLINE uint8_t src_zp() {
return memread8(addr_zp());
}
INLINE uint8_t * dest_zp() {
uint16_t addr = addr_zp();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_zp();
}
/**
@ -1051,8 +1017,7 @@ INLINE uint8_t src_X_ind() {
return memread( addr_X_ind() );
}
INLINE uint8_t * dest_X_ind() {
uint16_t addr = addr_X_ind();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_X_ind();
}
/**
@ -1071,8 +1036,7 @@ INLINE uint8_t src_ind_Y() {
return memread( addr_ind_Y() );
}
INLINE uint8_t * dest_ind_Y() {
uint16_t addr = addr_ind_Y();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_ind_Y();
}
/**
@ -1088,8 +1052,7 @@ INLINE uint8_t src_zp_X() {
return memread8(addr_zp_X());
}
INLINE uint8_t * dest_zp_X() {
uint16_t addr = addr_zp_X();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_zp_X();
}
/**
@ -1105,8 +1068,7 @@ INLINE uint8_t src_zp_Y() {
return memread8(addr_zp_Y());
}
INLINE uint8_t * dest_zp_Y() {
uint16_t addr = addr_zp_Y();
return ( RAM_PG_WR_TBL[addr >> 8] + (addr & 0xFF) );
return WRLOMEM + addr_zp_Y();
}

200
ssasa Normal file
View File

@ -0,0 +1,200 @@
DEBUG: 0 no LDA
Line Cycle Disassembly A X Y P S
DEBUG: 0 no LDA
5 44223738 C65E: BD 8C C0 LDA $C08C,X 0xF3 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
6 44223742 C661: 10 FB BPL $C65E 0xF3 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
7 44223744 C663: 49 D5 EOR #$D5 0x26 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
8 44223746 C665: D0 F7 BNE $C65E 0x26 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
15 44223770 C65E: BD 8C C0 LDA $C08C,X 0xCE 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
16 44223774 C661: 10 FB BPL $C65E 0xCE 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
17 44223776 C663: 49 D5 EOR #$D5 0x1B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
18 44223778 C665: D0 F7 BNE $C65E 0x1B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
25 44223802 C65E: BD 8C C0 LDA $C08C,X 0xE5 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
26 44223806 C661: 10 FB BPL $C65E 0xE5 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
27 44223808 C663: 49 D5 EOR #$D5 0x30 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
28 44223810 C665: D0 F7 BNE $C65E 0x30 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
35 44223834 C65E: BD 8C C0 LDA $C08C,X 0xF4 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
36 44223838 C661: 10 FB BPL $C65E 0xF4 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
37 44223840 C663: 49 D5 EOR #$D5 0x21 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
38 44223842 C665: D0 F7 BNE $C65E 0x21 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
45 44223866 C65E: BD 8C C0 LDA $C08C,X 0xCD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
46 44223870 C661: 10 FB BPL $C65E 0xCD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
47 44223872 C663: 49 D5 EOR #$D5 0x18 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
48 44223874 C665: D0 F7 BNE $C65E 0x18 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
55 44223898 C65E: BD 8C C0 LDA $C08C,X 0xBE 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
56 44223902 C661: 10 FB BPL $C65E 0xBE 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
57 44223904 C663: 49 D5 EOR #$D5 0x6B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
58 44223906 C665: D0 F7 BNE $C65E 0x6B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
65 44223930 C65E: BD 8C C0 LDA $C08C,X 0xFF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
66 44223934 C661: 10 FB BPL $C65E 0xFF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
67 44223936 C663: 49 D5 EOR #$D5 0x2A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
68 44223938 C665: D0 F7 BNE $C65E 0x2A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
75 44223962 C65E: BD 8C C0 LDA $C08C,X 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
76 44223966 C661: 10 FB BPL $C65E 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
77 44223968 C663: 49 D5 EOR #$D5 0x32 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
78 44223970 C665: D0 F7 BNE $C65E 0x32 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
85 44223994 C65E: BD 8C C0 LDA $C08C,X 0xCD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
86 44223998 C661: 10 FB BPL $C65E 0xCD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
87 44224000 C663: 49 D5 EOR #$D5 0x18 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
88 44224002 C665: D0 F7 BNE $C65E 0x18 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
95 44224026 C65E: BD 8C C0 LDA $C08C,X 0xBA 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
96 44224030 C661: 10 FB BPL $C65E 0xBA 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
97 44224032 C663: 49 D5 EOR #$D5 0x6F 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
98 44224034 C665: D0 F7 BNE $C65E 0x6F 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
105 44224058 C65E: BD 8C C0 LDA $C08C,X 0xB2 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
106 44224062 C661: 10 FB BPL $C65E 0xB2 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
107 44224064 C663: 49 D5 EOR #$D5 0x67 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
108 44224066 C665: D0 F7 BNE $C65E 0x67 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
115 44224090 C65E: BD 8C C0 LDA $C08C,X 0xA7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
116 44224094 C661: 10 FB BPL $C65E 0xA7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
117 44224096 C663: 49 D5 EOR #$D5 0x72 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
118 44224098 C665: D0 F7 BNE $C65E 0x72 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
125 44224122 C65E: BD 8C C0 LDA $C08C,X 0xFC 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
126 44224126 C661: 10 FB BPL $C65E 0xFC 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
127 44224128 C663: 49 D5 EOR #$D5 0x29 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
128 44224130 C665: D0 F7 BNE $C65E 0x29 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
135 44224154 C65E: BD 8C C0 LDA $C08C,X 0xF2 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
136 44224158 C661: 10 FB BPL $C65E 0xF2 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
137 44224160 C663: 49 D5 EOR #$D5 0x27 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
138 44224162 C665: D0 F7 BNE $C65E 0x27 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
145 44224186 C65E: BD 8C C0 LDA $C08C,X 0xE9 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
146 44224190 C661: 10 FB BPL $C65E 0xE9 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
147 44224192 C663: 49 D5 EOR #$D5 0x3C 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
148 44224194 C665: D0 F7 BNE $C65E 0x3C 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
155 44224218 C65E: BD 8C C0 LDA $C08C,X 0xFF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
156 44224222 C661: 10 FB BPL $C65E 0xFF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
157 44224224 C663: 49 D5 EOR #$D5 0x2A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
158 44224226 C665: D0 F7 BNE $C65E 0x2A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
165 44224250 C65E: BD 8C C0 LDA $C08C,X 0xCF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
166 44224254 C661: 10 FB BPL $C65E 0xCF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
167 44224256 C663: 49 D5 EOR #$D5 0x1A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
168 44224258 C665: D0 F7 BNE $C65E 0x1A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
175 44224282 C65E: BD 8C C0 LDA $C08C,X 0xA7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
176 44224286 C661: 10 FB BPL $C65E 0xA7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
177 44224288 C663: 49 D5 EOR #$D5 0x72 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
178 44224290 C665: D0 F7 BNE $C65E 0x72 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
185 44224314 C65E: BD 8C C0 LDA $C08C,X 0xDF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
186 44224318 C661: 10 FB BPL $C65E 0xDF 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
187 44224320 C663: 49 D5 EOR #$D5 0x0A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
188 44224322 C665: D0 F7 BNE $C65E 0x0A 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
195 44224346 C65E: BD 8C C0 LDA $C08C,X 0x9E 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
196 44224350 C661: 10 FB BPL $C65E 0x9E 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
197 44224352 C663: 49 D5 EOR #$D5 0x4B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
198 44224354 C665: D0 F7 BNE $C65E 0x4B 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
205 44224378 C65E: BD 8C C0 LDA $C08C,X 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
206 44224382 C661: 10 FB BPL $C65E 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
207 44224384 C663: 49 D5 EOR #$D5 0x32 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
208 44224386 C665: D0 F7 BNE $C65E 0x32 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
215 44224410 C65E: BD 8C C0 LDA $C08C,X 0x9B 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
216 44224414 C661: 10 FB BPL $C65E 0x9B 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
217 44224416 C663: 49 D5 EOR #$D5 0x4E 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
218 44224418 C665: D0 F7 BNE $C65E 0x4E 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
225 44224442 C65E: BD 8C C0 LDA $C08C,X 0xBA 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
226 44224446 C661: 10 FB BPL $C65E 0xBA 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
227 44224448 C663: 49 D5 EOR #$D5 0x6F 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
228 44224450 C665: D0 F7 BNE $C65E 0x6F 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
235 44224474 C65E: BD 8C C0 LDA $C08C,X 0xFD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
236 44224478 C661: 10 FB BPL $C65E 0xFD 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
237 44224480 C663: 49 D5 EOR #$D5 0x28 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
238 44224482 C665: D0 F7 BNE $C65E 0x28 0x60 0x00 0x34 0xFE
DEBUG: 0 no LDA
245 44224506 C65E: BD 8C C0 LDA $C08C,X 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
246 44224510 C661: 10 FB BPL $C65E 0xE7 0x60 0x00 0xB4 0xFE
DEBUG: 0 no LDA
247 44224512 C663: 49 D5 EOR #$D5 0x32 0x60 0x00 0x34 0xFE