Apple-2-Tools
/
Steve2
mirror of https://github.com/trudnai/Steve2.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

BugFix: ZeroPage Memory

This commit is contained in:
Tamas Rudnai 2024-01-09 20:24:58 -08:00
parent 176d0afa2a
commit 711b68608d
6 changed files with 118 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/6502_C.h
View File

@ -92,15 +92,15 @@ case 0x7C: JMP( addr_ind_ind_X()); return 6; // abs_addr_X() ); return 6;
case 0xFA: PLX(); return 4; // PLX
// STZ - STore Zero
case 0x64: STZ( addr_zp() ); return 3; // STZ zpg
case 0x74: STZ( addr_zp_X() ); return 4; // STZ zpg,X
case 0x64: STZ_zp( addr_zp() ); return 3; // STZ zpg
case 0x74: STZ_zp( addr_zp_X() ); return 4; // STZ zpg,X
case 0x9C: STZ( addr_abs() ); return 4; // STZ abs
case 0x9E: STZ( addr_abs_X() ); return 5; // STZ abs,X
// TRB - Test and Reset Bits
case 0x04: TSB( addr_zp() ); return 5; // TSB zpg
case 0x04: TSB_zp( addr_zp() ); return 5; // TSB zpg
case 0x0C: TSB( addr_abs() ); return 6; // TSB abs
case 0x14: TRB( addr_zp() ); return 5; // TRB zpg
case 0x14: TRB_zp( addr_zp() ); return 5; // TRB zpg
case 0x1C: TRB( addr_abs() ); return 6; // TRB abs

16
src/cpu/6502_std.h
View File

@ -36,7 +36,7 @@
case 0x01: ORA( src_X_ind() ); return 6; // ORA X,ind
case 0x05: ORA( src_zp() ); return 3; // ORA zpg
case 0x06: ASL( addr_zp() ); return 5; // ASL zpg
case 0x06: ASL_zp( addr_zp() ); return 5; // ASL zpg
case 0x08: PHP(); return 3; // PHP
case 0x09: ORA( imm() ); return 2; // ORA imm
@ -49,7 +49,7 @@
case 0x11: ORA( src_ind_Y() ); return 5; // ORA ind,Y
case 0x15: ORA( src_zp_X() ); return 4; // ORA zpg,X
case 0x16: ASL( addr_zp_X() ); return 6; // ASL zpg,X
case 0x16: ASL_zp( addr_zp_X() ); return 6; // ASL zpg,X
case 0x18: CLC(); return 2; // CLC
case 0x19: ORA( src_abs_Y() ); return 4+1; // ORA abs,Y
@ -62,7 +62,7 @@
case 0x24: BIT( src_zp() ); return 3; // BIT zpg
case 0x25: AND( src_zp() ); return 3; // AND zpg
case 0x26: ROL( addr_zp() ); return 5; // ROL zpg
case 0x26: ROL_zp( addr_zp() ); return 5; // ROL zpg
case 0x28: PLP(); return 4; // PLP
case 0x29: AND( imm() ); return 2; // AND imm
@ -76,7 +76,7 @@
case 0x31: AND( src_ind_Y() ); return 5; // AND ind,Y
case 0x35: AND( src_zp_X() ); return 4; // AND zpg,X
case 0x36: ROL( addr_zp_X() ); return 6; // ROL zpg,X
case 0x36: ROL_zp( addr_zp_X() ); return 6; // ROL zpg,X
case 0x38: SEC(); return 2; // SEC
case 0x39: AND( src_abs_Y() ); return 4+1; // AND abs,Y
@ -88,7 +88,7 @@
case 0x41: EOR( src_X_ind() ); return 6; // EOR X,ind
case 0x45: EOR( src_zp() ); return 3; // EOR zpg
case 0x46: LSR( addr_zp() ); return 5; // LSR zpg
case 0x46: LSR_zp( addr_zp() ); return 5; // LSR zpg
case 0x48: PHA(); return 3; // PHA
case 0x49: EOR( imm() ); return 2; // EOR imm
@ -102,7 +102,7 @@
case 0x51: EOR( src_ind_Y() ); return 5; // EOR ind,Y
case 0x55: EOR( src_zp_X() ); return 4; // AND zpg,X
case 0x56: LSR( addr_zp_X() ); return 6; // LSR zpg,X
case 0x56: LSR_zp( addr_zp_X() ); return 6; // LSR zpg,X
case 0x58: CLI(); return 2; // CLI
case 0x59: EOR( src_abs_Y() ); return 4+1; // EOR abs,Y
@ -114,7 +114,7 @@
case 0x61: ADC( src_X_ind() ); return 6; // ADC X,ind
case 0x65: ADC( src_zp() ); return 3; // ADC zpg
case 0x66: ROR( addr_zp() ); return 5; // ROR zpg
case 0x66: ROR_zp( addr_zp() ); return 5; // ROR zpg
case 0x68: PLA(); return 4; // PLA
case 0x69: ADC( imm() ); return 2; // ADC imm
@ -128,7 +128,7 @@
case 0x71: ADC( src_ind_Y() ); return 5; // ADC ind,Y
case 0x75: ADC( src_zp_X() ); return 4; // ADC zpg,X
case 0x76: ROR( addr_zp_X() ); return 6; // ROR zpg,X
case 0x76: ROR_zp( addr_zp_X() ); return 6; // ROR zpg,X
case 0x78: SEI(); return 2; // SEI
case 0x79: ADC( src_abs_Y() ); return 4+1; // ADC abs,Y

37
src/cpu/instructions/6502_instr_shift_rotate.h
View File

@ -86,6 +86,15 @@ INSTR void LSR( uint16_t addr ) {
set_flags_NZ( WRLOMEM[addr] >>= 1 );
#endif
}
INSTR void LSR_zp( uint16_t addr ) {
dbgPrintf("LSR ");
disPrintf(disassembly.inst, "LSR");
#ifndef DISASSEMBLER
m6502.C = WRZEROPG[addr] & 1;
set_flags_NZ( WRZEROPG[addr] >>= 1 );
#endif
}
INSTR void LSRA() {
dbgPrintf("LSR ");
disPrintf(disassembly.inst, "LSR");
@ -117,6 +126,12 @@ INSTR void _ROL( uint16_t addr ) {
WRLOMEM[addr] <<= 1;
set_flags_NZ( WRLOMEM[addr] |= C );
}
INSTR void _ROL_zp( uint16_t addr ) {
uint8_t C = m6502.C != 0;
m6502.C = WRZEROPG[addr] & 0x80;
WRZEROPG[addr] <<= 1;
set_flags_NZ( WRZEROPG[addr] |= C );
}
#endif
INSTR void ROL( uint16_t addr ) {
dbgPrintf("ROL ");
@ -126,6 +141,14 @@ INSTR void ROL( uint16_t addr ) {
_ROL(addr);
#endif
}
INSTR void ROL_zp( uint16_t addr ) {
dbgPrintf("ROL ");
disPrintf(disassembly.inst, "ROL");
#ifndef DISASSEMBLER
_ROL_zp(addr);
#endif
}
INSTR void ROLA() {
dbgPrintf("ROL ");
disPrintf(disassembly.inst, "ROL");
@ -159,6 +182,12 @@ INSTR void _ROR( uint16_t addr ) {
WRLOMEM[addr] >>= 1;
set_flags_NZ( WRLOMEM[addr] |= C << 7 );
}
INSTR void _ROR_zp( uint16_t addr ) {
uint8_t C = m6502.C != 0;
m6502.C = WRZEROPG[addr] & 1;
WRZEROPG[addr] >>= 1;
set_flags_NZ( WRZEROPG[addr] |= C << 7 );
}
#endif
INSTR void ROR( uint16_t addr ) {
dbgPrintf("ROR ");
@ -168,6 +197,14 @@ INSTR void ROR( uint16_t addr ) {
_ROR(addr);
#endif
}
INSTR void ROR_zp( uint16_t addr ) {
dbgPrintf("ROR ");
disPrintf(disassembly.inst, "ROR");
#ifndef DISASSEMBLER
_ROR_zp(addr);
#endif
}
INSTR void RORA() {
dbgPrintf("ROR ");
disPrintf(disassembly.inst, "ROR");

18
src/cpu/jit/instructions/6502_instr_compare_test.h
View File

@ -88,6 +88,15 @@ INSTR void TRB( uint16_t addr ) {
WRLOMEM[addr] &= ~m6502.A;
#endif
}
INSTR void TRB_zp( uint16_t addr ) {
dbgPrintf("TRB(%02X) ", src);
disPrintf(disassembly.inst, "TRB");
#ifndef DISASSEMBLER
set_flags_Z( WRZEROPG[addr] & m6502.A );
WRZEROPG[addr] &= ~m6502.A;
#endif
}
/**
TSB - Test and Set Bits
@ -118,6 +127,15 @@ INSTR void TSB( uint16_t addr ) {
WRLOMEM[addr] |= m6502.A;
#endif
}
INSTR void TSB_zp( uint16_t addr ) {
dbgPrintf("TSB(%02X) ", src);
disPrintf(disassembly.inst, "TSB");
#ifndef DISASSEMBLER
set_flags_Z( WRZEROPG[addr] & m6502.A );
WRZEROPG[addr] |= m6502.A;
#endif
}
/**
CMP Compare Memory with Accumulator

4
src/cpu/jit/instructions/6502_instr_set_clr.h
View File

@ -193,7 +193,7 @@ INSTR void SEI(void) {
#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
dbgPrintf("RMB"#n" "); \
disPrintf(disassembly.inst, "RMB"#n); \
WRLOMEM[zpg] &= ~(1 << n); \
WRZEROPG[zpg] &= ~(1 << n); \
}
#else
#define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
@ -216,7 +216,7 @@ INSTR void SEI(void) {
#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
dbgPrintf("SMB"#n" "); \
disPrintf(disassembly.inst, "SMB"#n); \
WRLOMEM[zpg] |= (1 << n); \
WRZEROPG[zpg] |= (1 << n); \
}
#else
#define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \

49
src/cpu/jit/instructions/6502_instr_shift_rotate.h
View File

@ -44,6 +44,10 @@ INSTR void _ASL( uint16_t addr ) {
m6502.C = _memread(addr) & 0x80;
set_flags_NZ( WRLOMEM[addr] <<= 1 );
}
INSTR void _ASL_zp( uint16_t addr ) {
m6502.C = _memread(addr) & 0x80;
set_flags_NZ( WRZEROPG[addr] <<= 1 );
}
#endif
INSTR void ASL( uint16_t addr ) {
dbgPrintf("ASL ");
@ -53,6 +57,14 @@ INSTR void ASL( uint16_t addr ) {
_ASL(addr);
#endif
}
INSTR void ASL_zp( uint16_t addr ) {
dbgPrintf("ASL ");
disPrintf(disassembly.inst, "ASL");
#ifndef DISASSEMBLER
_ASL_zp(addr);
#endif
}
INSTR void ASLA(void) {
dbgPrintf("ASL ");
disPrintf(disassembly.inst, "ASL");
@ -86,6 +98,15 @@ INSTR void LSR( uint16_t addr ) {
set_flags_NZ( WRLOMEM[addr] >>= 1 );
#endif
}
INSTR void LSR_zp( uint16_t addr ) {
dbgPrintf("LSR ");
disPrintf(disassembly.inst, "LSR");
#ifndef DISASSEMBLER
m6502.C = WRZEROPG[addr] & 1;
set_flags_NZ( WRZEROPG[addr] >>= 1 );
#endif
}
INSTR void LSRA(void) {
dbgPrintf("LSR ");
disPrintf(disassembly.inst, "LSR");
@ -117,6 +138,12 @@ INSTR void _ROL( uint16_t addr ) {
WRLOMEM[addr] <<= 1;
set_flags_NZ( WRLOMEM[addr] |= C );
}
INSTR void _ROL_zp( uint16_t addr ) {
uint8_t C = m6502.C != 0;
m6502.C = WRZEROPG[addr] & 0x80;
WRZEROPG[addr] <<= 1;
set_flags_NZ( WRZEROPG[addr] |= C );
}
#endif
INSTR void ROL( uint16_t addr ) {
dbgPrintf("ROL ");
@ -126,6 +153,14 @@ INSTR void ROL( uint16_t addr ) {
_ROL(addr);
#endif
}
INSTR void ROL_zp( uint16_t addr ) {
dbgPrintf("ROL ");
disPrintf(disassembly.inst, "ROL");
#ifndef DISASSEMBLER
_ROL_zp(addr);
#endif
}
INSTR void ROLA(void) {
dbgPrintf("ROL ");
disPrintf(disassembly.inst, "ROL");
@ -159,6 +194,12 @@ INSTR void _ROR( uint16_t addr ) {
WRLOMEM[addr] >>= 1;
set_flags_NZ( WRLOMEM[addr] |= C << 7 );
}
INSTR void _ROR_zp( uint16_t addr ) {
uint8_t C = m6502.C != 0;
m6502.C = WRZEROPG[addr] & 1;
WRZEROPG[addr] >>= 1;
set_flags_NZ( WRZEROPG[addr] |= C << 7 );
}
#endif
INSTR void ROR( uint16_t addr ) {
dbgPrintf("ROR ");
@ -168,6 +209,14 @@ INSTR void ROR( uint16_t addr ) {
_ROR(addr);
#endif
}
INSTR void ROR_zp( uint16_t addr ) {
dbgPrintf("ROR ");
disPrintf(disassembly.inst, "ROR");
#ifndef DISASSEMBLER
_ROR_zp(addr);
#endif
}
INSTR void RORA(void) {
dbgPrintf("ROR ");
disPrintf(disassembly.inst, "ROR");