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Code Issues Projects Releases Wiki Activity

Refactoring instruction handler in switch

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Fixed some issues
This commit is contained in:
Tamas Rudnai 2019-09-11 00:11:45 -07:00
parent 5ad28e911e
commit 8a6f1654ee
11 changed files with 7785 additions and 157 deletions
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7
A2Mac.xcodeproj/project.pbxproj
View File

@ -56,6 +56,8 @@
32439F8422ECD8AD0077AAE0 /* apple.rom */ = {isa = PBXFileReference; lastKnownFileType = file; path = apple.rom; sourceTree = "<group>"; };
32439F8522ECD8AD0077AAE0 /* 6502.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = 6502.h; sourceTree = "<group>"; };
32439F8622ECD8AD0077AAE0 /* common.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = common.h; sourceTree = "<group>"; };
3264261023284F6F008B615F /* Apple2_mmio_8bit_ioaddr.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = Apple2_mmio_8bit_ioaddr.h; sourceTree = "<group>"; };
326426112328ADF4008B615F /* Apple_II_ROM.s */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.asm; path = Apple_II_ROM.s; sourceTree = "<group>"; };
32BFFB5722EACC630003B53F /* A2Mac.app */ = {isa = PBXFileReference; explicitFileType = wrapper.application; includeInIndex = 0; path = A2Mac.app; sourceTree = BUILT_PRODUCTS_DIR; };
32BFFB5A22EACC630003B53F /* AppDelegate.swift */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.swift; path = AppDelegate.swift; sourceTree = "<group>"; };
32BFFB5C22EACC630003B53F /* ViewController.swift */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.swift; path = ViewController.swift; sourceTree = "<group>"; };
@ -121,6 +123,7 @@
32BFFB4E22EACC630003B53F = {
isa = PBXGroup;
children = (
326426112328ADF4008B615F /* Apple_II_ROM.s */,
32BFFB5922EACC630003B53F /* A2Mac */,
32BFFB6C22EACC660003B53F /* A2MacTests */,
32BFFB7722EACC660003B53F /* A2MacUITests */,
@ -146,6 +149,7 @@
32439F8522ECD8AD0077AAE0 /* 6502.h */,
32439F8422ECD8AD0077AAE0 /* apple.rom */,
32439F7322ECD8AD0077AAE0 /* Apple2_mmio.h */,
3264261023284F6F008B615F /* Apple2_mmio_8bit_ioaddr.h */,
32439F8622ECD8AD0077AAE0 /* common.h */,
32BFFB5A22EACC630003B53F /* AppDelegate.swift */,
32BFFB5C22EACC630003B53F /* ViewController.swift */,
@ -483,6 +487,7 @@
CODE_SIGN_STYLE = Automatic;
COMBINE_HIDPI_IMAGES = YES;
DEVELOPMENT_TEAM = W6TFQTZ4DA;
GCC_FAST_MATH = YES;
INFOPLIST_FILE = A2Mac/Info.plist;
LD_RUNPATH_SEARCH_PATHS = (
"$(inherited)",
@ -505,6 +510,8 @@
CODE_SIGN_STYLE = Automatic;
COMBINE_HIDPI_IMAGES = YES;
DEVELOPMENT_TEAM = W6TFQTZ4DA;
GCC_FAST_MATH = YES;
GCC_OPTIMIZATION_LEVEL = fast;
INFOPLIST_FILE = A2Mac/Info.plist;
LD_RUNPATH_SEARCH_PATHS = (
"$(inherited)",

5
A2Mac.xcodeproj/xcuserdata/trudnai.xcuserdatad/xcschemes/xcschememanagement.plist
View File

@ -9,6 +9,11 @@
<key>orderHint</key>
<integer>0</integer>
</dict>
<key>Debug.xcscheme</key>
<dict>
<key>orderHint</key>
<integer>1</integer>
</dict>
</dict>
<key>SuppressBuildableAutocreation</key>
<dict>

240
A2Mac/6502.c
View File

@ -45,31 +45,31 @@ static inline int m6502_step() {
//
switch ( fetch() ) {
case 0x00: BRK(); return 2; // BRK
case 0x01: ORA( memread( addr_X_ind() ) ); return 6; // ORA X,ind
case 0x01: ORA( src_X_ind() ); return 6; // ORA X,ind
// case 0x02: // t jams
// case 0x03: // SLO* (undocumented)
// case 0x04: // NOP* (undocumented)
case 0x05: ORA( memread_zp( fetch() ) ); return 3; // ORA zpg
case 0x06: ASL( & RAM[ fetch() ] ); return 5; // ASL zpg
case 0x05: ORA( src_zp() ); return 3; // ORA zpg
case 0x06: ASL( dest_zp() ); return 5; // ASL zpg
// case 0x07: // SLO* (undocumented)
case 0x08: PHP(); return 3; // PHP
case 0x09: ORA( fetch() ); return 2; // ORA imm
case 0x0A: ASL( & m6502.A ); return 2; // ASL A
case 0x09: ORA( imm() ); return 2; // ORA imm
case 0x0A: ASLA(); return 2; // ASL A
// case 0x0B: // ANC** (undocumented)
// case 0x0C: // NOP* (undocumented)
case 0x0D: ORA( memread( fetch16() ) ); return 4; // ORA abs
case 0x0E: ASL( & RAM[ fetch16() ] ); return 6; // ASL abs
case 0x0D: ORA( src_abs() ); return 4; // ORA abs
case 0x0E: ASL( dest_abs() ); return 6; // ASL abs
// case 0x0F: // SLO* (undocumented)
case 0x10: BPL( (int8_t)fetch() ); return 2; // BPL rel
case 0x11: ORA( memread( addr_ind_Y() ) ); return 5; // ORA ind,Y
case 0x10: BPL( rel_addr() ); return 2; // BPL rel
case 0x11: ORA( src_ind_Y() ); return 5; // ORA ind,Y
// case 0x12: // t jams
// case 0x13: // SLO* (undocumented)
// case 0x14: // NOP* (undocumented)
case 0x15: ORA( memread_zp( fetch() + m6502.X ) ); return 4; // ORA zpg,X
case 0x16: ASL( & RAM[ fetch() + m6502.X ] ); return 6; // ASL zpg,X
case 0x15: ORA( src_zp_X() ); return 4; // ORA zpg,X
case 0x16: ASL( dest_zp_X() ); return 6; // ASL zpg,X
// case 0x17: // SLO* (undocumented)
case 0x18: CLC(); return 2; // CLC
case 0x19: ORA( memread( fetch16() + m6502.Y ) ); return 4; // ORA abs,Y
case 0x19: ORA( src_abs_Y() ); return 4; // ORA abs,Y
// case 0x1A: // NOP* (undocumented)
// case 0x1B: // SLO* (undocumented)
// case 0x1C: // NOP* (undocumented)
@ -82,223 +82,223 @@ static inline int m6502_step() {
// case 0x23:
case 0x24: BIT( src_zp() ); return 3; // BIT zpg
case 0x25: AND( src_zp() ); return 3; // AND zpg
case 0x26: ROL( & RAM[ fetch() ] ); return 5; // ROL zpg
case 0x26: ROL( dest_zp() ); return 5; // ROL zpg
// case 0x27:
case 0x28: PLP(); return 4; // PLP
case 0x29: AND( fetch() ); return 2; // AND imm
case 0x2A: ROL( & m6502.A ); return 2; // ROL A
case 0x29: AND( imm() ); return 2; // AND imm
case 0x2A: ROLA(); return 2; // ROL A
// case 0x2B:
case 0x2C: BIT( memread( fetch16() ) ); return 4; // BIT abs
case 0x2D: AND( memread( fetch16() ) ); return 4; // AND abs
case 0x2E: ROL( & RAM[ fetch16() ] ); return 6; // ROL abs
case 0x2C: BIT( src_abs() ); return 4; // BIT abs
case 0x2D: AND( src_abs() ); return 4; // AND abs
case 0x2E: ROL( dest_abs() ); return 6; // ROL abs
// case 0x2F:
case 0x30: BMI( (int8_t)fetch() ); return 2; // BMI rel
case 0x31: AND( memread( addr_ind_Y() ) ); return 5; // AND ind,Y
case 0x30: BMI( rel_addr() ); return 2; // BMI rel
case 0x31: AND( src_ind_Y() ); return 5; // AND ind,Y
// case 0x32:
// case 0x33:
// case 0x34:
case 0x35: AND( memread_zp( addr_zp_X() ) ); return 4; // AND zpg,X
case 0x36: ROL( & RAM[ addr_zp_X() ] ); return 6; // ROL zpg,X
case 0x35: AND( src_zp_X() ); return 4; // AND zpg,X
case 0x36: ROL( dest_zp_X() ); return 6; // ROL zpg,X
// case 0x37:
case 0x38: SEC(); return 2; // SEC
case 0x39: AND( memread( addr_abs_Y() ) ); return 4; // AND abs,Y
case 0x39: AND( src_abs_Y() ); return 4; // AND abs,Y
// case 0x3A:
// case 0x3B:
// case 0x3C:
case 0x3D: AND( memread( addr_abs_X() ) ); return 4; // AND abs,X
case 0x3E: ROL( & RAM[ addr_abs_X() ] ); return 7; // ROL abs,X
case 0x3D: AND( src_abs_X() ); return 4; // AND abs,X
case 0x3E: ROL( dest_abs_X() ); return 7; // ROL abs,X
// case 0x3F:
case 0x40: RTI(); return 6; // RTI
case 0x41: EOR( memread( addr_X_ind() ) ); return 6; // EOR X,ind
case 0x41: EOR( src_X_ind() ); return 6; // EOR X,ind
// case 0x42:
// case 0x43:
// case 0x44:
case 0x45: EOR( memread_zp( fetch() ) ); return 3; // EOR zpg
case 0x46: LSR( & RAM[ fetch() ] ); return 5; // LSR zpg
case 0x45: EOR( src_zp() ); return 3; // EOR zpg
case 0x46: LSR( dest_zp() ); return 5; // LSR zpg
// case 0x47:
case 0x48: PHA(); return 3; // PHA
case 0x49: EOR( fetch() ); return 2; // EOR imm
case 0x4A: LSR( & m6502.A ); return 2; // LSR A
case 0x49: EOR( imm() ); return 2; // EOR imm
case 0x4A: LSRA(); return 2; // LSR A
// case 0x4B:
case 0x4C: JMP( fetch16() ); return 3; // JMP abs
case 0x4D: EOR( memread( fetch16() ) ); return 4; // EOR abs
case 0x4E: LSR( & RAM[ fetch16() ] ); return 6; // LSR abs
case 0x4C: JMP( abs_addr() ); return 3; // JMP abs
case 0x4D: EOR( src_abs() ); return 4; // EOR abs
case 0x4E: LSR( dest_abs() ); return 6; // LSR abs
// case 0x4F:
case 0x50: BVC( (int8_t)fetch() ); return 2; // BVC rel
case 0x51: EOR( memread( addr_ind_Y() ) ); return 5; // EOR ind,Y
case 0x50: BVC( rel_addr() ); return 2; // BVC rel
case 0x51: EOR( src_ind_Y() ); return 5; // EOR ind,Y
// case 0x52:
// case 0x53:
// case 0x54:
case 0x55: EOR( memread_zp( addr_zp_X() ) ); return 4; // AND zpg,X
case 0x56: LSR( & RAM[ addr_zp_X() ] ); return 6; // LSR zpg,X
case 0x55: EOR( src_zp_X() ); return 4; // AND zpg,X
case 0x56: LSR( dest_zp_X() ); return 6; // LSR zpg,X
// case 0x57:
case 0x58: CLI(); return 2; // CLI
case 0x59: EOR( memread( addr_abs_Y() ) ); return 4; // EOR abs,Y
case 0x59: EOR( src_abs_Y() ); return 4; // EOR abs,Y
// case 0x5A:
// case 0x5B:
// case 0x5C:
case 0x5D: EOR( memread( addr_abs_X() ) ); return 4; // EOR abs,X
case 0x5E: LSR( & RAM[ addr_abs_X() ] ); return 7; // LSR abs,X
case 0x5D: EOR( src_abs_X() ); return 4; // EOR abs,X
case 0x5E: LSR( dest_abs_X() ); return 7; // LSR abs,X
// case 0x5F:
case 0x60: RTS(); return 6; // RTS
case 0x61: ADC( memread( addr_X_ind() ) ); return 6; // ADC X,ind
case 0x61: ADC( src_X_ind() ); return 6; // ADC X,ind
// case 0x62:
// case 0x63:
// case 0x64:
case 0x65: ADC( memread_zp( fetch() ) ); return 3; // ADC zpg
case 0x66: ROR( & RAM[ fetch() ] ); return 5; // ROR zpg
case 0x65: ADC( src_zp() ); return 3; // ADC zpg
case 0x66: ROR( dest_zp() ); return 5; // ROR zpg
// case 0x67:
case 0x68: PLA(); break; // PLA
case 0x69: ADC( fetch() ); return 2; // ADC imm
case 0x6A: ROR( & m6502.A ); return 2; // ROR A
case 0x69: ADC( imm() ); return 2; // ADC imm
case 0x6A: RORA(); return 2; // ROR A
// case 0x6B:
case 0x6C: JMP( memread16( fetch16() ) ); return 5; // JMP ind
case 0x6D: ADC( memread( fetch16() ) ); return 4; // ADC abs
case 0x6E: ROR( & RAM[ fetch16() ] ); return 6; // ROR abs
case 0x6C: JMP( ind_addr() ); return 5; // JMP ind
case 0x6D: ADC( src_abs() ); return 4; // ADC abs
case 0x6E: ROR( dest_abs() ); return 6; // ROR abs
// case 0x6F:
case 0x70: BVS( (int8_t)fetch() ); break; // BVS rel
case 0x71: ADC( memread( addr_ind_Y() ) ); return 5; // ADC ind,Y
case 0x70: BVS( rel_addr() ); break; // BVS rel
case 0x71: ADC( src_ind_Y() ); return 5; // ADC ind,Y
// case 0x72:
// case 0x73:
// case 0x74:
case 0x75: ADC( memread_zp( addr_zp_X() ) ); return 4; // ADC zpg,X
case 0x76: ROR( & RAM[ addr_zp_X() ] ); return 6; // ROR zpg,X
case 0x75: ADC( src_zp_X() ); return 4; // ADC zpg,X
case 0x76: ROR( dest_zp_X() ); return 6; // ROR zpg,X
// case 0x77:
case 0x78: SEI(); break; // SEI
case 0x79: ADC( memread( addr_abs_Y() ) ); return 4; // ADC abs,Y
case 0x79: ADC( src_abs_Y() ); return 4; // ADC abs,Y
// case 0x7A:
// case 0x7B:
// case 0x7C:
case 0x7D: ADC( memread( addr_abs_X() ) ); return 4; // ADC abs,X
case 0x7E: ROR( & RAM[ addr_abs_X() ] ); return 7; // ROR abs,X
case 0x7D: ADC( src_abs_X() ); return 4; // ADC abs,X
case 0x7E: ROR( dest_abs_X() ); return 7; // ROR abs,X
// case 0x7F:
// case 0x80:
case 0x81: STA( & RAM[ addr_X_ind() ] ) ; return 6; // STA X,ind
case 0x81: STA( dest_X_ind() ) ; return 6; // STA X,ind
// case 0x82:
// case 0x83:
case 0x84: STY( & RAM[ fetch() ] ); return 3; // STY zpg
case 0x85: STA( & RAM[ fetch() ] ); return 3; // STA zpg
case 0x86: STX( & RAM[ fetch() ] ); return 3; // STX zpg
case 0x84: STY( dest_zp() ); return 3; // STY zpg
case 0x85: STA( dest_zp() ); return 3; // STA zpg
case 0x86: STX( dest_zp() ); return 3; // STX zpg
// case 0x87:
case 0x88: DEY(); return 2; // DEY
// case 0x89:
case 0x8A: TXA(); return 2; // TXA
// case 0x8B:
case 0x8C: STY( & RAM[ fetch16() ] ); return 4; // STY abs
case 0x8D: STA( & RAM[ fetch16() ] ); return 4; // STA abs
case 0x8E: STX( & RAM[ fetch16() ] ); return 4; // STX abs
case 0x8C: STY( dest_abs() ); return 4; // STY abs
case 0x8D: STA( dest_abs() ); return 4; // STA abs
case 0x8E: STX( dest_abs() ); return 4; // STX abs
// case 0x8F:
case 0x90: BCC( (int8_t)fetch() ); return 2; // BCC rel
case 0x91: STA( & RAM[ addr_ind_Y() ] ); return 6; // STA ind,Y
case 0x90: BCC( rel_addr() ); return 2; // BCC rel
case 0x91: STA( dest_ind_Y() ); return 6; // STA ind,Y
// case 0x92:
// case 0x93:
case 0x94: STY( & RAM[ addr_zp_X() ] ); return 4; // STY zpg,X
case 0x95: STA( & RAM[ addr_zp_X() ] ); return 4; // STA zpg,X
case 0x96: STX( & RAM[ addr_zp_Y() ] ); return 4; // STX zpg,Y
case 0x94: STY( dest_zp_X() ); return 4; // STY zpg,X
case 0x95: STA( dest_zp_X() ); return 4; // STA zpg,X
case 0x96: STX( dest_zp_X() ); return 4; // STX zpg,Y
// case 0x97:
case 0x98: TYA(); return 2; // TYA
case 0x99: STA( & RAM[ addr_abs_Y() ] ); return 5; // STA abs,Y
case 0x99: STA( dest_abs_Y() ); return 5; // STA abs,Y
case 0x9A: TXS(); return 2; // TXS
// case 0x9B:
// case 0x9C:
case 0x9D: STA( & RAM[ addr_abs_X() ] ); return 5; // STA abs,X
case 0x9D: STA( dest_abs_X() ); return 5; // STA abs,X
// case 0x9E:
// case 0x9F:
case 0xA0: LDY( fetch() ); return 2; // LDY imm
case 0xA1: LDA( memread( addr_X_ind() ) ) ; return 6; // LDA X,ind
case 0xA2: LDX( fetch() ); return 2; // LDX imm
case 0xA0: LDY( imm() ); return 2; // LDY imm
case 0xA1: LDA( src_X_ind() ) ; return 6; // LDA X,ind
case 0xA2: LDX( imm() ); return 2; // LDX imm
// case 0xA3:
case 0xA4: LDY( memread_zp( fetch() ) ); return 3; // LDY zpg
case 0xA5: LDA( memread_zp( fetch() ) ); return 3; // LDA zpg
case 0xA6: LDX( memread_zp( fetch() ) ); return 3; // LDX zpg
case 0xA4: LDY( src_zp() ); return 3; // LDY zpg
case 0xA5: LDA( src_zp() ); return 3; // LDA zpg
case 0xA6: LDX( src_zp() ); return 3; // LDX zpg
// case 0xA7:
case 0xA8: TAY(); return 2; // TAY
case 0xA9: LDA( fetch() ); return 2; // LDA imm
case 0xA9: LDA( imm() ); return 2; // LDA imm
case 0xAA: TAX(); return 2; // TAX
// case 0xAB:
case 0xAC: LDY( memread( fetch16() ) ); return 4; // LDY abs
case 0xAD: LDA( memread( fetch16() ) ); return 4; // LDA abs
case 0xAE: LDX( memread( fetch16() ) ); return 4; // LDX abs
case 0xAC: LDY( src_abs() ); return 4; // LDY abs
case 0xAD: LDA( src_abs() ); return 4; // LDA abs
case 0xAE: LDX( src_abs() ); return 4; // LDX abs
// case 0xAF:
case 0xB0: BCS( (int8_t)fetch() ); return 2; // BCS rel
case 0xB1: LDA( memread( addr_ind_Y() ) ); return 5; // LDA ind,Y
case 0xB0: BCS( rel_addr() ); return 2; // BCS rel
case 0xB1: LDA( src_ind_Y() ); return 5; // LDA ind,Y
// case 0xB2:
// case 0xB3:
case 0xB4: LDY( memread_zp( addr_zp_X() ) ); return 4; // LDY zpg,X
case 0xB5: LDA( memread_zp( addr_zp_X() ) ); return 4; // LDA zpg,X
case 0xB6: LDX( memread_zp( addr_zp_Y() ) ); return 4; // LDX zpg,Y
case 0xB4: LDY( src_zp_X() ); return 4; // LDY zpg,X
case 0xB5: LDA( src_zp_X() ); return 4; // LDA zpg,X
case 0xB6: LDX( src_zp_Y() ); return 4; // LDX zpg,Y
// case 0xB7:
case 0xB8: CLV(); return 2; // CLV
case 0xB9: LDA( memread( addr_abs_Y() ) ); return 4; // LDA abs,Y
case 0xB9: LDA( src_abs_Y() ); return 4; // LDA abs,Y
case 0xBA: TSX(); return 2; // TSX
// case 0xBB:
case 0xBC: LDY( memread( addr_abs_X() ) ); return 4; // LDY abs,X
case 0xBD: LDA( memread( addr_abs_X() ) ); return 4; // LDA abs,X
case 0xBE: LDX( memread( addr_abs_Y() ) ); return 4; // LDX abs,Y
case 0xBC: LDY( src_abs_X() ); return 4; // LDY abs,X
case 0xBD: LDA( src_abs_X() ); return 4; // LDA abs,X
case 0xBE: LDX( src_abs_Y() ); return 4; // LDX abs,Y
// case 0xBF:
case 0xC0: CPY( fetch() ); break; // CPY imm
case 0xC1: CMP( memread( addr_X_ind() ) ) ; break; // LDA X,ind
case 0xC0: CPY( imm() ); break; // CPY imm
case 0xC1: CMP( src_X_ind() ) ; break; // LDA X,ind
// case 0xC2:
// case 0xC3:
case 0xC4: CPY( memread_zp( fetch() ) ); return 3; // CPY zpg
case 0xC5: CMP( memread_zp( fetch() ) ); return 3; // CMP zpg
case 0xC6: DEC( & RAM[ fetch() ] ); return 5; // DEC zpg
case 0xC4: CPY( src_zp() ); return 3; // CPY zpg
case 0xC5: CMP( src_zp() ); return 3; // CMP zpg
case 0xC6: DEC( dest_zp() ); return 5; // DEC zpg
// case 0xC7:
case 0xC8: INY(); return 2; // INY
case 0xC9: CMP( fetch() ); return 2; // CMP imm
case 0xC9: CMP( imm() ); return 2; // CMP imm
case 0xCA: DEX(); return 2; // DEX
// case 0xCB:
case 0xCC: CPY( memread( fetch16() ) ); return 4; // CPY abs
case 0xCD: CMP( memread( fetch16() ) ); return 4; // CMP abs
case 0xCE: DEC( & RAM[ fetch16() ] ); return 4; // DEC abs
case 0xCC: CPY( src_abs() ); return 4; // CPY abs
case 0xCD: CMP( src_abs() ); return 4; // CMP abs
case 0xCE: DEC( dest_abs() ); return 4; // DEC abs
// case 0xCF:
case 0xD0: BNE( (int8_t)fetch() ); return 2; // BNE rel
case 0xD1: CMP( memread( addr_ind_Y() ) ); return 5; // CMP ind,Y
case 0xD0: BNE( rel_addr() ); return 2; // BNE rel
case 0xD1: CMP( src_ind_Y() ); return 5; // CMP ind,Y
// case 0xD2:
// case 0xD3:
// case 0xD4:
case 0xD5: CMP( memread_zp( addr_zp_X() ) ); return 4; // CMP zpg,X
case 0xD6: DEC( & RAM[ addr_zp_X() ] ); return 6; // DEC zpg,X
case 0xD5: CMP( src_zp_X() ); return 4; // CMP zpg,X
case 0xD6: DEC( dest_zp_X() ); return 6; // DEC zpg,X
// case 0xD7:
case 0xD8: CLD(); return 2; // CLD
case 0xD9: CMP( memread( addr_abs_Y() ) ); return 4; // CMP abs,Y
case 0xD9: CMP( src_abs_Y() ); return 4; // CMP abs,Y
// case 0xDA:
// case 0xDB:
// case 0xDC:
case 0xDD: CMP( memread( addr_abs_X() ) ); return 4; // CMP abs,X
case 0xDE: DEC( & RAM[ addr_abs_X() ] ); return 7; // DEC abs,X
case 0xDD: CMP( src_abs_X() ); return 4; // CMP abs,X
case 0xDE: DEC( dest_abs_X() ); return 7; // DEC abs,X
// case 0xDF:
case 0xE0: CPX( fetch() ); return 2; // CPX imm
case 0xE1: SBC( memread( addr_X_ind() ) ) ; return 6; // SBC (X,ind)
case 0xE0: CPX( imm() ); return 2; // CPX imm
case 0xE1: SBC( src_X_ind() ) ; return 6; // SBC (X,ind)
// case 0xE2:
// case 0xE3:
case 0xE4: CPX( memread_zp( fetch() ) ); return 3; // CPX zpg
case 0xE5: SBC( memread_zp( fetch() ) ); return 3; // SBC zpg
case 0xE6: INC( & RAM[ fetch() ] ); return 5; // INC zpg
case 0xE4: CPX( src_zp() ); return 3; // CPX zpg
case 0xE5: SBC( src_zp() ); return 3; // SBC zpg
case 0xE6: INC( dest_zp() ); return 5; // INC zpg
// case 0xE7:
case 0xE8: INX(); return 2; // INX
case 0xE9: SBC( fetch() ); return 2; // SBC imm
case 0xE9: SBC( imm() ); return 2; // SBC imm
case 0xEA: NOP(); return 2; // NOP
// case 0xEB:
case 0xEC: CPX( memread( fetch16() ) ); return 4; // CPX abs
case 0xED: SBC( fetch16() ); return 4; // SBC abs
case 0xEE: INC( & RAM[ fetch16() ] ); return 6; // INC abs
case 0xEC: CPX( src_abs() ); return 4; // CPX abs
case 0xED: SBC( src_abs() ); return 4; // SBC abs
case 0xEE: INC( dest_abs() ); return 6; // INC abs
// case 0xEF:
case 0xF0: BEQ( (int8_t)fetch() ); return 2; // BEQ rel
case 0xF1: SBC( memread( addr_ind_Y() ) ); return 5; // SBC ind,Y
case 0xF0: BEQ( rel_addr() ); return 2; // BEQ rel
case 0xF1: SBC( src_ind_Y() ); return 5; // SBC ind,Y
// case 0xF2:
// case 0xF3:
// case 0xF4:
case 0xF5: SBC( memread_zp( addr_zp_X() ) ); return 4; // SBC zpg,X
case 0xF6: INC( & RAM[ addr_zp_X() ] ); return 6; // INC zpg,X
case 0xF5: SBC( src_zp_X() ); return 4; // SBC zpg,X
case 0xF6: INC( dest_zp_X() ); return 6; // INC zpg,X
// case 0xF7:
case 0xF8: SED(); break; // SED
case 0xF9: SBC( memread( addr_abs_Y() ) ); return 4; // SBC abs,Y
case 0xF9: SBC( src_abs_Y() ); return 4; // SBC abs,Y
// case 0xFA:
// case 0xFB:
// case 0xFC:
case 0xFD: SBC( memread( addr_abs_X() ) ); return 4; // SBC abs,X
case 0xFE: INC( & RAM[ addr_abs_X() ] ); return 6; // INC abs,X
case 0xFD: SBC( src_abs_X() ); return 4; // SBC abs,X
case 0xFE: INC( dest_abs_X() ); return 6; // INC abs,X
// case 0xFF:
default:

62
A2Mac/Apple2_mmio.h
View File

@ -75,9 +75,11 @@ static inline uint8_t ioRead( uint16_t addr ) {
// printf("mmio:%04X\n", addr);
switch (addr) {
case io_KBD:
return RAM[addr];
return RAM[io_KBD];
case io_KBDSTRB:
// TODO: This is very slow!
dbgPrintf("io_KBDSTRB\n");
return RAM[io_KBD] &= 0x7F;
default:
@ -230,9 +232,40 @@ static inline uint8_t * dest_X_ind() {
effective address is word in (LL, LL + 1) incremented by Y with carry: C.w($00LL) + Y
**/
static inline uint16_t addr_ind_Y() {
uint8_t a = fetch();
// uint8_t a = fetch();
// dbgPrintf("addr_ind_Y: %04X + %02X = %04X ", addr_zpg_ind( a ), m6502.Y, addr_zpg_ind( a ) + m6502.Y);
return addr_zp_ind( a ) + m6502.Y;
return addr_zp_ind( fetch() ) + m6502.Y;
}
static inline uint8_t src_ind_Y() {
return memread( addr_ind_Y() );
}
static inline uint8_t * dest_ind_Y() {
return & RAM[ addr_ind_Y() ];
}
/**
abs .... absolute OPC $LLHH,X
operand is address; effective address is address incremented by X with carry **
**/
static inline uint16_t addr_abs() {
return fetch16();
}
static inline uint8_t src_abs() {
return memread( addr_abs() );
}
static inline uint8_t * dest_abs() {
return & RAM[ addr_abs() ];
}
static inline int8_t rel_addr() {
return fetch();
}
static inline uint16_t abs_addr() {
return fetch16();
}
static inline uint16_t ind_addr() {
return memread16( fetch16() );
}
/**
@ -250,16 +283,12 @@ static inline uint8_t * dest_abs_X() {
}
static inline uint16_t abs_addr() {
return fetch16();
}
/**
abs,Y .... absolute, Y-indexed OPC $LLHH,Y
operand is address; effective address is address incremented by Y with carry **
**/
static inline uint16_t addr_abs_Y() {
return fetch16() + m6502.Y;
return abs_addr() + m6502.Y;
}
static inline uint8_t src_abs_Y() {
return memread(addr_abs_Y());
@ -268,6 +297,11 @@ static inline uint8_t * dest_abs_Y() {
return & RAM[ addr_abs_Y() ];
}
static inline uint16_t imm() {
return fetch();
}
/**
zpg .... zeropage OPC $LL
operand is zeropage address (hi-byte is zero, address = $00LL)
@ -290,6 +324,12 @@ static inline uint8_t * dest_zp() {
static inline uint16_t addr_zp_X() {
return addr_zp() + m6502.X;
}
static inline uint8_t src_zp_X() {
return memread_zp(addr_zp_X());
}
static inline uint8_t * dest_zp_X() {
return & RAM[ addr_zp_X() ];
}
/**
zpg,Y .... zeropage, Y-indexed OPC $LL,Y
@ -299,6 +339,12 @@ static inline uint16_t addr_zp_X() {
static inline uint16_t addr_zp_Y() {
return addr_zp() + m6502.Y;
}
static inline uint8_t src_zp_Y() {
return memread_zp(addr_zp_Y());
}
static inline uint8_t * dest_zp_Y() {
return & RAM[ addr_zp_Y() ];
}
#endif // __APPLE2_MMIO_H__

581
A2Mac/Apple2_mmio_8bit_ioaddr.h Normal file
View File

@ -0,0 +1,581 @@
//
// main.c
// 6502
//
// Created by Tamas Rudnai on 7/14/19.
// Copyright © 2019 GameAlloy. All rights reserved.
//
#ifndef __APPLE2_MMIO_H__
#define __APPLE2_MMIO_H__
#include "common.h"
#include "6502.h"
enum mmio {
io_KBD = 0xC000,
io_KBDSTRB = 0xC010,
};
uint8_t RAM[ 64 * KB ] = {0};
#define PAGESIZE 256
#define PAGES 16
//uint8_t ram_0[PAGESIZE];
//uint8_t ram_1[PAGESIZE];
//uint8_t ram_2[PAGESIZE];
//uint8_t ram_3[PAGESIZE];
//uint8_t ram_4[PAGESIZE];
//uint8_t ram_5[PAGESIZE];
//uint8_t ram_6[PAGESIZE];
//uint8_t ram_7[PAGESIZE];
//uint8_t ram_8[PAGESIZE];
//uint8_t ram_9[PAGESIZE];
//uint8_t ram_A[PAGESIZE];
//uint8_t ram_B[PAGESIZE];
//uint8_t aui_C[PAGESIZE];
//uint8_t rom_D[PAGESIZE];
//uint8_t rom_E[PAGESIZE];
//uint8_t rom_F[PAGESIZE];
//
//uint8_t * ram[PAGES] = {
// ram_0,
// ram_1,
// ram_2,
// ram_3,
// ram_4,
// ram_5,
// ram_6,
// ram_7,
// ram_8,
// ram_9,
// ram_A,
// ram_B,
// aui_C,
// rom_D,
// rom_E,
// rom_F,
//};
//uint8_t ( * mmio_read [ 64 * KB ] )( uint16_t addr );
typedef union address16_u {
uint16_t addr;
struct {
uint8_t offs;
uint8_t page;
};
} address16_t;
static inline uint8_t ioRead( uint16_t addr ) {
// printf("mmio:%04X\n", addr);
// C0xx
switch ((uint8_t)addr) {
case 0x00:
return RAM[io_KBD];
case 0x10:
// TODO: This is very slow!
dbgPrintf("io_KBDSTRB\n");
return RAM[io_KBD] &= 0x7F;
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
case 0x0D:
case 0x0E:
case 0x0F:
case 0x11:
case 0x12:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x18:
case 0x19:
case 0x1A:
case 0x1B:
case 0x1C:
case 0x1D:
case 0x1E:
case 0x1F:
case 0x20:
case 0x21:
case 0x22:
case 0x23:
case 0x24:
case 0x25:
case 0x26:
case 0x27:
case 0x28:
case 0x29:
case 0x2A:
case 0x2B:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x2F:
case 0x30:
case 0x31:
case 0x32:
case 0x33:
case 0x34:
case 0x35:
case 0x36:
case 0x37:
case 0x38:
case 0x39:
case 0x3A:
case 0x3B:
case 0x3C:
case 0x3D:
case 0x3E:
case 0x3F:
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4A:
case 0x4B:
case 0x4C:
case 0x4D:
case 0x4E:
case 0x4F:
case 0x50:
case 0x51:
case 0x52:
case 0x53:
case 0x54:
case 0x55:
case 0x56:
case 0x57:
case 0x58:
case 0x59:
case 0x5A:
case 0x5B:
case 0x5C:
case 0x5D:
case 0x5E:
case 0x5F:
case 0x60:
case 0x61:
case 0x62:
case 0x63:
case 0x64:
case 0x65:
case 0x66:
case 0x67:
case 0x68:
case 0x69:
case 0x6A:
case 0x6B:
case 0x6C:
case 0x6D:
case 0x6E:
case 0x6F:
case 0x70:
case 0x71:
case 0x72:
case 0x73:
case 0x74:
case 0x75:
case 0x76:
case 0x77:
case 0x78:
case 0x79:
case 0x7A:
case 0x7B:
case 0x7C:
case 0x7D:
case 0x7E:
case 0x7F:
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8A:
case 0x8B:
case 0x8C:
case 0x8D:
case 0x8E:
case 0x8F:
case 0x90:
case 0x91:
case 0x92:
case 0x93:
case 0x94:
case 0x95:
case 0x96:
case 0x97:
case 0x98:
case 0x99:
case 0x9A:
case 0x9B:
case 0x9C:
case 0x9D:
case 0x9E:
case 0x9F:
case 0xA0:
case 0xA1:
case 0xA2:
case 0xA3:
case 0xA4:
case 0xA5:
case 0xA6:
case 0xA7:
case 0xA8:
case 0xA9:
case 0xAA:
case 0xAB:
case 0xAC:
case 0xAD:
case 0xAE:
case 0xAF:
case 0xB0:
case 0xB1:
case 0xB2:
case 0xB3:
case 0xB4:
case 0xB5:
case 0xB6:
case 0xB7:
case 0xB8:
case 0xB9:
case 0xBA:
case 0xBB:
case 0xBC:
case 0xBD:
case 0xBE:
case 0xBF:
case 0xC0:
case 0xC1:
case 0xC2:
case 0xC3:
case 0xC4:
case 0xC5:
case 0xC6:
case 0xC7:
case 0xC8:
case 0xC9:
case 0xCA:
case 0xCB:
case 0xCC:
case 0xCD:
case 0xCE:
case 0xCF:
case 0xD0:
case 0xD1:
case 0xD2:
case 0xD3:
case 0xD4:
case 0xD5:
case 0xD6:
case 0xD7:
case 0xD8:
case 0xD9:
case 0xDA:
case 0xDB:
case 0xDC:
case 0xDD:
case 0xDE:
case 0xDF:
case 0xE0:
case 0xE1:
case 0xE2:
case 0xE3:
case 0xE4:
case 0xE5:
case 0xE6:
case 0xE7:
case 0xE8:
case 0xE9:
case 0xEA:
case 0xEB:
case 0xEC:
case 0xED:
case 0xEE:
case 0xEF:
case 0xF0:
case 0xF1:
case 0xF2:
case 0xF3:
case 0xF4:
case 0xF5:
case 0xF6:
case 0xF7:
case 0xF8:
case 0xF9:
case 0xFA:
case 0xFB:
case 0xFC:
case 0xFD:
case 0xFE:
case 0xFF:
default:
break;
}
return 0;
}
static inline void ioWrite( uint16_t addr ) {
// printf("mmio:%04X\n", addr);
switch (addr) {
case io_KBD:
return;
default:
break;
}
return;
}
/**
Naive implementation of RAM read from address
**/
static inline uint8_t memread_zp( uint8_t addr ) {
return RAM[ addr ];
}
static inline uint8_t memread( uint16_t addr ) {
// switch ( ((address16_t)addr).page ) {
// case 0xC0:
// case 0xC1:
// case 0xC2:
// case 0xC3:
// case 0xC4:
// case 0xC5:
// case 0xC6:
// case 0xC7:
// case 0xC8:
// case 0xC9:
// case 0xCA:
// case 0xCB:
// case 0xCC:
// case 0xCD:
// case 0xCE:
// case 0xCF:
// return ioRead(addr);
//
// defaut:
// break;
// }
if ( (addr >= 0xC000) && (addr < 0xD000) ) {
ioRead(addr);
}
return RAM[ addr ];
}
/**
Naive implementation of RAM read from address
**/
static inline uint16_t memread16( uint16_t addr ) {
// if ( ( addr >= 0xC000 ) && ( addr < 0xD000 ) ) {
// return mmioRead(addr);
// }
// dbgPrintf("%04X ", * (uint16_t*) (& RAM[ addr ]));
return * (uint16_t*) (& RAM[ addr ]);
}
/**
Naive implementation of RAM read from address
**/
//static inline uint16_t memioread16( uint16_t addr ) {
// return (uint16_t)mmio_read[ addr ](addr);
//}
/**
Naive implementation of RAM write to address
**/
static void memwrite_zp( uint8_t addr, uint8_t byte ) {
RAM[ addr ] = byte;
}
/**
Naive implementation of RAM write to address
**/
static void memwrite( uint16_t addr, uint8_t byte ) {
// if ( addr >= 0xD000 ) {
// // ROM
// return;
// }
// if ( addr >= 0xC000 ) {
// return mmioWrite(addr);
// }
//
RAM[ addr ] = byte;
}
/**
Fetching 1 byte from memory address pc (program counter)
increase pc by one
**/
static inline uint8_t fetch() {
dbgPrintf("%02X ", RAM[m6502.pc]);
return memread( m6502.pc++ );
}
/**
Fetching 2 bytes as a 16 bit number from memory address pc (program counter)
increase pc by one
**/
static inline uint16_t fetch16() {
dbgPrintf("%04X ", memread16(m6502.pc));
uint16_t word = memread16( m6502.pc );
m6502.pc += 2;
return word;
}
/**
get a 16 bit address from the zp:zp+1
**/
static inline uint16_t addr_zp_ind( uint8_t addr ) {
return memread16(addr);
}
/**
X,ind .... X-indexed, indirect OPC ($LL,X)
operand is zeropage address;
effective address is word in (LL + X, LL + X + 1), inc. without carry: C.w($00LL + X)
**/
static inline uint16_t addr_X_ind() {
return addr_zp_ind( fetch() + m6502.X );
}
static inline uint8_t src_X_ind() {
return memread( addr_X_ind() );
}
static inline uint8_t * dest_X_ind() {
return & RAM[ addr_X_ind() ];
}
/**
ind,Y .... indirect, Y-indexed OPC ($LL),Y
operand is zeropage address;
effective address is word in (LL, LL + 1) incremented by Y with carry: C.w($00LL) + Y
**/
static inline uint16_t addr_ind_Y() {
uint8_t a = fetch();
// dbgPrintf("addr_ind_Y: %04X + %02X = %04X ", addr_zpg_ind( a ), m6502.Y, addr_zpg_ind( a ) + m6502.Y);
return addr_zp_ind( a ) + m6502.Y;
}
/**
abs,X .... absolute, X-indexed OPC $LLHH,X
operand is address; effective address is address incremented by X with carry **
**/
static inline uint16_t addr_abs_X() {
return fetch16() + m6502.X;
}
static inline uint8_t src_abs_X() {
return memread( addr_abs_X() );
}
static inline uint8_t * dest_abs_X() {
return & RAM[ addr_abs_X() ];
}
static inline uint16_t abs_addr() {
return fetch16();
}
/**
abs,Y .... absolute, Y-indexed OPC $LLHH,Y
operand is address; effective address is address incremented by Y with carry **
**/
static inline uint16_t addr_abs_Y() {
return fetch16() + m6502.Y;
}
static inline uint8_t src_abs_Y() {
return memread(addr_abs_Y());
}
static inline uint8_t * dest_abs_Y() {
return & RAM[ addr_abs_Y() ];
}
/**
zpg .... zeropage OPC $LL
operand is zeropage address (hi-byte is zero, address = $00LL)
**/
static inline uint16_t addr_zp() {
return fetch();
}
static inline uint8_t src_zp() {
return memread_zp(addr_zp());
}
static inline uint8_t * dest_zp() {
return & RAM[ addr_zp() ];
}
/**
zpg,X .... zeropage, X-indexed OPC $LL,X
operand is zeropage address;
effective address is address incremented by X without carry **
**/
static inline uint16_t addr_zp_X() {
return addr_zp() + m6502.X;
}
/**
zpg,Y .... zeropage, Y-indexed OPC $LL,Y
operand is zeropage address;
effective address is address incremented by Y without carry **
**/
static inline uint16_t addr_zp_Y() {
return addr_zp() + m6502.Y;
}
#endif // __APPLE2_MMIO_H__

49
A2Mac/instructions/6502_instr_branch.h
View File

@ -11,6 +11,7 @@
static inline void BRA( int8_t reladdr ) {
m6502.pc += reladdr;
dbgPrintf("BRA %04X ", m6502.pc);
}
/**
@ -25,8 +26,12 @@ static inline void BRA( int8_t reladdr ) {
**/
static inline void BCC( int8_t reladdr ) {
dbgPrintf("BCC ");
if ( m6502.flags.C == 0 )
if ( m6502.flags.C == 0 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -41,8 +46,12 @@ static inline void BCC( int8_t reladdr ) {
**/
static inline void BCS( int8_t reladdr ) {
dbgPrintf("BCS ");
if ( m6502.flags.C == 1 )
if ( m6502.flags.C == 1 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -57,8 +66,12 @@ static inline void BCS( int8_t reladdr ) {
**/
static inline void BNE( int8_t reladdr ) {
dbgPrintf("BNE ");
if ( m6502.flags.Z == 0 )
if ( m6502.flags.Z == 0 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -73,8 +86,12 @@ static inline void BNE( int8_t reladdr ) {
**/
static inline void BEQ( int8_t reladdr ) {
dbgPrintf("BEQ ");
if ( m6502.flags.Z == 1 )
if ( m6502.flags.Z == 1 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -89,8 +106,12 @@ static inline void BEQ( int8_t reladdr ) {
**/
static inline void BPL( int8_t reladdr ) {
dbgPrintf("BPL ");
if ( m6502.flags.N == 0 )
if ( m6502.flags.N == 0 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -105,8 +126,12 @@ static inline void BPL( int8_t reladdr ) {
**/
static inline void BMI( int8_t reladdr ) {
dbgPrintf("BMI ");
if ( m6502.flags.N == 1 )
if ( m6502.flags.N == 1 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -121,8 +146,12 @@ static inline void BMI( int8_t reladdr ) {
**/
static inline void BVC( int8_t reladdr ) {
dbgPrintf("BVC ");
if ( m6502.flags.V == 0 )
if ( m6502.flags.V == 0 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
/**
@ -137,8 +166,12 @@ static inline void BVC( int8_t reladdr ) {
**/
static inline void BVS( int8_t reladdr ) {
dbgPrintf("BVS ");
if ( m6502.flags.V == 1 )
if ( m6502.flags.V == 1 ) {
BRA( reladdr );
}
else {
dbgPrintf("-no-");
}
}
#endif // __6502_INSTR_BRANCH_H__

2
A2Mac/instructions/6502_instr_call_ret_jump.h
View File

@ -22,7 +22,7 @@
indirect JMP (oper) 6C 3 5
**/
static inline void JMP( uint16_t addr ) {
dbgPrintf("JMP ");
dbgPrintf("JMP %04X ", addr);
m6502.pc = addr;
}

7
A2Mac/instructions/6502_instr_compare_test.h
View File

@ -26,10 +26,9 @@
**/
static inline void BIT( uint8_t imm ) {
dbgPrintf("BIT(%02X) ", imm);
uint8_t m = m6502.A & imm;
m6502.flags.N = BITTEST(m, 7);
m6502.flags.V = BITTEST(m, 6);
m6502.flags.Z = m == 0;
m6502.flags.N = BITTEST(imm, 7);
m6502.flags.V = BITTEST(imm, 6);
m6502.flags.Z = (imm & m6502.A) == 0;
}
/**

31
A2Mac/instructions/6502_instr_load_store.h
View File

@ -30,7 +30,7 @@
(indirect),Y LDA (oper),Y B1 2 5*
**/
static inline void LDA( uint8_t imm ) {
dbgPrintf("LDA ");
dbgPrintf("LDA(%02X) ", imm);
m6502.A = imm;
set_flags_NZ(imm);
}
@ -50,7 +50,7 @@ static inline void LDA( uint8_t imm ) {
absolute,Y LDX oper,Y BE 3 4*
**/
static inline void LDX( uint8_t imm ) {
dbgPrintf("LDX ");
dbgPrintf("LDX(%02X) ", imm);
m6502.X = imm;
set_flags_NZ(imm);
}
@ -95,14 +95,29 @@ static inline void STR( uint8_t * dst, uint8_t imm ) {
// uint16_t v = dst - RAM;
// if ( ( v >= 0x400 ) && ( v < 0x800 ) ) {
// char c = charConv[imm];
// if ( c == '?' ) {
// printf("? SYNTAX ERROR\n");
// }
//// if ( c == '?' ) {
//// printf("? SYNTAX ERROR\n");
//// }
//
// if (( imm > ' ' ) && ( c < 0x7F ))
// printf("%04X: t:%02X '%c'\n", v, imm, isprint(c) ? c : ' ');
// printf("*** PRINT: %04X: t:%02X '%c'\n", v, imm, isprint(c) ? c : ' ');
// }
//
//
// else switch ( v ) {
// case 0x36:
// case 0x37:
// dbgPrintf("*** OUTROUT %04X: %02X\n", v, imm);
// break;
//
// case 0x9B:
// case 0x9C:
// dbgPrintf("*** LOWTR %04X: %02X\n", v, imm);
// break;
//
// default:
// break;
// }
}
/**

44
A2Mac/instructions/6502_instr_shift_rotate.h
View File

@ -27,8 +27,14 @@
static inline void ASL( uint8_t * dst ) {
dbgPrintf("ASL ");
m6502.flags.C = *dst >> 7;
*dst <<= 1;
set_flags_NZ( *dst );
;
set_flags_NZ( *dst <<= 1 );
}
static inline void ASLA() {
dbgPrintf("ASL ");
m6502.flags.C = m6502.A >> 7;
;
set_flags_NZ( m6502.A <<= 1 );
}
/**
@ -48,8 +54,14 @@ static inline void ASL( uint8_t * dst ) {
static inline void LSR( uint8_t * dst ) {
dbgPrintf("LSR ");
m6502.flags.C = *dst & 1;
*dst >>= 1;
set_flags_NZ( *dst );
;
set_flags_NZ( *dst >>= 1 );
}
static inline void LSRA() {
dbgPrintf("LSR ");
m6502.flags.C = m6502.A & 1;
;
set_flags_NZ( m6502.A >>= 1 );
}
/**
@ -71,8 +83,16 @@ static inline void ROL( uint8_t * dst ) {