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Undocumented Instruction Implementations
This commit is contained in:
tudnai
parent
6b43345ca2
commit
c7b202c9d0
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@ -25,13 +25,10 @@
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#define __6502_INSTR_BRANCH_H__
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INLINE void BRA( int8_t reladdr ) {
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m6502.PC += reladdr;
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#ifdef CLK_ABSOLUTE_PRECISE
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uint8_t pg = m6502.PC >> 8;
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m6502.clktime += m6502.PC >> 8 == pg ? 1 : 2;
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#else
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// m6502.clktime++;
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#endif
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m6502.PC += reladdr;
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m6502.clkfrm += m6502.PC >> 8 == pg ? 1 : 2;
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#ifdef DEBUG
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if ( reladdr == -2 ) {
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dbgPrintf2("Infinite Loop at %04X!\n", m6502.PC);
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@ -208,4 +205,79 @@ INLINE void BVS( int8_t reladdr ) {
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}
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}
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/**
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BBR BBS - Branch on Bit Reset or Set
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BBR and BBS test the specified zero page location and branch if the specified bit is clear (BBR) or set (BBS).
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Note that as with TRB, the term reset in BBR is used to mean clear.
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On the 6502 and 65C02, bit 7 is typically the most convenient bit to use for I/O and software flags because
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it can be tested by several instructions, such as BIT and LDA. BBR and BBS can test any of the 8 bits without
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affecting any flags or using any registers. Unlike other branch instructions, BBR and BBS always take the same
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number of cycles (five) whether the branch is taken or not. It is often useful to test bit 0, for example, to test
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whether a byte is even or odd. However, the usefulness of BBR and BBS is somewhat limited for a couple of reasons.
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First, there is only a single addressing mode for these instructions -- no indexing by X or Y, for instance.
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Second, they are restricted to zero page locations. For software flags this may be just fine, but it may not be very
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convenient (or cost effective) to add any additional address decoding hardware that may be necessary to
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map I/O locations to the zero page.
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The addressing mode is a combination of zero page addressing and relative addressing -- really just a juxtaposition of the two.
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The bit to test is typically specified as part of the instruction name rather than the operand, i.e.
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Flags affected: none
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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0F 3 5 zp,rel ........ BBR0 $12,LABEL
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1F 3 5 zp,rel ........ BBR1 $12,LABEL
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2F 3 5 zp,rel ........ BBR2 $12,LABEL
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3F 3 5 zp,rel ........ BBR3 $12,LABEL
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4F 3 5 zp,rel ........ BBR4 $12,LABEL
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5F 3 5 zp,rel ........ BBR5 $12,LABEL
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6F 3 5 zp,rel ........ BBR6 $12,LABEL
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7F 3 5 zp,rel ........ BBR7 $12,LABEL
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8F 3 5 zp,rel ........ BBS0 $12,LABEL
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9F 3 5 zp,rel ........ BBS1 $12,LABEL
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AF 3 5 zp,rel ........ BBS2 $12,LABEL
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BF 3 5 zp,rel ........ BBS3 $12,LABEL
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CF 3 5 zp,rel ........ BBS4 $12,LABEL
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DF 3 5 zp,rel ........ BBS5 $12,LABEL
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EF 3 5 zp,rel ........ BBS6 $12,LABEL
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FF 3 5 zp,rel ........ BBS7 $12,LABEL
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**/
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#define BBR(n) INLINE void BBR##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBR"#n" "); \
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disPrintf(disassembly.inst, "BBR"#n); \
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if ( ! (src & (1 << n) ) ) { \
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BRA( reladdr ); \
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} \
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}
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BBR(0)
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BBR(1)
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BBR(2)
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BBR(3)
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BBR(4)
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BBR(5)
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BBR(6)
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BBR(7)
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#define BBS(n) INLINE void BBS##n( uint8_t src, int8_t reladdr ) { \
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dbgPrintf("BBS"#n" "); \
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disPrintf(disassembly.inst, "BBS"#n); \
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if ( (src & (1 << n) ) ) { \
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BRA( reladdr ); \
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} \
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}
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BBS(0)
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BBS(1)
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BBS(2)
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BBS(3)
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BBS(4)
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BBS(5)
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BBS(6)
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BBS(7)
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#endif // __6502_INSTR_BRANCH_H__
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@ -45,6 +45,9 @@ INLINE void JMP( uint16_t addr ) {
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dbgPrintf("Infinite Loop at %04X!\n", m6502.PC);
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}
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#endif
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if (m6502.PC >> 8 != addr >> 8) {
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m6502.clkfrm += 1;
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}
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m6502.PC = addr;
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}
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@ -46,6 +46,62 @@ INLINE void BIT( uint8_t src ) {
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set_flags_Z(m6502.A & src);
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}
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/**
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TRB - Test and Reset Bits
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TRB can be one the more confusing instructions for a couple of reasons.
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First, the term reset is used to refer to the clearing of a bit, whereas the term clear had been used consistently before, such as CLC
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which stands for CLear Carry. Second, the effect on the Z flag is determined by a different function than the effect on memory.
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TRB has the same effect on the Z flag that a BIT instruction does. Specifically, it is based on whether the result of a bitwise AND of the
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accumulator with the contents of the memory location specified in the operand is zero. Also, like BIT, the accumulator is not affected.
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The accumulator determines which bits in the memory location specified in the operand are cleared and which are not affected.
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The bits in the accumulator that are ones are cleared (in memory), and the bits that are zeros (in the accumulator) are not affected (in memory).
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This is the same as saying that the resulting memory contents are the bitwise AND of the memory contents with the complement of the
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accumulator (i.e. the exclusive-or of the accululator with $FF).
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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14 2 5 zp ......Z. TRB $12
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1C 3 6 abs ......Z. TRB $3456
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**/
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INLINE void TRB( uint16_t addr ) {
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dbgPrintf("TRB(%02X) ", src);
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disPrintf(disassembly.inst, "TRB");
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set_flags_Z( WRLOMEM[addr] & m6502.A );
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WRLOMEM[addr] &= ~m6502.A;
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}
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/**
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TSB - Test and Set Bits
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TSB, like TRB, can be confusing. For one, like TRB, the effect on the Z flag is determined by a different function than the effect on memory.
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TSB, like TRB, has the same effect on the Z flag that a BIT instruction does. Specifically, it is based on whether the result of a bitwise AND
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of the accumulator with the contents of the memory location specified in the operand is zero. Also, like BIT (and TRB), the accumulator is not affected.
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The accumulator determines which bits in the memory location specified in the operand are set and which are not affected. The bits in the
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accumulator that are ones are set to one (in memory), and the bits that are zeros (in the accumulator) are not affected (in memory).
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This is the same as saying that the resulting memory contents are the bitwise OR of the memory contents with the accumulator.
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Flags affected: Z
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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04 2 5 zp ......Z. TSB $12
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0C 3 6 abs ......Z. TSB $3456
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**/
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INLINE void TSB( uint16_t addr ) {
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dbgPrintf("TSB(%02X) ", src);
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disPrintf(disassembly.inst, "TSB");
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set_flags_Z( WRLOMEM[addr] & m6502.A );
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WRLOMEM[addr] |= m6502.A;
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}
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/**
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CMP Compare Memory with Accumulator
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@ -80,6 +80,23 @@ INLINE void INY() {
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dbgPrintf("%02X ", m6502.Y);
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}
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/**
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INA Increment Accumulator by One
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A + 1 -> A N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied INA C8 1 2
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**/
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INLINE void INA() {
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dbgPrintf("INA %02X -> ", m6502.A);
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disPrintf(disassembly.inst, "INA");
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set_flags_NZ( ++m6502.A );
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dbgPrintf("%02X ", m6502.A);
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}
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/**
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DEC Decrement Memory by One
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@ -135,5 +152,22 @@ INLINE void DEY() {
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dbgPrintf("%02X ", m6502.Y);
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}
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/**
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DEA Decrement Accumulator by One
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A - 1 -> A N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied DEC 88 1 2
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**/
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INLINE void DEA() {
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dbgPrintf("DEA %02X -> ", m6502.A);
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disPrintf(disassembly.inst, "DEA");
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set_flags_NZ( --m6502.A );
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dbgPrintf("%02X ", m6502.A);
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}
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#endif // __6502_INSTR_INC_DEC_H__
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@ -168,5 +168,24 @@ INLINE void STY( uint16_t addr ) {
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STR(addr, m6502.Y);
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}
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/**
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STZ Store Zero (0) in Memory
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0 -> M N Z C I D V
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- - - - - -
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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64 2 3 zp ........ STZ $12
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74 2 4 zp,X ........ STZ $12,X
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9C 3 4 abs ........ STZ $3456
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9E 3 5 abs,X ........ STZ $3456,X
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**/
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INLINE void STZ( uint16_t addr ) {
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dbgPrintf("STZ ");
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disPrintf(disassembly.inst, "STZ");
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STR(addr, 0);
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}
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#endif // __6502_INSTR_LOAD_STORE_H__
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@ -136,5 +136,75 @@ INLINE void SEI() {
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m6502.I = 1;
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}
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/**
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RMB SMB - Reset or Set Memory Bit
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RMB and SMB clear (RMB) or set (SMB) the specified bit in the specified zero page location,
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and can be used in conjuction with the BBR and BBS instructions. Again, note that as with BBR and TRB,
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the term reset in RMB is used to mean clear.
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The function of RMB and SMB is very similar to the function of TRB and TSB, except that RMB and SMB
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can clear or set only one zero page bit, whereas TRB and TSB can clear or set any number of bits. Also,
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only zero page addressing is available with RMB and SMB, whereas zero page and absolute addressing
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are available for both TRB and TSB. As a result, RMB and SMB do not offer much that isn't already available
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with TRB and TSB (which are available on 65C02s from all manufacturers). The main advantages are that
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RMB and SMB, unlike TRB and TSB, do not use the accumulator, leaving it available, and do not affect any flags.
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However, it is worth noting that it is rarely useful to preserve the value of the Z (zero) flag (the only flag affected by
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TRB and TSB), unlike other flags (such as the carry).
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Like BBR and BBS, the bit to test is typically specified as part of the instruction name rather than the operand, i.e.
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Flags affected: none
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OP LEN CYC MODE FLAGS SYNTAX
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-- --- --- ---- ----- ------
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07 2 5 zp ........ RMB0 $12
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17 2 5 zp ........ RMB1 $12
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27 2 5 zp ........ RMB2 $12
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37 2 5 zp ........ RMB3 $12
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47 2 5 zp ........ RMB4 $12
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57 2 5 zp ........ RMB5 $12
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67 2 5 zp ........ RMB6 $12
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77 2 5 zp ........ RMB7 $12
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87 2 5 zp ........ SMB0 $12
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97 2 5 zp ........ SMB1 $12
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A7 2 5 zp ........ SMB2 $12
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B7 2 5 zp ........ SMB3 $12
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C7 2 5 zp ........ SMB4 $12
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D7 2 5 zp ........ SMB5 $12
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E7 2 5 zp ........ SMB6 $12
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F7 2 5 zp ........ SMB7 $12
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**/
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#define RMB(n) INLINE void RMB##n( uint8_t zpg ) { \
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dbgPrintf("RMB"#n" "); \
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disPrintf(disassembly.inst, "RMB"#n); \
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WRLOMEM[zpg] &= ~(1 << n); \
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}
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RMB(0)
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RMB(1)
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RMB(2)
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RMB(3)
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RMB(4)
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RMB(5)
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RMB(6)
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RMB(7)
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#define SMB(n) INLINE void SMB##n( uint8_t zpg ) { \
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dbgPrintf("SMB"#n" "); \
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disPrintf(disassembly.inst, "SMB"#n); \
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WRLOMEM[zpg] |= (1 << n); \
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}
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SMB(0)
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SMB(1)
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SMB(2)
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SMB(3)
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SMB(4)
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SMB(5)
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SMB(6)
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SMB(7)
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#endif // __6502_INSTR_SET_CLR_H__
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@ -40,7 +40,7 @@
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absolute,X ASL oper,X 1E 3 7
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**/
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INLINE void _ASL( uint16_t addr ) {
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m6502.C = WRLOMEM[addr] & 0x80;
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m6502.C = memread(addr) & 0x80;
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set_flags_NZ( WRLOMEM[addr] <<= 1 );
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}
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INLINE void ASL( uint16_t addr ) {
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@ -63,6 +63,38 @@ INLINE void PHA() {
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PUSH( m6502.A );
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}
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/**
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PHX Push index X on Stack
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push X N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied PHX 48 1 3
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**/
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INLINE void PHX() {
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dbgPrintf("PHX %02X ", m6502.X);
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disPrintf(disassembly.inst, "PHX");
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PUSH( m6502.X );
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}
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/**
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PHY Push index Y on Stack
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push Y N Z C I D V
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- - - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied PHY 48 1 3
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**/
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INLINE void PHY() {
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dbgPrintf("PHY %02X ", m6502.Y);
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disPrintf(disassembly.inst, "PHY");
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PUSH( m6502.Y );
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}
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/**
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PLA Pull Accumulator from Stack
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@ -80,6 +112,40 @@ INLINE void PLA() {
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set_flags_NZ( m6502.A );
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}
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/**
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PLX Pull index X from Stack
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pull X N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied PLX 68 1 4
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**/
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INLINE void PLX() {
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m6502.X = POP();
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dbgPrintf("PLX %02X ", m6502.X);
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disPrintf(disassembly.inst, "PLX");
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set_flags_NZ( m6502.X );
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}
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/**
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PLY Pull index Y from Stack
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pull Y N Z C I D V
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+ + - - - -
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addressing assembler opc bytes cyles
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--------------------------------------------
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implied PLY 68 1 4
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**/
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INLINE void PLY() {
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m6502.Y = POP();
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dbgPrintf("PLY %02X ", m6502.Y);
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disPrintf(disassembly.inst, "PLY");
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set_flags_NZ( m6502.Y );
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}
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/**
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PHP Push Processor Status on Stack
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