BugFix: ZeroPage Memory

src/cpu/6502_C.h

@@ -92,15 +92,15 @@ case 0x7C: JMP( addr_ind_ind_X()); return 6; // abs_addr_X() ); return 6;
         case 0xFA: PLX(); return 4;                                     // PLX
 
     // STZ - STore Zero
-        case 0x64: STZ( addr_zp() ); return 3;                          // STZ zpg
+        case 0x64: STZ_zp( addr_zp() ); return 3;                       // STZ zpg
-        case 0x74: STZ( addr_zp_X() ); return 4;                        // STZ zpg,X
+        case 0x74: STZ_zp( addr_zp_X() ); return 4;                     // STZ zpg,X
         case 0x9C: STZ( addr_abs() ); return 4;                         // STZ abs
         case 0x9E: STZ( addr_abs_X() ); return 5;                       // STZ abs,X
 
     // TRB - Test and Reset Bits
-        case 0x04: TSB( addr_zp() ); return 5;                          // TSB zpg
+        case 0x04: TSB_zp( addr_zp() ); return 5;                       // TSB zpg
         case 0x0C: TSB( addr_abs() ); return 6;                         // TSB abs
-        case 0x14: TRB( addr_zp() ); return 5;                          // TRB zpg
+        case 0x14: TRB_zp( addr_zp() ); return 5;                       // TRB zpg
         case 0x1C: TRB( addr_abs() ); return 6;                         // TRB abs
 
 

src/cpu/6502_std.h

@@ -1,4 +1,5 @@
 //
+//
 //  6502_std.h
 //  A2Mac
 //
@@ -35,7 +36,7 @@
         case 0x01: ORA( src_X_ind() ); return 6;                       // ORA X,ind
         
         case 0x05: ORA( src_zp() ); return 3;                          // ORA zpg
-        case 0x06: ASL( addr_zp() ); return 5;                         // ASL zpg
+        case 0x06: ASL_zp( addr_zp() ); return 5;                      // ASL zpg
         
         case 0x08: PHP(); return 3;                                    // PHP
         case 0x09: ORA( imm() ); return 2;                             // ORA imm
@@ -48,7 +49,7 @@
         case 0x11: ORA( src_ind_Y() ); return 5;                       // ORA ind,Y
 
         case 0x15: ORA( src_zp_X() ); return 4;                        // ORA zpg,X
-        case 0x16: ASL( addr_zp_X() ); return 6;                       // ASL zpg,X
+        case 0x16: ASL_zp( addr_zp_X() ); return 6;                    // ASL zpg,X
 
         case 0x18: CLC(); return 2;                                    // CLC
         case 0x19: ORA( src_abs_Y() ); return 4+1;                       // ORA abs,Y
@@ -61,7 +62,7 @@
 
         case 0x24: BIT( src_zp() ); return 3;                          // BIT zpg
         case 0x25: AND( src_zp() ); return 3;                          // AND zpg
-        case 0x26: ROL( addr_zp() ); return 5;                         // ROL zpg
+        case 0x26: ROL_zp( addr_zp() ); return 5;                      // ROL zpg
 
         case 0x28: PLP(); return 4;                                    // PLP
         case 0x29: AND( imm() ); return 2;                             // AND imm
@@ -75,7 +76,7 @@
         case 0x31: AND( src_ind_Y() ); return 5;                       // AND ind,Y
 
         case 0x35: AND( src_zp_X() ); return 4;                        // AND zpg,X
-        case 0x36: ROL( addr_zp_X() ); return 6;                       // ROL zpg,X
+        case 0x36: ROL_zp( addr_zp_X() ); return 6;                    // ROL zpg,X
 
         case 0x38: SEC(); return 2;                                    // SEC
         case 0x39: AND( src_abs_Y() ); return 4+1;                     // AND abs,Y
@@ -87,7 +88,7 @@
         case 0x41: EOR( src_X_ind() ); return 6;                       // EOR X,ind
 
         case 0x45: EOR( src_zp() ); return 3;                          // EOR zpg
-        case 0x46: LSR( addr_zp() ); return 5;                         // LSR zpg
+        case 0x46: LSR_zp( addr_zp() ); return 5;                      // LSR zpg
 
         case 0x48: PHA(); return 3;                                    // PHA
         case 0x49: EOR( imm() ); return 2;                             // EOR imm
@@ -101,7 +102,7 @@
         case 0x51: EOR( src_ind_Y() ); return 5;                       // EOR ind,Y
 
         case 0x55: EOR( src_zp_X() ); return 4;                        // AND zpg,X
-        case 0x56: LSR( addr_zp_X() ); return 6;                       // LSR zpg,X
+        case 0x56: LSR_zp( addr_zp_X() ); return 6;                    // LSR zpg,X
 
         case 0x58: CLI(); return 2;                                    // CLI
         case 0x59: EOR( src_abs_Y() ); return 4+1;                     // EOR abs,Y
@@ -113,7 +114,7 @@
         case 0x61: ADC( src_X_ind() ); return 6;                       // ADC X,ind
 
         case 0x65: ADC( src_zp() ); return 3;                          // ADC zpg
-        case 0x66: ROR( addr_zp() ); return 5;                         // ROR zpg
+        case 0x66: ROR_zp( addr_zp() ); return 5;                      // ROR zpg
 
         case 0x68: PLA(); return 4;                                    // PLA
         case 0x69: ADC( imm() ); return 2;                             // ADC imm
@@ -127,7 +128,7 @@
         case 0x71: ADC( src_ind_Y() ); return 5;                       // ADC ind,Y
 
         case 0x75: ADC( src_zp_X() ); return 4;                        // ADC zpg,X
-        case 0x76: ROR( addr_zp_X() ); return 6;                       // ROR zpg,X
+        case 0x76: ROR_zp( addr_zp_X() ); return 6;                    // ROR zpg,X
 
         case 0x78: SEI(); return 2;                                    // SEI
         case 0x79: ADC( src_abs_Y() ); return 4+1;                     // ADC abs,Y
@@ -137,9 +138,9 @@
 
         case 0x81: STA( addr_ind_X() ) ; return 6;                     // STA X,ind
 
-        case 0x84: STY( addr_zp() ); return 3;                         // STY zpg
+        case 0x84: STY_zp( addr_zp() ); return 3;                         // STY zpg
-        case 0x85: STA( addr_zp() ); return 3;                         // STA zpg
+        case 0x85: STA_zp( addr_zp() ); return 3;                         // STA zpg
-        case 0x86: STX( addr_zp() ); return 3;                         // STX zpg
+        case 0x86: STX_zp( addr_zp() ); return 3;                         // STX zpg
 
         case 0x88: DEY(); return 2;                                    // DEY
 
@@ -152,9 +153,9 @@
         case 0x90: BCC( rel_addr() ); return 2;                        // BCC rel
         case 0x91: STA( addr_ind_Y() ); return 6;                      // STA ind,Y
 
-        case 0x94: STY( addr_zp_X() ); return 4;                       // STY zpg,X
+        case 0x94: STY_zp( addr_zp_X() ); return 4;                       // STY zpg,X
-        case 0x95: STA( addr_zp_X() ); return 4;                       // STA zpg,X
+        case 0x95: STA_zp( addr_zp_X() ); return 4;                       // STA zpg,X
-        case 0x96: STX( addr_zp_Y() ); return 4;                       // STX zpg,Y
+        case 0x96: STX_zp( addr_zp_Y() ); return 4;                       // STX zpg,Y
 
         case 0x98: TYA(); return 2;                                    // TYA
         case 0x99: STA( addr_abs_Y() ); return 5;                      // STA abs,Y
@@ -198,7 +199,7 @@
 
         case 0xC4: CPY( src_zp() ); return 3;                          // CPY zpg
         case 0xC5: CMP( src_zp() ); return 3;                          // CMP zpg
-        case 0xC6: DEC( addr_zp() ); return 5;                         // DEC zpg
+        case 0xC6: DEC_zp( addr_zp() ); return 5;                      // DEC zpg
 
         case 0xC8: INY(); return 2;                                    // INY
         case 0xC9: CMP( imm() ); return 2;                             // CMP imm
@@ -212,7 +213,7 @@
         case 0xD1: CMP( src_ind_Y() ); return 5;                       // CMP ind,Y
 
         case 0xD5: CMP( src_zp_X() ); return 4;                        // CMP zpg,X
-        case 0xD6: DEC( addr_zp_X() ); return 6;                       // DEC zpg,X
+        case 0xD6: DEC_zp( addr_zp_X() ); return 6;                    // DEC zpg,X
 
         case 0xD8: CLD(); return 2;                                    // CLD
         case 0xD9: CMP( src_abs_Y() ); return 4;                       // CMP abs,Y
@@ -225,7 +226,7 @@
 
         case 0xE4: CPX( src_zp() ); return 3;                          // CPX zpg
         case 0xE5: SBC( src_zp() ); return 3;                          // SBC zpg
-        case 0xE6: INC( addr_zp() ); return 5;                         // INC zpg
+        case 0xE6: INC_zp( addr_zp() ); return 5;                      // INC zpg
 
         case 0xE8: INX(); return 2;                                    // INX
         case 0xE9: SBC( imm() ); return 2;                             // SBC imm
@@ -239,7 +240,7 @@
         case 0xF1: SBC( src_ind_Y() ); return 5;                       // SBC ind,Y
 
         case 0xF5: SBC( src_zp_X() ); return 4;                        // SBC zpg,X
-        case 0xF6: INC( addr_zp_X() ); return 6;                       // INC zpg,X
+        case 0xF6: INC_zp( addr_zp_X() ); return 6;                    // INC zpg,X
 
         case 0xF8: SED(); return 2;                                    // SED
         case 0xF9: SBC( src_abs_Y() ); return 4+1;                       // SBC abs,Y

src/cpu/instructions/6502_instr_inc_dec.h

@@ -39,10 +39,21 @@
  absolute,X    INC oper,X    FE    3     7
 **/
 #ifndef DISASSEMBLER
+INSTR void _INC_zp( uint16_t addr ) {
+    set_flags_NZ( ++(WRZEROPG[addr]) );
+}
 INSTR void _INC( uint16_t addr ) {
     set_flags_NZ( ++(WRLOMEM[addr]) );
 }
 #endif
+INSTR void INC_zp( uint16_t addr ) {
+    disPrintf(disassembly.inst, "INC");
+
+#ifndef DISASSEMBLER
+    _INC_zp(addr);
+#endif
+}
+#endif
 INSTR void INC( uint16_t addr ) {
     disPrintf(disassembly.inst, "INC");
 
@@ -125,10 +136,20 @@ INSTR void INA() {
  absolute,X    DEC oper,X    DE    3     7
 **/
 #ifndef DISASSEMBLER
+INSTR void _DEC_zp( uint16_t addr ) {
+    set_flags_NZ( --(WRZEROPG[addr]) );
+}
 INSTR void _DEC( uint16_t addr ) {
     set_flags_NZ( --(WRLOMEM[addr]) );
 }
 #endif
+INSTR void DEC_zp( uint16_t addr ) {
+    disPrintf(disassembly.inst, "DEC");
+
+#ifndef DISASSEMBLER
+    _DEC_zp(addr);
+#endif
+}
 INSTR void DEC( uint16_t addr ) {
     disPrintf(disassembly.inst, "DEC");
 

src/cpu/instructions/6502_instr_load_store.h

@@ -141,6 +141,13 @@ INSTR void STA( uint16_t addr ) {
     STR(addr, m6502.A);
 #endif
 }
+INSTR void STA_zp( uint8_t addr ) {
+    dbgPrintf("STA ");
+    disPrintf(disassembly.inst, "STA");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.A);
+#endif
+}
 
 /**
  STX  Store Index X in Memory
@@ -161,6 +168,13 @@ INSTR void STX( uint16_t addr ) {
     STR(addr, m6502.X);
 #endif
 }
+INSTR void STX_zp( uint8_t addr ) {
+    dbgPrintf("STX ");
+    disPrintf(disassembly.inst, "STX");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.X);
+#endif
+}
 
 /**
  STY  Sore Index Y in Memory
@@ -181,6 +195,13 @@ INSTR void STY( uint16_t addr ) {
     STR(addr, m6502.Y);
 #endif
 }
+INSTR void STY_zp( uint18_t addr ) {
+    dbgPrintf("STY ");
+    disPrintf(disassembly.inst, "STY");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.Y);
+#endif
+}
 
 /**
  STZ  Store Zero (0) in Memory
@@ -202,6 +223,13 @@ INSTR void STZ( uint16_t addr ) {
     STR(addr, 0);
 #endif
 }
+INSTR void STZ_zp( uint8_t addr ) {
+    dbgPrintf("STZ ");
+    disPrintf(disassembly.inst, "STZ");
+#ifndef DISASSEMBLER
+    STR_zp(addr, 0);
+#endif
+}
 
 #endif // __6502_INSTR_LOAD_STORE_H__
 

src/cpu/instructions/6502_instr_shift_rotate.h

@@ -86,6 +86,15 @@ INSTR void LSR( uint16_t addr ) {
     set_flags_NZ( WRLOMEM[addr] >>= 1 );
 #endif
 }
+INSTR void LSR_zp( uint16_t addr ) {
+    dbgPrintf("LSR ");
+    disPrintf(disassembly.inst, "LSR");
+
+#ifndef DISASSEMBLER
+    m6502.C = WRZEROPG[addr] & 1;
+    set_flags_NZ( WRZEROPG[addr] >>= 1 );
+#endif
+}
 INSTR void LSRA() {
     dbgPrintf("LSR ");
     disPrintf(disassembly.inst, "LSR");
@@ -117,6 +126,12 @@ INSTR void _ROL( uint16_t addr ) {
     WRLOMEM[addr] <<= 1;
     set_flags_NZ( WRLOMEM[addr] |= C );
 }
+INSTR void _ROL_zp( uint16_t addr ) {
+    uint8_t C = m6502.C != 0;
+    m6502.C = WRZEROPG[addr] & 0x80;
+    WRZEROPG[addr] <<= 1;
+    set_flags_NZ( WRZEROPG[addr] |= C );
+}
 #endif
 INSTR void ROL( uint16_t addr ) {
     dbgPrintf("ROL ");
@@ -126,6 +141,14 @@ INSTR void ROL( uint16_t addr ) {
     _ROL(addr);
 #endif
 }
+INSTR void ROL_zp( uint16_t addr ) {
+    dbgPrintf("ROL ");
+    disPrintf(disassembly.inst, "ROL");
+
+#ifndef DISASSEMBLER
+    _ROL_zp(addr);
+#endif
+}
 INSTR void ROLA() {
     dbgPrintf("ROL ");
     disPrintf(disassembly.inst, "ROL");
@@ -159,6 +182,12 @@ INSTR void _ROR( uint16_t addr ) {
     WRLOMEM[addr] >>= 1;
     set_flags_NZ( WRLOMEM[addr] |= C  << 7 );
 }
+INSTR void _ROR_zp( uint16_t addr ) {
+    uint8_t C = m6502.C != 0;
+    m6502.C = WRZEROPG[addr] & 1;
+    WRZEROPG[addr] >>= 1;
+    set_flags_NZ( WRZEROPG[addr] |= C  << 7 );
+}
 #endif
 INSTR void ROR( uint16_t addr ) {
     dbgPrintf("ROR ");
@@ -168,6 +197,14 @@ INSTR void ROR( uint16_t addr ) {
     _ROR(addr);
 #endif
 }
+INSTR void ROR_zp( uint16_t addr ) {
+    dbgPrintf("ROR ");
+    disPrintf(disassembly.inst, "ROR");
+    
+#ifndef DISASSEMBLER
+    _ROR_zp(addr);
+#endif
+}
 INSTR void RORA() {
     dbgPrintf("ROR ");
     disPrintf(disassembly.inst, "ROR");

src/cpu/jit/instructions/6502_instr_compare_test.h

@@ -88,6 +88,15 @@ INSTR void TRB( uint16_t addr ) {
     WRLOMEM[addr] &= ~m6502.A;
 #endif
 }
+INSTR void TRB_zp( uint16_t addr ) {
+    dbgPrintf("TRB(%02X) ", src);
+    disPrintf(disassembly.inst, "TRB");
+
+#ifndef DISASSEMBLER
+    set_flags_Z( WRZEROPG[addr] & m6502.A );
+    WRZEROPG[addr] &= ~m6502.A;
+#endif
+}
 
 /**
  TSB - Test and Set Bits
@@ -118,6 +127,15 @@ INSTR void TSB( uint16_t addr ) {
     WRLOMEM[addr] |= m6502.A;
 #endif
 }
+INSTR void TSB_zp( uint16_t addr ) {
+    dbgPrintf("TSB(%02X) ", src);
+    disPrintf(disassembly.inst, "TSB");
+
+#ifndef DISASSEMBLER
+    set_flags_Z( WRZEROPG[addr] & m6502.A );
+    WRZEROPG[addr] |= m6502.A;
+#endif
+}
 
 /**
  CMP  Compare Memory with Accumulator

src/cpu/jit/instructions/6502_instr_inc_dec.h

@@ -39,6 +39,18 @@
  absolute,X    INC oper,X    FE    3     7
 **/
 #ifndef DISASSEMBLER
+INSTR void _INC_zp( uint16_t addr ) {
+    set_flags_NZ( ++(WRZEROPG[addr]) );
+}
+#endif
+INSTR void INC_zp( uint16_t addr ) {
+    disPrintf(disassembly.inst, "INC");
+
+#ifndef DISASSEMBLER
+    _INC_zp(addr);
+#endif
+}
+#ifndef DISASSEMBLER
 INSTR void _INC( uint16_t addr ) {
     set_flags_NZ( ++(WRLOMEM[addr]) );
 }
@@ -125,10 +137,20 @@ INSTR void INA(void) {
  absolute,X    DEC oper,X    DE    3     7
 **/
 #ifndef DISASSEMBLER
+INSTR void _DEC_zp( uint16_t addr ) {
+    set_flags_NZ( --(WRZEROPG[addr]) );
+}
 INSTR void _DEC( uint16_t addr ) {
     set_flags_NZ( --(WRLOMEM[addr]) );
 }
 #endif
+INSTR void DEC_zp( uint16_t addr ) {
+    disPrintf(disassembly.inst, "DEC");
+
+#ifndef DISASSEMBLER
+    _DEC_zp(addr);
+#endif
+}
 INSTR void DEC( uint16_t addr ) {
     disPrintf(disassembly.inst, "DEC");
 

src/cpu/jit/instructions/6502_instr_load_store.h

@@ -117,6 +117,12 @@ INSTR void STR( uint16_t addr, uint8_t src ) {
     _memwrite(addr, src);
 #endif
 }
+INSTR void STR_zp( uint8_t addr, uint8_t src ) {
+    dbgPrintf("STR [%04X], %02X ", addr, src );
+#ifndef DISASSEMBLER
+    _memwrite8_zp(addr, src);
+#endif
+}
 
 /**
  STA  Store Accumulator in Memory
@@ -141,6 +147,13 @@ INSTR void STA( uint16_t addr ) {
     STR(addr, m6502.A);
 #endif
 }
+INSTR void STA_zp( uint8_t addr ) {
+    dbgPrintf("STA ");
+    disPrintf(disassembly.inst, "STA");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.A);
+#endif
+}
 
 /**
  STX  Store Index X in Memory
@@ -161,6 +174,13 @@ INSTR void STX( uint16_t addr ) {
     STR(addr, m6502.X);
 #endif
 }
+INSTR void STX_zp( uint8_t addr ) {
+    dbgPrintf("STX ");
+    disPrintf(disassembly.inst, "STX");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.X);
+#endif
+}
 
 /**
  STY  Sore Index Y in Memory
@@ -181,6 +201,13 @@ INSTR void STY( uint16_t addr ) {
     STR(addr, m6502.Y);
 #endif
 }
+INSTR void STY_zp( uint8_t addr ) {
+    dbgPrintf("STY ");
+    disPrintf(disassembly.inst, "STY");
+#ifndef DISASSEMBLER
+    STR_zp(addr, m6502.Y);
+#endif
+}
 
 /**
  STZ  Store Zero (0) in Memory
@@ -202,6 +229,13 @@ INSTR void STZ( uint16_t addr ) {
     STR(addr, 0);
 #endif
 }
+INSTR void STZ_zp( uint8_t addr ) {
+    dbgPrintf("STZ ");
+    disPrintf(disassembly.inst, "STZ");
+#ifndef DISASSEMBLER
+    STR_zp(addr, 0);
+#endif
+}
 
 #endif // __6502_INSTR_LOAD_STORE_H__
 

src/cpu/jit/instructions/6502_instr_set_clr.h

@@ -193,7 +193,7 @@ INSTR void SEI(void) {
 #define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
     dbgPrintf("RMB"#n" "); \
     disPrintf(disassembly.inst, "RMB"#n); \
-    WRLOMEM[zpg] &= ~(1 << n); \
+    WRZEROPG[zpg] &= ~(1 << n); \
 }
 #else
 #define RMB(n) INSTR void RMB##n( uint8_t zpg ) { \
@@ -216,7 +216,7 @@ INSTR void SEI(void) {
 #define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \
     dbgPrintf("SMB"#n" "); \
     disPrintf(disassembly.inst, "SMB"#n); \
-    WRLOMEM[zpg] |= (1 << n); \
+    WRZEROPG[zpg] |= (1 << n); \
 }
 #else
 #define SMB(n) INSTR void SMB##n( uint8_t zpg ) { \

src/cpu/jit/instructions/6502_instr_shift_rotate.h

@@ -44,6 +44,10 @@ INSTR void _ASL( uint16_t addr ) {
     m6502.C = _memread(addr) & 0x80;
     set_flags_NZ( WRLOMEM[addr] <<= 1 );
 }
+INSTR void _ASL_zp( uint16_t addr ) {
+    m6502.C = _memread(addr) & 0x80;
+    set_flags_NZ( WRZEROPG[addr] <<= 1 );
+}
 #endif
 INSTR void ASL( uint16_t addr ) {
     dbgPrintf("ASL ");
@@ -53,6 +57,14 @@ INSTR void ASL( uint16_t addr ) {
     _ASL(addr);
 #endif
 }
+INSTR void ASL_zp( uint16_t addr ) {
+    dbgPrintf("ASL ");
+    disPrintf(disassembly.inst, "ASL");
+
+#ifndef DISASSEMBLER
+    _ASL_zp(addr);
+#endif
+}
 INSTR void ASLA(void) {
     dbgPrintf("ASL ");
     disPrintf(disassembly.inst, "ASL");
@@ -86,6 +98,15 @@ INSTR void LSR( uint16_t addr ) {
     set_flags_NZ( WRLOMEM[addr] >>= 1 );
 #endif
 }
+INSTR void LSR_zp( uint16_t addr ) {
+    dbgPrintf("LSR ");
+    disPrintf(disassembly.inst, "LSR");
+
+#ifndef DISASSEMBLER
+    m6502.C = WRZEROPG[addr] & 1;
+    set_flags_NZ( WRZEROPG[addr] >>= 1 );
+#endif
+}
 INSTR void LSRA(void) {
     dbgPrintf("LSR ");
     disPrintf(disassembly.inst, "LSR");
@@ -117,6 +138,12 @@ INSTR void _ROL( uint16_t addr ) {
     WRLOMEM[addr] <<= 1;
     set_flags_NZ( WRLOMEM[addr] |= C );
 }
+INSTR void _ROL_zp( uint16_t addr ) {
+    uint8_t C = m6502.C != 0;
+    m6502.C = WRZEROPG[addr] & 0x80;
+    WRZEROPG[addr] <<= 1;
+    set_flags_NZ( WRZEROPG[addr] |= C );
+}
 #endif
 INSTR void ROL( uint16_t addr ) {
     dbgPrintf("ROL ");
@@ -126,6 +153,14 @@ INSTR void ROL( uint16_t addr ) {
     _ROL(addr);
 #endif
 }
+INSTR void ROL_zp( uint16_t addr ) {
+    dbgPrintf("ROL ");
+    disPrintf(disassembly.inst, "ROL");
+
+#ifndef DISASSEMBLER
+    _ROL_zp(addr);
+#endif
+}
 INSTR void ROLA(void) {
     dbgPrintf("ROL ");
     disPrintf(disassembly.inst, "ROL");
@@ -159,6 +194,12 @@ INSTR void _ROR( uint16_t addr ) {
     WRLOMEM[addr] >>= 1;
     set_flags_NZ( WRLOMEM[addr] |= C  << 7 );
 }
+INSTR void _ROR_zp( uint16_t addr ) {
+    uint8_t C = m6502.C != 0;
+    m6502.C = WRZEROPG[addr] & 1;
+    WRZEROPG[addr] >>= 1;
+    set_flags_NZ( WRZEROPG[addr] |= C  << 7 );
+}
 #endif
 INSTR void ROR( uint16_t addr ) {
     dbgPrintf("ROR ");
@@ -168,6 +209,14 @@ INSTR void ROR( uint16_t addr ) {
     _ROR(addr);
 #endif
 }
+INSTR void ROR_zp( uint16_t addr ) {
+    dbgPrintf("ROR ");
+    disPrintf(disassembly.inst, "ROR");
+    
+#ifndef DISASSEMBLER
+    _ROR_zp(addr);
+#endif
+}
 INSTR void RORA(void) {
     dbgPrintf("ROR ");
     disPrintf(disassembly.inst, "ROR");

src/dev/mem/mmio.c

@@ -77,7 +77,7 @@ MEMcfg_t MEMcfg = INIT_MEMCFG;
 MEMcfg_t newMEMcfg = INIT_MEMCFG;
 
 
-const uint8_t * const shadowZPSTCKMEM = Apple2_64K_MEM;
+uint8_t * shadowZPSTCKMEM = Apple2_64K_MEM;
 const uint8_t * currentZPSTCKMEM = Apple2_64K_RAM;
 const uint8_t * const shadowLowMEM = Apple2_64K_MEM + 0x200;
 const uint8_t * currentLowRDMEM = Apple2_64K_RAM + 0x200;
@@ -1008,6 +1008,9 @@ INLINE uint8_t check_mem_wr_bp(uint16_t addr) {
 /**
  Naive implementation of RAM read from address
  **/
+INLINE uint8_t memread8_zp( uint16_t addr ) {
+    return shadowZPSTCKMEM[addr];
+}
 INLINE uint8_t memread8_low( uint16_t addr ) {
     return Apple2_64K_MEM[addr];
 }
@@ -1018,11 +1021,17 @@ INLINE uint8_t memread8( uint16_t addr ) {
     if (addr >= 0xC000) {
         return memread8_high(addr);
     }
-    return memread8_low(addr);
+    if (addr >= 0x200) {
+        return memread8_low(addr);
+    }
+    return memread8_zp(addr);
 }
 /**
  Naive implementation of RAM read from address
  **/
+INLINE uint16_t memread16_zp( uint16_t addr ) {
+    return * (uint16_t*) ( shadowZPSTCKMEM + addr );
+}
 INLINE uint16_t memread16_low( uint16_t addr ) {
     return * (uint16_t*) ( Apple2_64K_MEM + addr );
 
@@ -1054,12 +1063,15 @@ INLINE uint8_t _memread( uint16_t addr ) {
         if (addr < 0xC100) {
             return ioRead(addr);
         }
-        
 //        return memread8_paged(addr);
         return memread8_high(addr);
     }
+    if (addr >= 0x200) {
+        return memread8_low(addr);
+    }
+
 //    return memread8_paged(addr);
-    return memread8_low(addr);
+    return memread8_zp(addr);
     
 //    return memread8(addr);
 }
@@ -1074,8 +1086,12 @@ INLINE uint8_t _memread_dis( uint16_t addr ) {
 //        return memread8_paged(addr);
         return memread8_high(addr);
     }
+    if (addr >= 0x200) {
+        return memread8_low(addr);
+    }
+
 //    return memread8_paged(addr);
-    return memread8_low(addr);
+    return memread8_zp(addr);
 
 //    return memread8(addr);
 }
@@ -1101,6 +1117,9 @@ INLINE uint8_t _memread_dis( uint16_t addr ) {
  Naive implementation of RAM write to address
  **/
 
+INLINE void _memwrite8_zp( uint16_t addr, uint8_t data ) {
+    shadowZPSTCKMEM[addr] = data;
+}
 INLINE void _memwrite8_low( uint16_t addr, uint8_t data ) {
     if ((addr >= 0x400) && (addr < 0x800)) {
         if ((data == 0x00) || (data == 0xFF)) {
@@ -1133,10 +1152,14 @@ INLINE void _memwrite( uint16_t addr, uint8_t data ) {
             memwrite8_high(addr, data);
         }
     }
-    else {
+    else if (addr >= 0x200) {
         // RAM
         memwrite8_low(addr, data);
     }
+    else {
+        // RAM
+        memwrite8_zp(addr, data);
+    }
 }
 
 /**
@@ -1350,13 +1373,13 @@ INLINE uint8_t _addr_zp_dis(void) {
     return _fetch_dis();
 }
 INLINE uint8_t _src_zp(void) {
-    return memread8_low(_addr_zp());
+    return memread8(_addr_zp());
 }
 INLINE uint8_t _src_zp_dbg(void) {
     return _memread_dbg(_addr_zp_dbg());
 }
 INLINE uint8_t _src_zp_dis(void) {
-    return memread8_low(_addr_zp_dis());
+    return memread8(_addr_zp_dis());
 }
 //INLINE uint8_t * dest_zp() {
 //    return WRLOMEM + addr_zp();
@@ -1514,13 +1537,13 @@ INLINE uint8_t _addr_zp_X_dis(void) {
     return _fetch_dis() + m6502.X;
 }
 INLINE uint8_t _src_zp_X(void) {
-    return memread8_low(_addr_zp_X());
+    return memread8(_addr_zp_X());
 }
 INLINE uint8_t _src_zp_X_dbg(void) {
     return _memread_dbg(_addr_zp_X());
 }
 INLINE uint8_t _src_zp_X_dis(void) {
-    return memread8_low(_addr_zp_X_dis());
+    return memread8(_addr_zp_X_dis());
 }
 //INLINE uint8_t * dest_zp_X() {
 //    return WRLOMEM + addr_zp_X();
@@ -1545,13 +1568,13 @@ INLINE uint8_t _addr_zp_Y_dis(void) {
     return _fetch_dis() + m6502.Y;
 }
 INLINE uint8_t _src_zp_Y(void) {
-    return memread8_low(_addr_zp_Y());
+    return memread8(_addr_zp_Y());
 }
 INLINE uint8_t _src_zp_Y_dbg(void) {
     return _memread_dbg(_addr_zp_Y());
 }
 INLINE uint8_t _src_zp_Y_dis(void) {
-    return memread8_low(_addr_zp_Y_dis());
+    return memread8(_addr_zp_Y_dis());
 }
 //INLINE uint8_t * dest_zp_Y() {
 //    return WRLOMEM + addr_zp_Y();
@@ -1563,7 +1586,7 @@ void auxMemorySelect( MEMcfg_t newMEMcfg ) {
     uint8_t * newWriteMEM = currentLowWRMEM;
 
     // TODO: Check if this is supposed to be the opposite
-    if ( newMEMcfg.is_80STORE ) {
+//    if ( newMEMcfg.is_80STORE ) {
         if ( newMEMcfg.RD_AUX_MEM ) {
             newReadMEM = Apple2_64K_AUX + 0x200;
         }
@@ -1577,11 +1600,11 @@ void auxMemorySelect( MEMcfg_t newMEMcfg ) {
         else {
             newWriteMEM = Apple2_64K_RAM;
         }
-    }
+//    }
-    else {
+//    else {
-        newReadMEM = Apple2_64K_RAM + 0x200;
+//        newReadMEM = Apple2_64K_RAM + 0x200;
-        newWriteMEM = Apple2_64K_RAM;
+//        newWriteMEM = Apple2_64K_RAM;
-    }
+//    }
     
     
     // save old content to shadow memory
@@ -1727,10 +1750,10 @@ void CxMemorySelect( MEMcfg_t newMEMcfg ) {
 void resetMemory(void) {
     newMEMcfg = initMEMcfg;
     
-    WRZEROPG= Apple2_64K_MEM;       // for Write $0000 - $0200 (shadow memory)
+    WRZEROPG = Apple2_64K_MEM;       // for Write $0000 - $0200 (shadow memory)
-    WRLOMEM = Apple2_64K_MEM;       // for Write $0200 - $BFFF (shadow memory)
+    WRLOMEM  = Apple2_64K_MEM;       // for Write $0200 - $BFFF (shadow memory)
-    WRD0MEM = Apple2_Dummy_RAM;     // for writing $D000 - $DFFF
+    WRD0MEM  = Apple2_Dummy_RAM;     // for writing $D000 - $DFFF
-    WRHIMEM = Apple2_Dummy_RAM;     // for writing $E000 - $FFFF
+    WRHIMEM  = Apple2_Dummy_RAM;     // for writing $E000 - $FFFF
     
     auxMemorySelect(MEMcfg);
     CxMemorySelect(MEMcfg);
@@ -1798,7 +1821,8 @@ void setIO ( uint16_t ioaddr, uint8_t val ) {
 }
 
 uint8_t getMEM ( uint16_t addr ) {
-    return Apple2_64K_MEM[addr];
+    return memread8(addr);
+//    return Apple2_64K_MEM[addr];
 }
 
 uint16_t getMEM16 ( uint16_t addr ) {

src/dev/mem/mmio.h

@@ -414,6 +414,7 @@ INLINE uint16_t memread16( uint16_t addr );
 INLINE uint8_t _memread( uint16_t addr );
 INLINE uint8_t _memread_dbg( uint16_t addr );
 INLINE uint8_t _memread_dis( uint16_t addr );
+INLINE void _memwrite8_zp( uint16_t addr, uint8_t data );
 INLINE void _memwrite8_low( uint16_t addr, uint8_t data );
 INLINE void _memwrite8_bank( uint16_t addr, uint8_t data );
 INLINE void _memwrite8_high( uint16_t addr, uint8_t data );
@@ -497,6 +498,7 @@ INLINE uint8_t _src_zp_Y_dis(void);
 #define fetch() _fetch_dis()
 #define fetch16() _fetch16_dis()
 #define memread(addr) _memread_dis(addr)
+#define memwrite8_zp(addr,data)     // do not write anything into the memory while disassembling
 #define memwrite8_low(addr,data)    // do not write anything into the memory while disassembling
 #define memwrite8_bank(addr,data)   // do not write anything into the memory while disassembling
 #define memwrite8_high(addr,data)   // do not write anything into the memory while disassembling
@@ -531,6 +533,7 @@ INLINE uint8_t _src_zp_Y_dis(void);
 #define fetch() _fetch()
 #define fetch16() _fetch16()
 #define memread(addr) _memread_dbg(addr)
+#define memwrite8_zp(addr,data) _memwrite8_zp(addr,data)
 #define memwrite8_low(addr,data) _memwrite8_low(addr,data)
 #define memwrite8_bank(addr,data) _memwrite8_bank(addr,data)
 #define memwrite8_high(addr,data) _memwrite8_high(addr,data)
@@ -565,6 +568,7 @@ INLINE uint8_t _src_zp_Y_dis(void);
 #define fetch() _fetch()
 #define fetch16() _fetch16()
 #define memread(addr) _memread(addr)
+#define memwrite8_zp(addr,data) _memwrite8_zp(addr,data)
 #define memwrite8_low(addr,data) _memwrite8_low(addr,data)
 #define memwrite8_bank(addr,data) _memwrite8_bank(addr,data)
 #define memwrite8_high(addr,data) _memwrite8_high(addr,data)